1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
19 See the file COPYING in this distribution for more information.
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
28 * Test Tx checksumming thoroughly
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
49 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
51 #define DRV_NAME "8139cp"
52 #define DRV_VERSION "1.3"
53 #define DRV_RELDATE "Mar 22, 2004"
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/kernel.h>
59 #include <linux/compiler.h>
60 #include <linux/netdevice.h>
61 #include <linux/etherdevice.h>
62 #include <linux/init.h>
63 #include <linux/interrupt.h>
64 #include <linux/pci.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/delay.h>
67 #include <linux/ethtool.h>
68 #include <linux/gfp.h>
69 #include <linux/mii.h>
70 #include <linux/if_vlan.h>
71 #include <linux/crc32.h>
74 #include <linux/tcp.h>
75 #include <linux/udp.h>
76 #include <linux/cache.h>
79 #include <asm/uaccess.h>
81 /* These identify the driver base version and may not be removed. */
82 static char version
[] =
83 DRV_NAME
": 10/100 PCI Ethernet driver v" DRV_VERSION
" (" DRV_RELDATE
")\n";
85 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
86 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
87 MODULE_VERSION(DRV_VERSION
);
88 MODULE_LICENSE("GPL");
90 static int debug
= -1;
91 module_param(debug
, int, 0);
92 MODULE_PARM_DESC (debug
, "8139cp: bitmapped message enable number");
94 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
95 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
96 static int multicast_filter_limit
= 32;
97 module_param(multicast_filter_limit
, int, 0);
98 MODULE_PARM_DESC (multicast_filter_limit
, "8139cp: maximum number of filtered multicast addresses");
100 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
103 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
104 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
105 #define CP_REGS_SIZE (0xff + 1)
106 #define CP_REGS_VER 1 /* version 1 */
107 #define CP_RX_RING_SIZE 64
108 #define CP_TX_RING_SIZE 64
109 #define CP_RING_BYTES \
110 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
111 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
113 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
114 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
115 #define TX_BUFFS_AVAIL(CP) \
116 (((CP)->tx_tail <= (CP)->tx_head) ? \
117 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
118 (CP)->tx_tail - (CP)->tx_head - 1)
120 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
121 #define CP_INTERNAL_PHY 32
123 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
124 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
125 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
126 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
127 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
129 /* Time in jiffies before concluding the transmitter is hung. */
130 #define TX_TIMEOUT (6*HZ)
132 /* hardware minimum and maximum for a single frame's data payload */
133 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
134 #define CP_MAX_MTU 4096
137 /* NIC register offsets */
138 MAC0
= 0x00, /* Ethernet hardware address. */
139 MAR0
= 0x08, /* Multicast filter. */
140 StatsAddr
= 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
141 TxRingAddr
= 0x20, /* 64-bit start addr of Tx ring */
142 HiTxRingAddr
= 0x28, /* 64-bit start addr of high priority Tx ring */
143 Cmd
= 0x37, /* Command register */
144 IntrMask
= 0x3C, /* Interrupt mask */
145 IntrStatus
= 0x3E, /* Interrupt status */
146 TxConfig
= 0x40, /* Tx configuration */
147 ChipVersion
= 0x43, /* 8-bit chip version, inside TxConfig */
148 RxConfig
= 0x44, /* Rx configuration */
149 RxMissed
= 0x4C, /* 24 bits valid, write clears */
150 Cfg9346
= 0x50, /* EEPROM select/control; Cfg reg [un]lock */
151 Config1
= 0x52, /* Config1 */
152 Config3
= 0x59, /* Config3 */
153 Config4
= 0x5A, /* Config4 */
154 MultiIntr
= 0x5C, /* Multiple interrupt select */
155 BasicModeCtrl
= 0x62, /* MII BMCR */
156 BasicModeStatus
= 0x64, /* MII BMSR */
157 NWayAdvert
= 0x66, /* MII ADVERTISE */
158 NWayLPAR
= 0x68, /* MII LPA */
159 NWayExpansion
= 0x6A, /* MII Expansion */
160 Config5
= 0xD8, /* Config5 */
161 TxPoll
= 0xD9, /* Tell chip to check Tx descriptors for work */
162 RxMaxSize
= 0xDA, /* Max size of an Rx packet (8169 only) */
163 CpCmd
= 0xE0, /* C+ Command register (C+ mode only) */
164 IntrMitigate
= 0xE2, /* rx/tx interrupt mitigation control */
165 RxRingAddr
= 0xE4, /* 64-bit start addr of Rx ring */
166 TxThresh
= 0xEC, /* Early Tx threshold */
167 OldRxBufAddr
= 0x30, /* DMA address of Rx ring buffer (C mode) */
168 OldTSD0
= 0x10, /* DMA address of first Tx desc (C mode) */
170 /* Tx and Rx status descriptors */
171 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
172 RingEnd
= (1 << 30), /* End of descriptor ring */
173 FirstFrag
= (1 << 29), /* First segment of a packet */
174 LastFrag
= (1 << 28), /* Final segment of a packet */
175 LargeSend
= (1 << 27), /* TCP Large Send Offload (TSO) */
176 MSSShift
= 16, /* MSS value position */
177 MSSMask
= 0xfff, /* MSS value: 11 bits */
178 TxError
= (1 << 23), /* Tx error summary */
179 RxError
= (1 << 20), /* Rx error summary */
180 IPCS
= (1 << 18), /* Calculate IP checksum */
181 UDPCS
= (1 << 17), /* Calculate UDP/IP checksum */
182 TCPCS
= (1 << 16), /* Calculate TCP/IP checksum */
183 TxVlanTag
= (1 << 17), /* Add VLAN tag */
184 RxVlanTagged
= (1 << 16), /* Rx VLAN tag available */
185 IPFail
= (1 << 15), /* IP checksum failed */
186 UDPFail
= (1 << 14), /* UDP/IP checksum failed */
187 TCPFail
= (1 << 13), /* TCP/IP checksum failed */
188 NormalTxPoll
= (1 << 6), /* One or more normal Tx packets to send */
189 PID1
= (1 << 17), /* 2 protocol id bits: 0==non-IP, */
190 PID0
= (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
194 TxFIFOUnder
= (1 << 25), /* Tx FIFO underrun */
195 TxOWC
= (1 << 22), /* Tx Out-of-window collision */
196 TxLinkFail
= (1 << 21), /* Link failed during Tx of packet */
197 TxMaxCol
= (1 << 20), /* Tx aborted due to excessive collisions */
198 TxColCntShift
= 16, /* Shift, to get 4-bit Tx collision cnt */
199 TxColCntMask
= 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
200 RxErrFrame
= (1 << 27), /* Rx frame alignment error */
201 RxMcast
= (1 << 26), /* Rx multicast packet rcv'd */
202 RxErrCRC
= (1 << 18), /* Rx CRC error */
203 RxErrRunt
= (1 << 19), /* Rx error, packet < 64 bytes */
204 RxErrLong
= (1 << 21), /* Rx error, packet > 4096 bytes */
205 RxErrFIFO
= (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
207 /* StatsAddr register */
208 DumpStats
= (1 << 3), /* Begin stats dump */
210 /* RxConfig register */
211 RxCfgFIFOShift
= 13, /* Shift, to get Rx FIFO thresh value */
212 RxCfgDMAShift
= 8, /* Shift, to get Rx Max DMA value */
213 AcceptErr
= 0x20, /* Accept packets with CRC errors */
214 AcceptRunt
= 0x10, /* Accept runt (<64 bytes) packets */
215 AcceptBroadcast
= 0x08, /* Accept broadcast packets */
216 AcceptMulticast
= 0x04, /* Accept multicast packets */
217 AcceptMyPhys
= 0x02, /* Accept pkts with our MAC as dest */
218 AcceptAllPhys
= 0x01, /* Accept all pkts w/ physical dest */
220 /* IntrMask / IntrStatus registers */
221 PciErr
= (1 << 15), /* System error on the PCI bus */
222 TimerIntr
= (1 << 14), /* Asserted when TCTR reaches TimerInt value */
223 LenChg
= (1 << 13), /* Cable length change */
224 SWInt
= (1 << 8), /* Software-requested interrupt */
225 TxEmpty
= (1 << 7), /* No Tx descriptors available */
226 RxFIFOOvr
= (1 << 6), /* Rx FIFO Overflow */
227 LinkChg
= (1 << 5), /* Packet underrun, or link change */
228 RxEmpty
= (1 << 4), /* No Rx descriptors available */
229 TxErr
= (1 << 3), /* Tx error */
230 TxOK
= (1 << 2), /* Tx packet sent */
231 RxErr
= (1 << 1), /* Rx error */
232 RxOK
= (1 << 0), /* Rx packet received */
233 IntrResvd
= (1 << 10), /* reserved, according to RealTek engineers,
234 but hardware likes to raise it */
236 IntrAll
= PciErr
| TimerIntr
| LenChg
| SWInt
| TxEmpty
|
237 RxFIFOOvr
| LinkChg
| RxEmpty
| TxErr
| TxOK
|
238 RxErr
| RxOK
| IntrResvd
,
240 /* C mode command register */
241 CmdReset
= (1 << 4), /* Enable to reset; self-clearing */
242 RxOn
= (1 << 3), /* Rx mode enable */
243 TxOn
= (1 << 2), /* Tx mode enable */
245 /* C+ mode command register */
246 RxVlanOn
= (1 << 6), /* Rx VLAN de-tagging enable */
247 RxChkSum
= (1 << 5), /* Rx checksum offload enable */
248 PCIDAC
= (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
249 PCIMulRW
= (1 << 3), /* Enable PCI read/write multiple */
250 CpRxOn
= (1 << 1), /* Rx mode enable */
251 CpTxOn
= (1 << 0), /* Tx mode enable */
253 /* Cfg9436 EEPROM control register */
254 Cfg9346_Lock
= 0x00, /* Lock ConfigX/MII register access */
255 Cfg9346_Unlock
= 0xC0, /* Unlock ConfigX/MII register access */
257 /* TxConfig register */
258 IFG
= (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
259 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
261 /* Early Tx Threshold register */
262 TxThreshMask
= 0x3f, /* Mask bits 5-0 */
263 TxThreshMax
= 2048, /* Max early Tx threshold */
265 /* Config1 register */
266 DriverLoaded
= (1 << 5), /* Software marker, driver is loaded */
267 LWACT
= (1 << 4), /* LWAKE active mode */
268 PMEnable
= (1 << 0), /* Enable various PM features of chip */
270 /* Config3 register */
271 PARMEnable
= (1 << 6), /* Enable auto-loading of PHY parms */
272 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
273 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
275 /* Config4 register */
276 LWPTN
= (1 << 1), /* LWAKE Pattern */
277 LWPME
= (1 << 4), /* LANWAKE vs PMEB */
279 /* Config5 register */
280 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
281 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
282 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
283 LANWake
= (1 << 1), /* Enable LANWake signal */
284 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
286 cp_norx_intr_mask
= PciErr
| LinkChg
| TxOK
| TxErr
| TxEmpty
,
287 cp_rx_intr_mask
= RxOK
| RxErr
| RxEmpty
| RxFIFOOvr
,
288 cp_intr_mask
= cp_rx_intr_mask
| cp_norx_intr_mask
,
291 static const unsigned int cp_rx_config
=
292 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) |
293 (RX_DMA_BURST
<< RxCfgDMAShift
);
301 struct cp_dma_stats
{
317 struct cp_extra_stats
{
318 unsigned long rx_frags
;
323 struct net_device
*dev
;
327 struct napi_struct napi
;
329 struct pci_dev
*pdev
;
333 struct cp_extra_stats cp_stats
;
335 unsigned rx_head ____cacheline_aligned
;
337 struct cp_desc
*rx_ring
;
338 struct sk_buff
*rx_skb
[CP_RX_RING_SIZE
];
340 unsigned tx_head ____cacheline_aligned
;
342 struct cp_desc
*tx_ring
;
343 struct sk_buff
*tx_skb
[CP_TX_RING_SIZE
];
346 unsigned wol_enabled
: 1; /* Is Wake-on-LAN enabled? */
350 struct mii_if_info mii_if
;
353 #define cpr8(reg) readb(cp->regs + (reg))
354 #define cpr16(reg) readw(cp->regs + (reg))
355 #define cpr32(reg) readl(cp->regs + (reg))
356 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
357 #define cpw16(reg,val) writew((val), cp->regs + (reg))
358 #define cpw32(reg,val) writel((val), cp->regs + (reg))
359 #define cpw8_f(reg,val) do { \
360 writeb((val), cp->regs + (reg)); \
361 readb(cp->regs + (reg)); \
363 #define cpw16_f(reg,val) do { \
364 writew((val), cp->regs + (reg)); \
365 readw(cp->regs + (reg)); \
367 #define cpw32_f(reg,val) do { \
368 writel((val), cp->regs + (reg)); \
369 readl(cp->regs + (reg)); \
373 static void __cp_set_rx_mode (struct net_device
*dev
);
374 static void cp_tx (struct cp_private
*cp
);
375 static void cp_clean_rings (struct cp_private
*cp
);
376 #ifdef CONFIG_NET_POLL_CONTROLLER
377 static void cp_poll_controller(struct net_device
*dev
);
379 static int cp_get_eeprom_len(struct net_device
*dev
);
380 static int cp_get_eeprom(struct net_device
*dev
,
381 struct ethtool_eeprom
*eeprom
, u8
*data
);
382 static int cp_set_eeprom(struct net_device
*dev
,
383 struct ethtool_eeprom
*eeprom
, u8
*data
);
385 static DEFINE_PCI_DEVICE_TABLE(cp_pci_tbl
) = {
386 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, PCI_DEVICE_ID_REALTEK_8139
), },
387 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH
, PCI_DEVICE_ID_TTTECH_MC322
), },
390 MODULE_DEVICE_TABLE(pci
, cp_pci_tbl
);
393 const char str
[ETH_GSTRING_LEN
];
394 } ethtool_stats_keys
[] = {
412 static inline void cp_set_rxbufsize (struct cp_private
*cp
)
414 unsigned int mtu
= cp
->dev
->mtu
;
416 if (mtu
> ETH_DATA_LEN
)
417 /* MTU + ethernet header + FCS + optional VLAN tag */
418 cp
->rx_buf_sz
= mtu
+ ETH_HLEN
+ 8;
420 cp
->rx_buf_sz
= PKT_BUF_SZ
;
423 static inline void cp_rx_skb (struct cp_private
*cp
, struct sk_buff
*skb
,
424 struct cp_desc
*desc
)
426 u32 opts2
= le32_to_cpu(desc
->opts2
);
428 skb
->protocol
= eth_type_trans (skb
, cp
->dev
);
430 cp
->dev
->stats
.rx_packets
++;
431 cp
->dev
->stats
.rx_bytes
+= skb
->len
;
433 if (opts2
& RxVlanTagged
)
434 __vlan_hwaccel_put_tag(skb
, swab16(opts2
& 0xffff));
436 napi_gro_receive(&cp
->napi
, skb
);
439 static void cp_rx_err_acct (struct cp_private
*cp
, unsigned rx_tail
,
442 netif_dbg(cp
, rx_err
, cp
->dev
, "rx err, slot %d status 0x%x len %d\n",
443 rx_tail
, status
, len
);
444 cp
->dev
->stats
.rx_errors
++;
445 if (status
& RxErrFrame
)
446 cp
->dev
->stats
.rx_frame_errors
++;
447 if (status
& RxErrCRC
)
448 cp
->dev
->stats
.rx_crc_errors
++;
449 if ((status
& RxErrRunt
) || (status
& RxErrLong
))
450 cp
->dev
->stats
.rx_length_errors
++;
451 if ((status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
))
452 cp
->dev
->stats
.rx_length_errors
++;
453 if (status
& RxErrFIFO
)
454 cp
->dev
->stats
.rx_fifo_errors
++;
457 static inline unsigned int cp_rx_csum_ok (u32 status
)
459 unsigned int protocol
= (status
>> 16) & 0x3;
461 if (((protocol
== RxProtoTCP
) && !(status
& TCPFail
)) ||
462 ((protocol
== RxProtoUDP
) && !(status
& UDPFail
)))
468 static int cp_rx_poll(struct napi_struct
*napi
, int budget
)
470 struct cp_private
*cp
= container_of(napi
, struct cp_private
, napi
);
471 struct net_device
*dev
= cp
->dev
;
472 unsigned int rx_tail
= cp
->rx_tail
;
477 cpw16(IntrStatus
, cp_rx_intr_mask
);
482 struct sk_buff
*skb
, *new_skb
;
483 struct cp_desc
*desc
;
484 const unsigned buflen
= cp
->rx_buf_sz
;
486 skb
= cp
->rx_skb
[rx_tail
];
489 desc
= &cp
->rx_ring
[rx_tail
];
490 status
= le32_to_cpu(desc
->opts1
);
491 if (status
& DescOwn
)
494 len
= (status
& 0x1fff) - 4;
495 mapping
= le64_to_cpu(desc
->addr
);
497 if ((status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
)) {
498 /* we don't support incoming fragmented frames.
499 * instead, we attempt to ensure that the
500 * pre-allocated RX skbs are properly sized such
501 * that RX fragments are never encountered
503 cp_rx_err_acct(cp
, rx_tail
, status
, len
);
504 dev
->stats
.rx_dropped
++;
505 cp
->cp_stats
.rx_frags
++;
509 if (status
& (RxError
| RxErrFIFO
)) {
510 cp_rx_err_acct(cp
, rx_tail
, status
, len
);
514 netif_dbg(cp
, rx_status
, dev
, "rx slot %d status 0x%x len %d\n",
515 rx_tail
, status
, len
);
517 new_skb
= netdev_alloc_skb_ip_align(dev
, buflen
);
519 dev
->stats
.rx_dropped
++;
523 dma_unmap_single(&cp
->pdev
->dev
, mapping
,
524 buflen
, PCI_DMA_FROMDEVICE
);
526 /* Handle checksum offloading for incoming packets. */
527 if (cp_rx_csum_ok(status
))
528 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
530 skb_checksum_none_assert(skb
);
534 mapping
= dma_map_single(&cp
->pdev
->dev
, new_skb
->data
, buflen
,
536 cp
->rx_skb
[rx_tail
] = new_skb
;
538 cp_rx_skb(cp
, skb
, desc
);
542 cp
->rx_ring
[rx_tail
].opts2
= 0;
543 cp
->rx_ring
[rx_tail
].addr
= cpu_to_le64(mapping
);
544 if (rx_tail
== (CP_RX_RING_SIZE
- 1))
545 desc
->opts1
= cpu_to_le32(DescOwn
| RingEnd
|
548 desc
->opts1
= cpu_to_le32(DescOwn
| cp
->rx_buf_sz
);
549 rx_tail
= NEXT_RX(rx_tail
);
555 cp
->rx_tail
= rx_tail
;
557 /* if we did not reach work limit, then we're done with
558 * this round of polling
563 if (cpr16(IntrStatus
) & cp_rx_intr_mask
)
566 spin_lock_irqsave(&cp
->lock
, flags
);
567 __napi_complete(napi
);
568 cpw16_f(IntrMask
, cp_intr_mask
);
569 spin_unlock_irqrestore(&cp
->lock
, flags
);
575 static irqreturn_t
cp_interrupt (int irq
, void *dev_instance
)
577 struct net_device
*dev
= dev_instance
;
578 struct cp_private
*cp
;
581 if (unlikely(dev
== NULL
))
583 cp
= netdev_priv(dev
);
585 status
= cpr16(IntrStatus
);
586 if (!status
|| (status
== 0xFFFF))
589 netif_dbg(cp
, intr
, dev
, "intr, status %04x cmd %02x cpcmd %04x\n",
590 status
, cpr8(Cmd
), cpr16(CpCmd
));
592 cpw16(IntrStatus
, status
& ~cp_rx_intr_mask
);
594 spin_lock(&cp
->lock
);
596 /* close possible race's with dev_close */
597 if (unlikely(!netif_running(dev
))) {
599 spin_unlock(&cp
->lock
);
603 if (status
& (RxOK
| RxErr
| RxEmpty
| RxFIFOOvr
))
604 if (napi_schedule_prep(&cp
->napi
)) {
605 cpw16_f(IntrMask
, cp_norx_intr_mask
);
606 __napi_schedule(&cp
->napi
);
609 if (status
& (TxOK
| TxErr
| TxEmpty
| SWInt
))
611 if (status
& LinkChg
)
612 mii_check_media(&cp
->mii_if
, netif_msg_link(cp
), false);
614 spin_unlock(&cp
->lock
);
616 if (status
& PciErr
) {
619 pci_read_config_word(cp
->pdev
, PCI_STATUS
, &pci_status
);
620 pci_write_config_word(cp
->pdev
, PCI_STATUS
, pci_status
);
621 netdev_err(dev
, "PCI bus error, status=%04x, PCI status=%04x\n",
624 /* TODO: reset hardware */
630 #ifdef CONFIG_NET_POLL_CONTROLLER
632 * Polling receive - used by netconsole and other diagnostic tools
633 * to allow network i/o with interrupts disabled.
635 static void cp_poll_controller(struct net_device
*dev
)
637 disable_irq(dev
->irq
);
638 cp_interrupt(dev
->irq
, dev
);
639 enable_irq(dev
->irq
);
643 static void cp_tx (struct cp_private
*cp
)
645 unsigned tx_head
= cp
->tx_head
;
646 unsigned tx_tail
= cp
->tx_tail
;
648 while (tx_tail
!= tx_head
) {
649 struct cp_desc
*txd
= cp
->tx_ring
+ tx_tail
;
654 status
= le32_to_cpu(txd
->opts1
);
655 if (status
& DescOwn
)
658 skb
= cp
->tx_skb
[tx_tail
];
661 dma_unmap_single(&cp
->pdev
->dev
, le64_to_cpu(txd
->addr
),
662 le32_to_cpu(txd
->opts1
) & 0xffff,
665 if (status
& LastFrag
) {
666 if (status
& (TxError
| TxFIFOUnder
)) {
667 netif_dbg(cp
, tx_err
, cp
->dev
,
668 "tx err, status 0x%x\n", status
);
669 cp
->dev
->stats
.tx_errors
++;
671 cp
->dev
->stats
.tx_window_errors
++;
672 if (status
& TxMaxCol
)
673 cp
->dev
->stats
.tx_aborted_errors
++;
674 if (status
& TxLinkFail
)
675 cp
->dev
->stats
.tx_carrier_errors
++;
676 if (status
& TxFIFOUnder
)
677 cp
->dev
->stats
.tx_fifo_errors
++;
679 cp
->dev
->stats
.collisions
+=
680 ((status
>> TxColCntShift
) & TxColCntMask
);
681 cp
->dev
->stats
.tx_packets
++;
682 cp
->dev
->stats
.tx_bytes
+= skb
->len
;
683 netif_dbg(cp
, tx_done
, cp
->dev
,
684 "tx done, slot %d\n", tx_tail
);
686 dev_kfree_skb_irq(skb
);
689 cp
->tx_skb
[tx_tail
] = NULL
;
691 tx_tail
= NEXT_TX(tx_tail
);
694 cp
->tx_tail
= tx_tail
;
696 if (TX_BUFFS_AVAIL(cp
) > (MAX_SKB_FRAGS
+ 1))
697 netif_wake_queue(cp
->dev
);
700 static inline u32
cp_tx_vlan_tag(struct sk_buff
*skb
)
702 return vlan_tx_tag_present(skb
) ?
703 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
706 static netdev_tx_t
cp_start_xmit (struct sk_buff
*skb
,
707 struct net_device
*dev
)
709 struct cp_private
*cp
= netdev_priv(dev
);
712 unsigned long intr_flags
;
716 spin_lock_irqsave(&cp
->lock
, intr_flags
);
718 /* This is a hard error, log it. */
719 if (TX_BUFFS_AVAIL(cp
) <= (skb_shinfo(skb
)->nr_frags
+ 1)) {
720 netif_stop_queue(dev
);
721 spin_unlock_irqrestore(&cp
->lock
, intr_flags
);
722 netdev_err(dev
, "BUG! Tx Ring full when queue awake!\n");
723 return NETDEV_TX_BUSY
;
727 eor
= (entry
== (CP_TX_RING_SIZE
- 1)) ? RingEnd
: 0;
728 mss
= skb_shinfo(skb
)->gso_size
;
730 opts2
= cpu_to_le32(cp_tx_vlan_tag(skb
));
732 if (skb_shinfo(skb
)->nr_frags
== 0) {
733 struct cp_desc
*txd
= &cp
->tx_ring
[entry
];
738 mapping
= dma_map_single(&cp
->pdev
->dev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
740 txd
->addr
= cpu_to_le64(mapping
);
743 flags
= eor
| len
| DescOwn
| FirstFrag
| LastFrag
;
746 flags
|= LargeSend
| ((mss
& MSSMask
) << MSSShift
);
747 else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
748 const struct iphdr
*ip
= ip_hdr(skb
);
749 if (ip
->protocol
== IPPROTO_TCP
)
750 flags
|= IPCS
| TCPCS
;
751 else if (ip
->protocol
== IPPROTO_UDP
)
752 flags
|= IPCS
| UDPCS
;
754 WARN_ON(1); /* we need a WARN() */
757 txd
->opts1
= cpu_to_le32(flags
);
760 cp
->tx_skb
[entry
] = skb
;
761 entry
= NEXT_TX(entry
);
764 u32 first_len
, first_eor
;
765 dma_addr_t first_mapping
;
766 int frag
, first_entry
= entry
;
767 const struct iphdr
*ip
= ip_hdr(skb
);
769 /* We must give this initial chunk to the device last.
770 * Otherwise we could race with the device.
773 first_len
= skb_headlen(skb
);
774 first_mapping
= dma_map_single(&cp
->pdev
->dev
, skb
->data
,
775 first_len
, PCI_DMA_TODEVICE
);
776 cp
->tx_skb
[entry
] = skb
;
777 entry
= NEXT_TX(entry
);
779 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
780 skb_frag_t
*this_frag
= &skb_shinfo(skb
)->frags
[frag
];
785 len
= this_frag
->size
;
786 mapping
= dma_map_single(&cp
->pdev
->dev
,
787 skb_frag_address(this_frag
),
788 len
, PCI_DMA_TODEVICE
);
789 eor
= (entry
== (CP_TX_RING_SIZE
- 1)) ? RingEnd
: 0;
791 ctrl
= eor
| len
| DescOwn
;
795 ((mss
& MSSMask
) << MSSShift
);
796 else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
797 if (ip
->protocol
== IPPROTO_TCP
)
798 ctrl
|= IPCS
| TCPCS
;
799 else if (ip
->protocol
== IPPROTO_UDP
)
800 ctrl
|= IPCS
| UDPCS
;
805 if (frag
== skb_shinfo(skb
)->nr_frags
- 1)
808 txd
= &cp
->tx_ring
[entry
];
810 txd
->addr
= cpu_to_le64(mapping
);
813 txd
->opts1
= cpu_to_le32(ctrl
);
816 cp
->tx_skb
[entry
] = skb
;
817 entry
= NEXT_TX(entry
);
820 txd
= &cp
->tx_ring
[first_entry
];
822 txd
->addr
= cpu_to_le64(first_mapping
);
825 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
826 if (ip
->protocol
== IPPROTO_TCP
)
827 txd
->opts1
= cpu_to_le32(first_eor
| first_len
|
828 FirstFrag
| DescOwn
|
830 else if (ip
->protocol
== IPPROTO_UDP
)
831 txd
->opts1
= cpu_to_le32(first_eor
| first_len
|
832 FirstFrag
| DescOwn
|
837 txd
->opts1
= cpu_to_le32(first_eor
| first_len
|
838 FirstFrag
| DescOwn
);
842 netif_dbg(cp
, tx_queued
, cp
->dev
, "tx queued, slot %d, skblen %d\n",
844 if (TX_BUFFS_AVAIL(cp
) <= (MAX_SKB_FRAGS
+ 1))
845 netif_stop_queue(dev
);
847 spin_unlock_irqrestore(&cp
->lock
, intr_flags
);
849 cpw8(TxPoll
, NormalTxPoll
);
854 /* Set or clear the multicast filter for this adaptor.
855 This routine is not state sensitive and need not be SMP locked. */
857 static void __cp_set_rx_mode (struct net_device
*dev
)
859 struct cp_private
*cp
= netdev_priv(dev
);
860 u32 mc_filter
[2]; /* Multicast hash filter */
864 /* Note: do not reorder, GCC is clever about common statements. */
865 if (dev
->flags
& IFF_PROMISC
) {
866 /* Unconditionally log net taps. */
868 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
870 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
871 } else if ((netdev_mc_count(dev
) > multicast_filter_limit
) ||
872 (dev
->flags
& IFF_ALLMULTI
)) {
873 /* Too many to filter perfectly -- accept all multicasts. */
874 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
875 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
877 struct netdev_hw_addr
*ha
;
878 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
879 mc_filter
[1] = mc_filter
[0] = 0;
880 netdev_for_each_mc_addr(ha
, dev
) {
881 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
883 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
884 rx_mode
|= AcceptMulticast
;
888 /* We can safely update without stopping the chip. */
889 tmp
= cp_rx_config
| rx_mode
;
890 if (cp
->rx_config
!= tmp
) {
891 cpw32_f (RxConfig
, tmp
);
894 cpw32_f (MAR0
+ 0, mc_filter
[0]);
895 cpw32_f (MAR0
+ 4, mc_filter
[1]);
898 static void cp_set_rx_mode (struct net_device
*dev
)
901 struct cp_private
*cp
= netdev_priv(dev
);
903 spin_lock_irqsave (&cp
->lock
, flags
);
904 __cp_set_rx_mode(dev
);
905 spin_unlock_irqrestore (&cp
->lock
, flags
);
908 static void __cp_get_stats(struct cp_private
*cp
)
910 /* only lower 24 bits valid; write any value to clear */
911 cp
->dev
->stats
.rx_missed_errors
+= (cpr32 (RxMissed
) & 0xffffff);
915 static struct net_device_stats
*cp_get_stats(struct net_device
*dev
)
917 struct cp_private
*cp
= netdev_priv(dev
);
920 /* The chip only need report frame silently dropped. */
921 spin_lock_irqsave(&cp
->lock
, flags
);
922 if (netif_running(dev
) && netif_device_present(dev
))
924 spin_unlock_irqrestore(&cp
->lock
, flags
);
929 static void cp_stop_hw (struct cp_private
*cp
)
931 cpw16(IntrStatus
, ~(cpr16(IntrStatus
)));
932 cpw16_f(IntrMask
, 0);
935 cpw16_f(IntrStatus
, ~(cpr16(IntrStatus
)));
938 cp
->tx_head
= cp
->tx_tail
= 0;
941 static void cp_reset_hw (struct cp_private
*cp
)
943 unsigned work
= 1000;
948 if (!(cpr8(Cmd
) & CmdReset
))
951 schedule_timeout_uninterruptible(10);
954 netdev_err(cp
->dev
, "hardware reset timeout\n");
957 static inline void cp_start_hw (struct cp_private
*cp
)
959 cpw16(CpCmd
, cp
->cpcmd
);
960 cpw8(Cmd
, RxOn
| TxOn
);
963 static void cp_init_hw (struct cp_private
*cp
)
965 struct net_device
*dev
= cp
->dev
;
970 cpw8_f (Cfg9346
, Cfg9346_Unlock
);
972 /* Restore our idea of the MAC address. */
973 cpw32_f (MAC0
+ 0, le32_to_cpu (*(__le32
*) (dev
->dev_addr
+ 0)));
974 cpw32_f (MAC0
+ 4, le32_to_cpu (*(__le32
*) (dev
->dev_addr
+ 4)));
977 cpw8(TxThresh
, 0x06); /* XXX convert magic num to a constant */
979 __cp_set_rx_mode(dev
);
980 cpw32_f (TxConfig
, IFG
| (TX_DMA_BURST
<< TxDMAShift
));
982 cpw8(Config1
, cpr8(Config1
) | DriverLoaded
| PMEnable
);
983 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
984 cpw8(Config3
, PARMEnable
);
987 cpw8(Config5
, cpr8(Config5
) & PMEStatus
);
989 cpw32_f(HiTxRingAddr
, 0);
990 cpw32_f(HiTxRingAddr
+ 4, 0);
992 ring_dma
= cp
->ring_dma
;
993 cpw32_f(RxRingAddr
, ring_dma
& 0xffffffff);
994 cpw32_f(RxRingAddr
+ 4, (ring_dma
>> 16) >> 16);
996 ring_dma
+= sizeof(struct cp_desc
) * CP_RX_RING_SIZE
;
997 cpw32_f(TxRingAddr
, ring_dma
& 0xffffffff);
998 cpw32_f(TxRingAddr
+ 4, (ring_dma
>> 16) >> 16);
1000 cpw16(MultiIntr
, 0);
1002 cpw16_f(IntrMask
, cp_intr_mask
);
1004 cpw8_f(Cfg9346
, Cfg9346_Lock
);
1007 static int cp_refill_rx(struct cp_private
*cp
)
1009 struct net_device
*dev
= cp
->dev
;
1012 for (i
= 0; i
< CP_RX_RING_SIZE
; i
++) {
1013 struct sk_buff
*skb
;
1016 skb
= netdev_alloc_skb_ip_align(dev
, cp
->rx_buf_sz
);
1020 mapping
= dma_map_single(&cp
->pdev
->dev
, skb
->data
,
1021 cp
->rx_buf_sz
, PCI_DMA_FROMDEVICE
);
1022 cp
->rx_skb
[i
] = skb
;
1024 cp
->rx_ring
[i
].opts2
= 0;
1025 cp
->rx_ring
[i
].addr
= cpu_to_le64(mapping
);
1026 if (i
== (CP_RX_RING_SIZE
- 1))
1027 cp
->rx_ring
[i
].opts1
=
1028 cpu_to_le32(DescOwn
| RingEnd
| cp
->rx_buf_sz
);
1030 cp
->rx_ring
[i
].opts1
=
1031 cpu_to_le32(DescOwn
| cp
->rx_buf_sz
);
1041 static void cp_init_rings_index (struct cp_private
*cp
)
1044 cp
->tx_head
= cp
->tx_tail
= 0;
1047 static int cp_init_rings (struct cp_private
*cp
)
1049 memset(cp
->tx_ring
, 0, sizeof(struct cp_desc
) * CP_TX_RING_SIZE
);
1050 cp
->tx_ring
[CP_TX_RING_SIZE
- 1].opts1
= cpu_to_le32(RingEnd
);
1052 cp_init_rings_index(cp
);
1054 return cp_refill_rx (cp
);
1057 static int cp_alloc_rings (struct cp_private
*cp
)
1061 mem
= dma_alloc_coherent(&cp
->pdev
->dev
, CP_RING_BYTES
,
1062 &cp
->ring_dma
, GFP_KERNEL
);
1067 cp
->tx_ring
= &cp
->rx_ring
[CP_RX_RING_SIZE
];
1069 return cp_init_rings(cp
);
1072 static void cp_clean_rings (struct cp_private
*cp
)
1074 struct cp_desc
*desc
;
1077 for (i
= 0; i
< CP_RX_RING_SIZE
; i
++) {
1078 if (cp
->rx_skb
[i
]) {
1079 desc
= cp
->rx_ring
+ i
;
1080 dma_unmap_single(&cp
->pdev
->dev
,le64_to_cpu(desc
->addr
),
1081 cp
->rx_buf_sz
, PCI_DMA_FROMDEVICE
);
1082 dev_kfree_skb(cp
->rx_skb
[i
]);
1086 for (i
= 0; i
< CP_TX_RING_SIZE
; i
++) {
1087 if (cp
->tx_skb
[i
]) {
1088 struct sk_buff
*skb
= cp
->tx_skb
[i
];
1090 desc
= cp
->tx_ring
+ i
;
1091 dma_unmap_single(&cp
->pdev
->dev
,le64_to_cpu(desc
->addr
),
1092 le32_to_cpu(desc
->opts1
) & 0xffff,
1094 if (le32_to_cpu(desc
->opts1
) & LastFrag
)
1096 cp
->dev
->stats
.tx_dropped
++;
1100 memset(cp
->rx_ring
, 0, sizeof(struct cp_desc
) * CP_RX_RING_SIZE
);
1101 memset(cp
->tx_ring
, 0, sizeof(struct cp_desc
) * CP_TX_RING_SIZE
);
1103 memset(cp
->rx_skb
, 0, sizeof(struct sk_buff
*) * CP_RX_RING_SIZE
);
1104 memset(cp
->tx_skb
, 0, sizeof(struct sk_buff
*) * CP_TX_RING_SIZE
);
1107 static void cp_free_rings (struct cp_private
*cp
)
1110 dma_free_coherent(&cp
->pdev
->dev
, CP_RING_BYTES
, cp
->rx_ring
,
1116 static int cp_open (struct net_device
*dev
)
1118 struct cp_private
*cp
= netdev_priv(dev
);
1121 netif_dbg(cp
, ifup
, dev
, "enabling interface\n");
1123 rc
= cp_alloc_rings(cp
);
1127 napi_enable(&cp
->napi
);
1131 rc
= request_irq(dev
->irq
, cp_interrupt
, IRQF_SHARED
, dev
->name
, dev
);
1135 netif_carrier_off(dev
);
1136 mii_check_media(&cp
->mii_if
, netif_msg_link(cp
), true);
1137 netif_start_queue(dev
);
1142 napi_disable(&cp
->napi
);
1148 static int cp_close (struct net_device
*dev
)
1150 struct cp_private
*cp
= netdev_priv(dev
);
1151 unsigned long flags
;
1153 napi_disable(&cp
->napi
);
1155 netif_dbg(cp
, ifdown
, dev
, "disabling interface\n");
1157 spin_lock_irqsave(&cp
->lock
, flags
);
1159 netif_stop_queue(dev
);
1160 netif_carrier_off(dev
);
1164 spin_unlock_irqrestore(&cp
->lock
, flags
);
1166 free_irq(dev
->irq
, dev
);
1172 static void cp_tx_timeout(struct net_device
*dev
)
1174 struct cp_private
*cp
= netdev_priv(dev
);
1175 unsigned long flags
;
1178 netdev_warn(dev
, "Transmit timeout, status %2x %4x %4x %4x\n",
1179 cpr8(Cmd
), cpr16(CpCmd
),
1180 cpr16(IntrStatus
), cpr16(IntrMask
));
1182 spin_lock_irqsave(&cp
->lock
, flags
);
1186 rc
= cp_init_rings(cp
);
1189 netif_wake_queue(dev
);
1191 spin_unlock_irqrestore(&cp
->lock
, flags
);
1195 static int cp_change_mtu(struct net_device
*dev
, int new_mtu
)
1197 struct cp_private
*cp
= netdev_priv(dev
);
1199 unsigned long flags
;
1201 /* check for invalid MTU, according to hardware limits */
1202 if (new_mtu
< CP_MIN_MTU
|| new_mtu
> CP_MAX_MTU
)
1205 /* if network interface not up, no need for complexity */
1206 if (!netif_running(dev
)) {
1208 cp_set_rxbufsize(cp
); /* set new rx buf size */
1212 spin_lock_irqsave(&cp
->lock
, flags
);
1214 cp_stop_hw(cp
); /* stop h/w and free rings */
1218 cp_set_rxbufsize(cp
); /* set new rx buf size */
1220 rc
= cp_init_rings(cp
); /* realloc and restart h/w */
1223 spin_unlock_irqrestore(&cp
->lock
, flags
);
1229 static const char mii_2_8139_map
[8] = {
1240 static int mdio_read(struct net_device
*dev
, int phy_id
, int location
)
1242 struct cp_private
*cp
= netdev_priv(dev
);
1244 return location
< 8 && mii_2_8139_map
[location
] ?
1245 readw(cp
->regs
+ mii_2_8139_map
[location
]) : 0;
1249 static void mdio_write(struct net_device
*dev
, int phy_id
, int location
,
1252 struct cp_private
*cp
= netdev_priv(dev
);
1254 if (location
== 0) {
1255 cpw8(Cfg9346
, Cfg9346_Unlock
);
1256 cpw16(BasicModeCtrl
, value
);
1257 cpw8(Cfg9346
, Cfg9346_Lock
);
1258 } else if (location
< 8 && mii_2_8139_map
[location
])
1259 cpw16(mii_2_8139_map
[location
], value
);
1262 /* Set the ethtool Wake-on-LAN settings */
1263 static int netdev_set_wol (struct cp_private
*cp
,
1264 const struct ethtool_wolinfo
*wol
)
1268 options
= cpr8 (Config3
) & ~(LinkUp
| MagicPacket
);
1269 /* If WOL is being disabled, no need for complexity */
1271 if (wol
->wolopts
& WAKE_PHY
) options
|= LinkUp
;
1272 if (wol
->wolopts
& WAKE_MAGIC
) options
|= MagicPacket
;
1275 cpw8 (Cfg9346
, Cfg9346_Unlock
);
1276 cpw8 (Config3
, options
);
1277 cpw8 (Cfg9346
, Cfg9346_Lock
);
1279 options
= 0; /* Paranoia setting */
1280 options
= cpr8 (Config5
) & ~(UWF
| MWF
| BWF
);
1281 /* If WOL is being disabled, no need for complexity */
1283 if (wol
->wolopts
& WAKE_UCAST
) options
|= UWF
;
1284 if (wol
->wolopts
& WAKE_BCAST
) options
|= BWF
;
1285 if (wol
->wolopts
& WAKE_MCAST
) options
|= MWF
;
1288 cpw8 (Config5
, options
);
1290 cp
->wol_enabled
= (wol
->wolopts
) ? 1 : 0;
1295 /* Get the ethtool Wake-on-LAN settings */
1296 static void netdev_get_wol (struct cp_private
*cp
,
1297 struct ethtool_wolinfo
*wol
)
1301 wol
->wolopts
= 0; /* Start from scratch */
1302 wol
->supported
= WAKE_PHY
| WAKE_BCAST
| WAKE_MAGIC
|
1303 WAKE_MCAST
| WAKE_UCAST
;
1304 /* We don't need to go on if WOL is disabled */
1305 if (!cp
->wol_enabled
) return;
1307 options
= cpr8 (Config3
);
1308 if (options
& LinkUp
) wol
->wolopts
|= WAKE_PHY
;
1309 if (options
& MagicPacket
) wol
->wolopts
|= WAKE_MAGIC
;
1311 options
= 0; /* Paranoia setting */
1312 options
= cpr8 (Config5
);
1313 if (options
& UWF
) wol
->wolopts
|= WAKE_UCAST
;
1314 if (options
& BWF
) wol
->wolopts
|= WAKE_BCAST
;
1315 if (options
& MWF
) wol
->wolopts
|= WAKE_MCAST
;
1318 static void cp_get_drvinfo (struct net_device
*dev
, struct ethtool_drvinfo
*info
)
1320 struct cp_private
*cp
= netdev_priv(dev
);
1322 strcpy (info
->driver
, DRV_NAME
);
1323 strcpy (info
->version
, DRV_VERSION
);
1324 strcpy (info
->bus_info
, pci_name(cp
->pdev
));
1327 static int cp_get_regs_len(struct net_device
*dev
)
1329 return CP_REGS_SIZE
;
1332 static int cp_get_sset_count (struct net_device
*dev
, int sset
)
1336 return CP_NUM_STATS
;
1342 static int cp_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1344 struct cp_private
*cp
= netdev_priv(dev
);
1346 unsigned long flags
;
1348 spin_lock_irqsave(&cp
->lock
, flags
);
1349 rc
= mii_ethtool_gset(&cp
->mii_if
, cmd
);
1350 spin_unlock_irqrestore(&cp
->lock
, flags
);
1355 static int cp_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1357 struct cp_private
*cp
= netdev_priv(dev
);
1359 unsigned long flags
;
1361 spin_lock_irqsave(&cp
->lock
, flags
);
1362 rc
= mii_ethtool_sset(&cp
->mii_if
, cmd
);
1363 spin_unlock_irqrestore(&cp
->lock
, flags
);
1368 static int cp_nway_reset(struct net_device
*dev
)
1370 struct cp_private
*cp
= netdev_priv(dev
);
1371 return mii_nway_restart(&cp
->mii_if
);
1374 static u32
cp_get_msglevel(struct net_device
*dev
)
1376 struct cp_private
*cp
= netdev_priv(dev
);
1377 return cp
->msg_enable
;
1380 static void cp_set_msglevel(struct net_device
*dev
, u32 value
)
1382 struct cp_private
*cp
= netdev_priv(dev
);
1383 cp
->msg_enable
= value
;
1386 static int cp_set_features(struct net_device
*dev
, u32 features
)
1388 struct cp_private
*cp
= netdev_priv(dev
);
1389 unsigned long flags
;
1391 if (!((dev
->features
^ features
) & NETIF_F_RXCSUM
))
1394 spin_lock_irqsave(&cp
->lock
, flags
);
1396 if (features
& NETIF_F_RXCSUM
)
1397 cp
->cpcmd
|= RxChkSum
;
1399 cp
->cpcmd
&= ~RxChkSum
;
1401 if (features
& NETIF_F_HW_VLAN_RX
)
1402 cp
->cpcmd
|= RxVlanOn
;
1404 cp
->cpcmd
&= ~RxVlanOn
;
1406 cpw16_f(CpCmd
, cp
->cpcmd
);
1407 spin_unlock_irqrestore(&cp
->lock
, flags
);
1412 static void cp_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1415 struct cp_private
*cp
= netdev_priv(dev
);
1416 unsigned long flags
;
1418 if (regs
->len
< CP_REGS_SIZE
)
1419 return /* -EINVAL */;
1421 regs
->version
= CP_REGS_VER
;
1423 spin_lock_irqsave(&cp
->lock
, flags
);
1424 memcpy_fromio(p
, cp
->regs
, CP_REGS_SIZE
);
1425 spin_unlock_irqrestore(&cp
->lock
, flags
);
1428 static void cp_get_wol (struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1430 struct cp_private
*cp
= netdev_priv(dev
);
1431 unsigned long flags
;
1433 spin_lock_irqsave (&cp
->lock
, flags
);
1434 netdev_get_wol (cp
, wol
);
1435 spin_unlock_irqrestore (&cp
->lock
, flags
);
1438 static int cp_set_wol (struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1440 struct cp_private
*cp
= netdev_priv(dev
);
1441 unsigned long flags
;
1444 spin_lock_irqsave (&cp
->lock
, flags
);
1445 rc
= netdev_set_wol (cp
, wol
);
1446 spin_unlock_irqrestore (&cp
->lock
, flags
);
1451 static void cp_get_strings (struct net_device
*dev
, u32 stringset
, u8
*buf
)
1453 switch (stringset
) {
1455 memcpy(buf
, ðtool_stats_keys
, sizeof(ethtool_stats_keys
));
1463 static void cp_get_ethtool_stats (struct net_device
*dev
,
1464 struct ethtool_stats
*estats
, u64
*tmp_stats
)
1466 struct cp_private
*cp
= netdev_priv(dev
);
1467 struct cp_dma_stats
*nic_stats
;
1471 nic_stats
= dma_alloc_coherent(&cp
->pdev
->dev
, sizeof(*nic_stats
),
1476 /* begin NIC statistics dump */
1477 cpw32(StatsAddr
+ 4, (u64
)dma
>> 32);
1478 cpw32(StatsAddr
, ((u64
)dma
& DMA_BIT_MASK(32)) | DumpStats
);
1481 for (i
= 0; i
< 1000; i
++) {
1482 if ((cpr32(StatsAddr
) & DumpStats
) == 0)
1486 cpw32(StatsAddr
, 0);
1487 cpw32(StatsAddr
+ 4, 0);
1491 tmp_stats
[i
++] = le64_to_cpu(nic_stats
->tx_ok
);
1492 tmp_stats
[i
++] = le64_to_cpu(nic_stats
->rx_ok
);
1493 tmp_stats
[i
++] = le64_to_cpu(nic_stats
->tx_err
);
1494 tmp_stats
[i
++] = le32_to_cpu(nic_stats
->rx_err
);
1495 tmp_stats
[i
++] = le16_to_cpu(nic_stats
->rx_fifo
);
1496 tmp_stats
[i
++] = le16_to_cpu(nic_stats
->frame_align
);
1497 tmp_stats
[i
++] = le32_to_cpu(nic_stats
->tx_ok_1col
);
1498 tmp_stats
[i
++] = le32_to_cpu(nic_stats
->tx_ok_mcol
);
1499 tmp_stats
[i
++] = le64_to_cpu(nic_stats
->rx_ok_phys
);
1500 tmp_stats
[i
++] = le64_to_cpu(nic_stats
->rx_ok_bcast
);
1501 tmp_stats
[i
++] = le32_to_cpu(nic_stats
->rx_ok_mcast
);
1502 tmp_stats
[i
++] = le16_to_cpu(nic_stats
->tx_abort
);
1503 tmp_stats
[i
++] = le16_to_cpu(nic_stats
->tx_underrun
);
1504 tmp_stats
[i
++] = cp
->cp_stats
.rx_frags
;
1505 BUG_ON(i
!= CP_NUM_STATS
);
1507 dma_free_coherent(&cp
->pdev
->dev
, sizeof(*nic_stats
), nic_stats
, dma
);
1510 static const struct ethtool_ops cp_ethtool_ops
= {
1511 .get_drvinfo
= cp_get_drvinfo
,
1512 .get_regs_len
= cp_get_regs_len
,
1513 .get_sset_count
= cp_get_sset_count
,
1514 .get_settings
= cp_get_settings
,
1515 .set_settings
= cp_set_settings
,
1516 .nway_reset
= cp_nway_reset
,
1517 .get_link
= ethtool_op_get_link
,
1518 .get_msglevel
= cp_get_msglevel
,
1519 .set_msglevel
= cp_set_msglevel
,
1520 .get_regs
= cp_get_regs
,
1521 .get_wol
= cp_get_wol
,
1522 .set_wol
= cp_set_wol
,
1523 .get_strings
= cp_get_strings
,
1524 .get_ethtool_stats
= cp_get_ethtool_stats
,
1525 .get_eeprom_len
= cp_get_eeprom_len
,
1526 .get_eeprom
= cp_get_eeprom
,
1527 .set_eeprom
= cp_set_eeprom
,
1530 static int cp_ioctl (struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
1532 struct cp_private
*cp
= netdev_priv(dev
);
1534 unsigned long flags
;
1536 if (!netif_running(dev
))
1539 spin_lock_irqsave(&cp
->lock
, flags
);
1540 rc
= generic_mii_ioctl(&cp
->mii_if
, if_mii(rq
), cmd
, NULL
);
1541 spin_unlock_irqrestore(&cp
->lock
, flags
);
1545 static int cp_set_mac_address(struct net_device
*dev
, void *p
)
1547 struct cp_private
*cp
= netdev_priv(dev
);
1548 struct sockaddr
*addr
= p
;
1550 if (!is_valid_ether_addr(addr
->sa_data
))
1551 return -EADDRNOTAVAIL
;
1553 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
1555 spin_lock_irq(&cp
->lock
);
1557 cpw8_f(Cfg9346
, Cfg9346_Unlock
);
1558 cpw32_f(MAC0
+ 0, le32_to_cpu (*(__le32
*) (dev
->dev_addr
+ 0)));
1559 cpw32_f(MAC0
+ 4, le32_to_cpu (*(__le32
*) (dev
->dev_addr
+ 4)));
1560 cpw8_f(Cfg9346
, Cfg9346_Lock
);
1562 spin_unlock_irq(&cp
->lock
);
1567 /* Serial EEPROM section. */
1569 /* EEPROM_Ctrl bits. */
1570 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1571 #define EE_CS 0x08 /* EEPROM chip select. */
1572 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1573 #define EE_WRITE_0 0x00
1574 #define EE_WRITE_1 0x02
1575 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1576 #define EE_ENB (0x80 | EE_CS)
1578 /* Delay between EEPROM clock transitions.
1579 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1582 #define eeprom_delay() readl(ee_addr)
1584 /* The EEPROM commands include the alway-set leading bit. */
1585 #define EE_EXTEND_CMD (4)
1586 #define EE_WRITE_CMD (5)
1587 #define EE_READ_CMD (6)
1588 #define EE_ERASE_CMD (7)
1590 #define EE_EWDS_ADDR (0)
1591 #define EE_WRAL_ADDR (1)
1592 #define EE_ERAL_ADDR (2)
1593 #define EE_EWEN_ADDR (3)
1595 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1597 static void eeprom_cmd_start(void __iomem
*ee_addr
)
1599 writeb (EE_ENB
& ~EE_CS
, ee_addr
);
1600 writeb (EE_ENB
, ee_addr
);
1604 static void eeprom_cmd(void __iomem
*ee_addr
, int cmd
, int cmd_len
)
1608 /* Shift the command bits out. */
1609 for (i
= cmd_len
- 1; i
>= 0; i
--) {
1610 int dataval
= (cmd
& (1 << i
)) ? EE_DATA_WRITE
: 0;
1611 writeb (EE_ENB
| dataval
, ee_addr
);
1613 writeb (EE_ENB
| dataval
| EE_SHIFT_CLK
, ee_addr
);
1616 writeb (EE_ENB
, ee_addr
);
1620 static void eeprom_cmd_end(void __iomem
*ee_addr
)
1622 writeb (~EE_CS
, ee_addr
);
1626 static void eeprom_extend_cmd(void __iomem
*ee_addr
, int extend_cmd
,
1629 int cmd
= (EE_EXTEND_CMD
<< addr_len
) | (extend_cmd
<< (addr_len
- 2));
1631 eeprom_cmd_start(ee_addr
);
1632 eeprom_cmd(ee_addr
, cmd
, 3 + addr_len
);
1633 eeprom_cmd_end(ee_addr
);
1636 static u16
read_eeprom (void __iomem
*ioaddr
, int location
, int addr_len
)
1640 void __iomem
*ee_addr
= ioaddr
+ Cfg9346
;
1641 int read_cmd
= location
| (EE_READ_CMD
<< addr_len
);
1643 eeprom_cmd_start(ee_addr
);
1644 eeprom_cmd(ee_addr
, read_cmd
, 3 + addr_len
);
1646 for (i
= 16; i
> 0; i
--) {
1647 writeb (EE_ENB
| EE_SHIFT_CLK
, ee_addr
);
1650 (retval
<< 1) | ((readb (ee_addr
) & EE_DATA_READ
) ? 1 :
1652 writeb (EE_ENB
, ee_addr
);
1656 eeprom_cmd_end(ee_addr
);
1661 static void write_eeprom(void __iomem
*ioaddr
, int location
, u16 val
,
1665 void __iomem
*ee_addr
= ioaddr
+ Cfg9346
;
1666 int write_cmd
= location
| (EE_WRITE_CMD
<< addr_len
);
1668 eeprom_extend_cmd(ee_addr
, EE_EWEN_ADDR
, addr_len
);
1670 eeprom_cmd_start(ee_addr
);
1671 eeprom_cmd(ee_addr
, write_cmd
, 3 + addr_len
);
1672 eeprom_cmd(ee_addr
, val
, 16);
1673 eeprom_cmd_end(ee_addr
);
1675 eeprom_cmd_start(ee_addr
);
1676 for (i
= 0; i
< 20000; i
++)
1677 if (readb(ee_addr
) & EE_DATA_READ
)
1679 eeprom_cmd_end(ee_addr
);
1681 eeprom_extend_cmd(ee_addr
, EE_EWDS_ADDR
, addr_len
);
1684 static int cp_get_eeprom_len(struct net_device
*dev
)
1686 struct cp_private
*cp
= netdev_priv(dev
);
1689 spin_lock_irq(&cp
->lock
);
1690 size
= read_eeprom(cp
->regs
, 0, 8) == 0x8129 ? 256 : 128;
1691 spin_unlock_irq(&cp
->lock
);
1696 static int cp_get_eeprom(struct net_device
*dev
,
1697 struct ethtool_eeprom
*eeprom
, u8
*data
)
1699 struct cp_private
*cp
= netdev_priv(dev
);
1700 unsigned int addr_len
;
1702 u32 offset
= eeprom
->offset
>> 1;
1703 u32 len
= eeprom
->len
;
1706 eeprom
->magic
= CP_EEPROM_MAGIC
;
1708 spin_lock_irq(&cp
->lock
);
1710 addr_len
= read_eeprom(cp
->regs
, 0, 8) == 0x8129 ? 8 : 6;
1712 if (eeprom
->offset
& 1) {
1713 val
= read_eeprom(cp
->regs
, offset
, addr_len
);
1714 data
[i
++] = (u8
)(val
>> 8);
1718 while (i
< len
- 1) {
1719 val
= read_eeprom(cp
->regs
, offset
, addr_len
);
1720 data
[i
++] = (u8
)val
;
1721 data
[i
++] = (u8
)(val
>> 8);
1726 val
= read_eeprom(cp
->regs
, offset
, addr_len
);
1730 spin_unlock_irq(&cp
->lock
);
1734 static int cp_set_eeprom(struct net_device
*dev
,
1735 struct ethtool_eeprom
*eeprom
, u8
*data
)
1737 struct cp_private
*cp
= netdev_priv(dev
);
1738 unsigned int addr_len
;
1740 u32 offset
= eeprom
->offset
>> 1;
1741 u32 len
= eeprom
->len
;
1744 if (eeprom
->magic
!= CP_EEPROM_MAGIC
)
1747 spin_lock_irq(&cp
->lock
);
1749 addr_len
= read_eeprom(cp
->regs
, 0, 8) == 0x8129 ? 8 : 6;
1751 if (eeprom
->offset
& 1) {
1752 val
= read_eeprom(cp
->regs
, offset
, addr_len
) & 0xff;
1753 val
|= (u16
)data
[i
++] << 8;
1754 write_eeprom(cp
->regs
, offset
, val
, addr_len
);
1758 while (i
< len
- 1) {
1759 val
= (u16
)data
[i
++];
1760 val
|= (u16
)data
[i
++] << 8;
1761 write_eeprom(cp
->regs
, offset
, val
, addr_len
);
1766 val
= read_eeprom(cp
->regs
, offset
, addr_len
) & 0xff00;
1767 val
|= (u16
)data
[i
];
1768 write_eeprom(cp
->regs
, offset
, val
, addr_len
);
1771 spin_unlock_irq(&cp
->lock
);
1775 /* Put the board into D3cold state and wait for WakeUp signal */
1776 static void cp_set_d3_state (struct cp_private
*cp
)
1778 pci_enable_wake (cp
->pdev
, 0, 1); /* Enable PME# generation */
1779 pci_set_power_state (cp
->pdev
, PCI_D3hot
);
1782 static const struct net_device_ops cp_netdev_ops
= {
1783 .ndo_open
= cp_open
,
1784 .ndo_stop
= cp_close
,
1785 .ndo_validate_addr
= eth_validate_addr
,
1786 .ndo_set_mac_address
= cp_set_mac_address
,
1787 .ndo_set_rx_mode
= cp_set_rx_mode
,
1788 .ndo_get_stats
= cp_get_stats
,
1789 .ndo_do_ioctl
= cp_ioctl
,
1790 .ndo_start_xmit
= cp_start_xmit
,
1791 .ndo_tx_timeout
= cp_tx_timeout
,
1792 .ndo_set_features
= cp_set_features
,
1794 .ndo_change_mtu
= cp_change_mtu
,
1797 #ifdef CONFIG_NET_POLL_CONTROLLER
1798 .ndo_poll_controller
= cp_poll_controller
,
1802 static int cp_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1804 struct net_device
*dev
;
1805 struct cp_private
*cp
;
1808 resource_size_t pciaddr
;
1809 unsigned int addr_len
, i
, pci_using_dac
;
1812 static int version_printed
;
1813 if (version_printed
++ == 0)
1814 pr_info("%s", version
);
1817 if (pdev
->vendor
== PCI_VENDOR_ID_REALTEK
&&
1818 pdev
->device
== PCI_DEVICE_ID_REALTEK_8139
&& pdev
->revision
< 0x20) {
1819 dev_info(&pdev
->dev
,
1820 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip, use 8139too\n",
1821 pdev
->vendor
, pdev
->device
, pdev
->revision
);
1825 dev
= alloc_etherdev(sizeof(struct cp_private
));
1828 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1830 cp
= netdev_priv(dev
);
1833 cp
->msg_enable
= (debug
< 0 ? CP_DEF_MSG_ENABLE
: debug
);
1834 spin_lock_init (&cp
->lock
);
1835 cp
->mii_if
.dev
= dev
;
1836 cp
->mii_if
.mdio_read
= mdio_read
;
1837 cp
->mii_if
.mdio_write
= mdio_write
;
1838 cp
->mii_if
.phy_id
= CP_INTERNAL_PHY
;
1839 cp
->mii_if
.phy_id_mask
= 0x1f;
1840 cp
->mii_if
.reg_num_mask
= 0x1f;
1841 cp_set_rxbufsize(cp
);
1843 rc
= pci_enable_device(pdev
);
1847 rc
= pci_set_mwi(pdev
);
1849 goto err_out_disable
;
1851 rc
= pci_request_regions(pdev
, DRV_NAME
);
1855 pciaddr
= pci_resource_start(pdev
, 1);
1858 dev_err(&pdev
->dev
, "no MMIO resource\n");
1861 if (pci_resource_len(pdev
, 1) < CP_REGS_SIZE
) {
1863 dev_err(&pdev
->dev
, "MMIO resource (%llx) too small\n",
1864 (unsigned long long)pci_resource_len(pdev
, 1));
1868 /* Configure DMA attributes. */
1869 if ((sizeof(dma_addr_t
) > 4) &&
1870 !pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64)) &&
1871 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64))) {
1876 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
1879 "No usable DMA configuration, aborting\n");
1882 rc
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
1885 "No usable consistent DMA configuration, aborting\n");
1890 cp
->cpcmd
= (pci_using_dac
? PCIDAC
: 0) |
1891 PCIMulRW
| RxChkSum
| CpRxOn
| CpTxOn
;
1893 dev
->features
|= NETIF_F_RXCSUM
;
1894 dev
->hw_features
|= NETIF_F_RXCSUM
;
1896 regs
= ioremap(pciaddr
, CP_REGS_SIZE
);
1899 dev_err(&pdev
->dev
, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1900 (unsigned long long)pci_resource_len(pdev
, 1),
1901 (unsigned long long)pciaddr
);
1904 dev
->base_addr
= (unsigned long) regs
;
1909 /* read MAC address from EEPROM */
1910 addr_len
= read_eeprom (regs
, 0, 8) == 0x8129 ? 8 : 6;
1911 for (i
= 0; i
< 3; i
++)
1912 ((__le16
*) (dev
->dev_addr
))[i
] =
1913 cpu_to_le16(read_eeprom (regs
, i
+ 7, addr_len
));
1914 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
1916 dev
->netdev_ops
= &cp_netdev_ops
;
1917 netif_napi_add(dev
, &cp
->napi
, cp_rx_poll
, 16);
1918 dev
->ethtool_ops
= &cp_ethtool_ops
;
1919 dev
->watchdog_timeo
= TX_TIMEOUT
;
1921 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
1924 dev
->features
|= NETIF_F_HIGHDMA
;
1926 /* disabled by default until verified */
1927 dev
->hw_features
|= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
1928 NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
1929 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
1932 dev
->irq
= pdev
->irq
;
1934 rc
= register_netdev(dev
);
1938 netdev_info(dev
, "RTL-8139C+ at 0x%lx, %pM, IRQ %d\n",
1939 dev
->base_addr
, dev
->dev_addr
, dev
->irq
);
1941 pci_set_drvdata(pdev
, dev
);
1943 /* enable busmastering and memory-write-invalidate */
1944 pci_set_master(pdev
);
1946 if (cp
->wol_enabled
)
1947 cp_set_d3_state (cp
);
1954 pci_release_regions(pdev
);
1956 pci_clear_mwi(pdev
);
1958 pci_disable_device(pdev
);
1964 static void cp_remove_one (struct pci_dev
*pdev
)
1966 struct net_device
*dev
= pci_get_drvdata(pdev
);
1967 struct cp_private
*cp
= netdev_priv(dev
);
1969 unregister_netdev(dev
);
1971 if (cp
->wol_enabled
)
1972 pci_set_power_state (pdev
, PCI_D0
);
1973 pci_release_regions(pdev
);
1974 pci_clear_mwi(pdev
);
1975 pci_disable_device(pdev
);
1976 pci_set_drvdata(pdev
, NULL
);
1981 static int cp_suspend (struct pci_dev
*pdev
, pm_message_t state
)
1983 struct net_device
*dev
= pci_get_drvdata(pdev
);
1984 struct cp_private
*cp
= netdev_priv(dev
);
1985 unsigned long flags
;
1987 if (!netif_running(dev
))
1990 netif_device_detach (dev
);
1991 netif_stop_queue (dev
);
1993 spin_lock_irqsave (&cp
->lock
, flags
);
1995 /* Disable Rx and Tx */
1996 cpw16 (IntrMask
, 0);
1997 cpw8 (Cmd
, cpr8 (Cmd
) & (~RxOn
| ~TxOn
));
1999 spin_unlock_irqrestore (&cp
->lock
, flags
);
2001 pci_save_state(pdev
);
2002 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), cp
->wol_enabled
);
2003 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
2008 static int cp_resume (struct pci_dev
*pdev
)
2010 struct net_device
*dev
= pci_get_drvdata (pdev
);
2011 struct cp_private
*cp
= netdev_priv(dev
);
2012 unsigned long flags
;
2014 if (!netif_running(dev
))
2017 netif_device_attach (dev
);
2019 pci_set_power_state(pdev
, PCI_D0
);
2020 pci_restore_state(pdev
);
2021 pci_enable_wake(pdev
, PCI_D0
, 0);
2023 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2024 cp_init_rings_index (cp
);
2026 netif_start_queue (dev
);
2028 spin_lock_irqsave (&cp
->lock
, flags
);
2030 mii_check_media(&cp
->mii_if
, netif_msg_link(cp
), false);
2032 spin_unlock_irqrestore (&cp
->lock
, flags
);
2036 #endif /* CONFIG_PM */
2038 static struct pci_driver cp_driver
= {
2040 .id_table
= cp_pci_tbl
,
2041 .probe
= cp_init_one
,
2042 .remove
= cp_remove_one
,
2044 .resume
= cp_resume
,
2045 .suspend
= cp_suspend
,
2049 static int __init
cp_init (void)
2052 pr_info("%s", version
);
2054 return pci_register_driver(&cp_driver
);
2057 static void __exit
cp_exit (void)
2059 pci_unregister_driver (&cp_driver
);
2062 module_init(cp_init
);
2063 module_exit(cp_exit
);