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Merge remote-tracking branch 'moduleh/module.h-split'
[linux-2.6/next.git] / drivers / usb / host / isp1760-hcd.c
blob5b08bd743accfe7edb6d2ad9dc6cb6ce55cb1a93
1 /*
2 * Driver for the NXP ISP1760 chip
3 *
4 * However, the code might contain some bugs. What doesn't work for sure is:
5 * - ISO
6 * - OTG
7 e The interrupt line is configured as active low, level.
8 *
9 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
10 *
11 * (c) 2011 Arvid Brodin <arvid.brodin@enea.com>
12 *
13 */
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/slab.h>
17 #include <linux/list.h>
18 #include <linux/usb.h>
19 #include <linux/usb/hcd.h>
20 #include <linux/debugfs.h>
21 #include <linux/uaccess.h>
22 #include <linux/io.h>
23 #include <linux/mm.h>
24 #include <linux/timer.h>
25 #include <asm/unaligned.h>
26 #include <asm/cacheflush.h>
27
28 #include "isp1760-hcd.h"
29
30 static struct kmem_cache *qtd_cachep;
31 static struct kmem_cache *qh_cachep;
32 static struct kmem_cache *urb_listitem_cachep;
33
34 struct isp1760_hcd {
35 u32 hcs_params;
36 spinlock_t lock;
37 struct slotinfo atl_slots[32];
38 int atl_done_map;
39 struct slotinfo int_slots[32];
40 int int_done_map;
41 struct memory_chunk memory_pool[BLOCKS];
42 struct list_head controlqhs, bulkqhs, interruptqhs;
43
44 /* periodic schedule support */
45 #define DEFAULT_I_TDPS 1024
46 unsigned periodic_size;
47 unsigned i_thresh;
48 unsigned long reset_done;
49 unsigned long next_statechange;
50 unsigned int devflags;
51 };
52
53 static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
54 {
55 return (struct isp1760_hcd *) (hcd->hcd_priv);
56 }
57
58 /* Section 2.2 Host Controller Capability Registers */
59 #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
60 #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
61 #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
62 #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
63 #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
64 #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
65 #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
66
67 /* Section 2.3 Host Controller Operational Registers */
68 #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
69 #define CMD_RESET (1<<1) /* reset HC not bus */
70 #define CMD_RUN (1<<0) /* start/stop HC */
71 #define STS_PCD (1<<2) /* port change detect */
72 #define FLAG_CF (1<<0) /* true: we'll support "high speed" */
73
74 #define PORT_OWNER (1<<13) /* true: companion hc owns this port */
75 #define PORT_POWER (1<<12) /* true: has power (see PPC) */
76 #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
77 #define PORT_RESET (1<<8) /* reset port */
78 #define PORT_SUSPEND (1<<7) /* suspend port */
79 #define PORT_RESUME (1<<6) /* resume it */
80 #define PORT_PE (1<<2) /* port enable */
81 #define PORT_CSC (1<<1) /* connect status change */
82 #define PORT_CONNECT (1<<0) /* device connected */
83 #define PORT_RWC_BITS (PORT_CSC)
84
85 struct isp1760_qtd {
86 u8 packet_type;
87 void *data_buffer;
88 u32 payload_addr;
89
90 /* the rest is HCD-private */
91 struct list_head qtd_list;
92 struct urb *urb;
93 size_t length;
94 size_t actual_length;
95
96 /* QTD_ENQUEUED: waiting for transfer (inactive) */
97 /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */
98 /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only
99 interrupt handler may touch this qtd! */
100 /* QTD_XFER_COMPLETE: payload has been transferred successfully */
101 /* QTD_RETIRE: transfer error/abort qtd */
102 #define QTD_ENQUEUED 0
103 #define QTD_PAYLOAD_ALLOC 1
104 #define QTD_XFER_STARTED 2
105 #define QTD_XFER_COMPLETE 3
106 #define QTD_RETIRE 4
107 u32 status;
108 };
109
110 /* Queue head, one for each active endpoint */
111 struct isp1760_qh {
112 struct list_head qh_list;
113 struct list_head qtd_list;
114 u32 toggle;
115 u32 ping;
116 int slot;
117 int tt_buffer_dirty; /* See USB2.0 spec section 11.17.5 */
118 };
119
120 struct urb_listitem {
121 struct list_head urb_list;
122 struct urb *urb;
123 };
124
125 /*
126 * Access functions for isp176x registers (addresses 0..0x03FF).
127 */
128 static u32 reg_read32(void __iomem *base, u32 reg)
129 {
130 return readl(base + reg);
131 }
132
133 static void reg_write32(void __iomem *base, u32 reg, u32 val)
134 {
135 writel(val, base + reg);
136 }
137
138 /*
139 * Access functions for isp176x memory (offset >= 0x0400).
140 *
141 * bank_reads8() reads memory locations prefetched by an earlier write to
142 * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
143 * bank optimizations, you should use the more generic mem_reads8() below.
144 *
145 * For access to ptd memory, use the specialized ptd_read() and ptd_write()
146 * below.
147 *
148 * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
149 * doesn't quite work because some people have to enforce 32-bit access
150 */
151 static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
152 __u32 *dst, u32 bytes)
153 {
154 __u32 __iomem *src;
155 u32 val;
156 __u8 *src_byteptr;
157 __u8 *dst_byteptr;
158
159 src = src_base + (bank_addr | src_offset);
160
161 if (src_offset < PAYLOAD_OFFSET) {
162 while (bytes >= 4) {
163 *dst = le32_to_cpu(__raw_readl(src));
164 bytes -= 4;
165 src++;
166 dst++;
167 }
168 } else {
169 while (bytes >= 4) {
170 *dst = __raw_readl(src);
171 bytes -= 4;
172 src++;
173 dst++;
174 }
175 }
176
177 if (!bytes)
178 return;
179
180 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
181 * allocated.
182 */
183 if (src_offset < PAYLOAD_OFFSET)
184 val = le32_to_cpu(__raw_readl(src));
185 else
186 val = __raw_readl(src);
187
188 dst_byteptr = (void *) dst;
189 src_byteptr = (void *) &val;
190 while (bytes > 0) {
191 *dst_byteptr = *src_byteptr;
192 dst_byteptr++;
193 src_byteptr++;
194 bytes--;
195 }
196 }
197
198 static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst,
199 u32 bytes)
200 {
201 reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0));
202 ndelay(90);
203 bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes);
204 }
205
206 static void mem_writes8(void __iomem *dst_base, u32 dst_offset,
207 __u32 const *src, u32 bytes)
208 {
209 __u32 __iomem *dst;
210
211 dst = dst_base + dst_offset;
212
213 if (dst_offset < PAYLOAD_OFFSET) {
214 while (bytes >= 4) {
215 __raw_writel(cpu_to_le32(*src), dst);
216 bytes -= 4;
217 src++;
218 dst++;
219 }
220 } else {
221 while (bytes >= 4) {
222 __raw_writel(*src, dst);
223 bytes -= 4;
224 src++;
225 dst++;
226 }
227 }
228
229 if (!bytes)
230 return;
231 /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
232 * extra bytes should not be read by the HW.
233 */
234
235 if (dst_offset < PAYLOAD_OFFSET)
236 __raw_writel(cpu_to_le32(*src), dst);
237 else
238 __raw_writel(*src, dst);
239 }
240
241 /*
242 * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
243 * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
244 */
245 static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot,
246 struct ptd *ptd)
247 {
248 reg_write32(base, HC_MEMORY_REG,
249 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd));
250 ndelay(90);
251 bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0),
252 (void *) ptd, sizeof(*ptd));
253 }
254
255 static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
256 struct ptd *ptd)
257 {
258 mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0),
259 &ptd->dw1, 7*sizeof(ptd->dw1));
260 /* Make sure dw0 gets written last (after other dw's and after payload)
261 since it contains the enable bit */
262 wmb();
263 mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0,
264 sizeof(ptd->dw0));
265 }
266
267
268 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
269 static void init_memory(struct isp1760_hcd *priv)
270 {
271 int i, curr;
272 u32 payload_addr;
273
274 payload_addr = PAYLOAD_OFFSET;
275 for (i = 0; i < BLOCK_1_NUM; i++) {
276 priv->memory_pool[i].start = payload_addr;
277 priv->memory_pool[i].size = BLOCK_1_SIZE;
278 priv->memory_pool[i].free = 1;
279 payload_addr += priv->memory_pool[i].size;
280 }
281
282 curr = i;
283 for (i = 0; i < BLOCK_2_NUM; i++) {
284 priv->memory_pool[curr + i].start = payload_addr;
285 priv->memory_pool[curr + i].size = BLOCK_2_SIZE;
286 priv->memory_pool[curr + i].free = 1;
287 payload_addr += priv->memory_pool[curr + i].size;
288 }
289
290 curr = i;
291 for (i = 0; i < BLOCK_3_NUM; i++) {
292 priv->memory_pool[curr + i].start = payload_addr;
293 priv->memory_pool[curr + i].size = BLOCK_3_SIZE;
294 priv->memory_pool[curr + i].free = 1;
295 payload_addr += priv->memory_pool[curr + i].size;
296 }
297
298 WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
299 }
300
301 static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
302 {
303 struct isp1760_hcd *priv = hcd_to_priv(hcd);
304 int i;
305
306 WARN_ON(qtd->payload_addr);
307
308 if (!qtd->length)
309 return;
310
311 for (i = 0; i < BLOCKS; i++) {
312 if (priv->memory_pool[i].size >= qtd->length &&
313 priv->memory_pool[i].free) {
314 priv->memory_pool[i].free = 0;
315 qtd->payload_addr = priv->memory_pool[i].start;
316 return;
317 }
318 }
319 }
320
321 static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
322 {
323 struct isp1760_hcd *priv = hcd_to_priv(hcd);
324 int i;
325
326 if (!qtd->payload_addr)
327 return;
328
329 for (i = 0; i < BLOCKS; i++) {
330 if (priv->memory_pool[i].start == qtd->payload_addr) {
331 WARN_ON(priv->memory_pool[i].free);
332 priv->memory_pool[i].free = 1;
333 qtd->payload_addr = 0;
334 return;
335 }
336 }
337
338 dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
339 __func__, qtd->payload_addr);
340 WARN_ON(1);
341 qtd->payload_addr = 0;
342 }
343
344 static int handshake(struct usb_hcd *hcd, u32 reg,
345 u32 mask, u32 done, int usec)
346 {
347 u32 result;
348
349 do {
350 result = reg_read32(hcd->regs, reg);
351 if (result == ~0)
352 return -ENODEV;
353 result &= mask;
354 if (result == done)
355 return 0;
356 udelay(1);
357 usec--;
358 } while (usec > 0);
359 return -ETIMEDOUT;
360 }
361
362 /* reset a non-running (STS_HALT == 1) controller */
363 static int ehci_reset(struct usb_hcd *hcd)
364 {
365 int retval;
366 struct isp1760_hcd *priv = hcd_to_priv(hcd);
367
368 u32 command = reg_read32(hcd->regs, HC_USBCMD);
369
370 command |= CMD_RESET;
371 reg_write32(hcd->regs, HC_USBCMD, command);
372 hcd->state = HC_STATE_HALT;
373 priv->next_statechange = jiffies;
374 retval = handshake(hcd, HC_USBCMD,
375 CMD_RESET, 0, 250 * 1000);
376 return retval;
377 }
378
379 static struct isp1760_qh *qh_alloc(gfp_t flags)
380 {
381 struct isp1760_qh *qh;
382
383 qh = kmem_cache_zalloc(qh_cachep, flags);
384 if (!qh)
385 return NULL;
386
387 INIT_LIST_HEAD(&qh->qh_list);
388 INIT_LIST_HEAD(&qh->qtd_list);
389 qh->slot = -1;
390
391 return qh;
392 }
393
394 static void qh_free(struct isp1760_qh *qh)
395 {
396 WARN_ON(!list_empty(&qh->qtd_list));
397 WARN_ON(qh->slot > -1);
398 kmem_cache_free(qh_cachep, qh);
399 }
400
401 /* one-time init, only for memory state */
402 static int priv_init(struct usb_hcd *hcd)
403 {
404 struct isp1760_hcd *priv = hcd_to_priv(hcd);
405 u32 hcc_params;
406
407 spin_lock_init(&priv->lock);
408
409 INIT_LIST_HEAD(&priv->interruptqhs);
410 INIT_LIST_HEAD(&priv->controlqhs);
411 INIT_LIST_HEAD(&priv->bulkqhs);
412
413 /*
414 * hw default: 1K periodic list heads, one per frame.
415 * periodic_size can shrink by USBCMD update if hcc_params allows.
416 */
417 priv->periodic_size = DEFAULT_I_TDPS;
418
419 /* controllers may cache some of the periodic schedule ... */
420 hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS);
421 /* full frame cache */
422 if (HCC_ISOC_CACHE(hcc_params))
423 priv->i_thresh = 8;
424 else /* N microframes cached */
425 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
426
427 return 0;
428 }
429
430 static int isp1760_hc_setup(struct usb_hcd *hcd)
431 {
432 struct isp1760_hcd *priv = hcd_to_priv(hcd);
433 int result;
434 u32 scratch, hwmode;
435
436 /* Setup HW Mode Control: This assumes a level active-low interrupt */
437 hwmode = HW_DATA_BUS_32BIT;
438
439 if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
440 hwmode &= ~HW_DATA_BUS_32BIT;
441 if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
442 hwmode |= HW_ANA_DIGI_OC;
443 if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
444 hwmode |= HW_DACK_POL_HIGH;
445 if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
446 hwmode |= HW_DREQ_POL_HIGH;
447 if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH)
448 hwmode |= HW_INTR_HIGH_ACT;
449 if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG)
450 hwmode |= HW_INTR_EDGE_TRIG;
451
452 /*
453 * We have to set this first in case we're in 16-bit mode.
454 * Write it twice to ensure correct upper bits if switching
455 * to 16-bit mode.
456 */
457 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
458 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
459
460 reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe);
461 /* Change bus pattern */
462 scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG);
463 scratch = reg_read32(hcd->regs, HC_SCRATCH_REG);
464 if (scratch != 0xdeadbabe) {
465 dev_err(hcd->self.controller, "Scratch test failed.\n");
466 return -ENODEV;
467 }
468
469 /* pre reset */
470 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
471 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
472 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
473 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
474
475 /* reset */
476 reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL);
477 mdelay(100);
478
479 reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC);
480 mdelay(100);
481
482 result = ehci_reset(hcd);
483 if (result)
484 return result;
485
486 /* Step 11 passed */
487
488 dev_info(hcd->self.controller, "bus width: %d, oc: %s\n",
489 (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
490 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
491 "analog" : "digital");
492
493 /* ATL reset */
494 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET);
495 mdelay(10);
496 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
497
498 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK);
499
500 /*
501 * PORT 1 Control register of the ISP1760 is the OTG control
502 * register on ISP1761. Since there is no OTG or device controller
503 * support in this driver, we use port 1 as a "normal" USB host port on
504 * both chips.
505 */
506 reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2);
507 mdelay(10);
508
509 priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS);
510
511 return priv_init(hcd);
512 }
513
514 static u32 base_to_chip(u32 base)
515 {
516 return ((base - 0x400) >> 3);
517 }
518
519 static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
520 {
521 struct urb *urb;
522
523 if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
524 return 1;
525
526 urb = qtd->urb;
527 qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
528 return (qtd->urb != urb);
529 }
530
531 /* magic numbers that can affect system performance */
532 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
533 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
534 #define EHCI_TUNE_RL_TT 0
535 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
536 #define EHCI_TUNE_MULT_TT 1
537 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
538
539 static void create_ptd_atl(struct isp1760_qh *qh,
540 struct isp1760_qtd *qtd, struct ptd *ptd)
541 {
542 u32 maxpacket;
543 u32 multi;
544 u32 rl = RL_COUNTER;
545 u32 nak = NAK_COUNTER;
546
547 memset(ptd, 0, sizeof(*ptd));
548
549 /* according to 3.6.2, max packet len can not be > 0x400 */
550 maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
551 usb_pipeout(qtd->urb->pipe));
552 multi = 1 + ((maxpacket >> 11) & 0x3);
553 maxpacket &= 0x7ff;
554
555 /* DW0 */
556 ptd->dw0 = DW0_VALID_BIT;
557 ptd->dw0 |= TO_DW0_LENGTH(qtd->length);
558 ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket);
559 ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
560
561 /* DW1 */
562 ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1;
563 ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
564 ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type);
565
566 if (usb_pipebulk(qtd->urb->pipe))
567 ptd->dw1 |= DW1_TRANS_BULK;
568 else if (usb_pipeint(qtd->urb->pipe))
569 ptd->dw1 |= DW1_TRANS_INT;
570
571 if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
572 /* split transaction */
573
574 ptd->dw1 |= DW1_TRANS_SPLIT;
575 if (qtd->urb->dev->speed == USB_SPEED_LOW)
576 ptd->dw1 |= DW1_SE_USB_LOSPEED;
577
578 ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport);
579 ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
580
581 /* SE bit for Split INT transfers */
582 if (usb_pipeint(qtd->urb->pipe) &&
583 (qtd->urb->dev->speed == USB_SPEED_LOW))
584 ptd->dw1 |= 2 << 16;
585
586 rl = 0;
587 nak = 0;
588 } else {
589 ptd->dw0 |= TO_DW0_MULTI(multi);
590 if (usb_pipecontrol(qtd->urb->pipe) ||
591 usb_pipebulk(qtd->urb->pipe))
592 ptd->dw3 |= TO_DW3_PING(qh->ping);
593 }
594 /* DW2 */
595 ptd->dw2 = 0;
596 ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
597 ptd->dw2 |= TO_DW2_RL(rl);
598
599 /* DW3 */
600 ptd->dw3 |= TO_DW3_NAKCOUNT(nak);
601 ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle);
602 if (usb_pipecontrol(qtd->urb->pipe)) {
603 if (qtd->data_buffer == qtd->urb->setup_packet)
604 ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1);
605 else if (last_qtd_of_urb(qtd, qh))
606 ptd->dw3 |= TO_DW3_DATA_TOGGLE(1);
607 }
608
609 ptd->dw3 |= DW3_ACTIVE_BIT;
610 /* Cerr */
611 ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER);
612 }
613
614 static void transform_add_int(struct isp1760_qh *qh,
615 struct isp1760_qtd *qtd, struct ptd *ptd)
616 {
617 u32 usof;
618 u32 period;
619
620 /*
621 * Most of this is guessing. ISP1761 datasheet is quite unclear, and
622 * the algorithm from the original Philips driver code, which was
623 * pretty much used in this driver before as well, is quite horrendous
624 * and, i believe, incorrect. The code below follows the datasheet and
625 * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
626 * more reliable this way (fingers crossed...).
627 */
628
629 if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
630 /* urb->interval is in units of microframes (1/8 ms) */
631 period = qtd->urb->interval >> 3;
632
633 if (qtd->urb->interval > 4)
634 usof = 0x01; /* One bit set =>
635 interval 1 ms * uFrame-match */
636 else if (qtd->urb->interval > 2)
637 usof = 0x22; /* Two bits set => interval 1/2 ms */
638 else if (qtd->urb->interval > 1)
639 usof = 0x55; /* Four bits set => interval 1/4 ms */
640 else
641 usof = 0xff; /* All bits set => interval 1/8 ms */
642 } else {
643 /* urb->interval is in units of frames (1 ms) */
644 period = qtd->urb->interval;
645 usof = 0x0f; /* Execute Start Split on any of the
646 four first uFrames */
647
648 /*
649 * First 8 bits in dw5 is uSCS and "specifies which uSOF the
650 * complete split needs to be sent. Valid only for IN." Also,
651 * "All bits can be set to one for every transfer." (p 82,
652 * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
653 * that number come from? 0xff seems to work fine...
654 */
655 /* ptd->dw5 = 0x1c; */
656 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */
657 }
658
659 period = period >> 1;/* Ensure equal or shorter period than requested */
660 period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
661
662 ptd->dw2 |= period;
663 ptd->dw4 = usof;
664 }
665
666 static void create_ptd_int(struct isp1760_qh *qh,
667 struct isp1760_qtd *qtd, struct ptd *ptd)
668 {
669 create_ptd_atl(qh, qtd, ptd);
670 transform_add_int(qh, qtd, ptd);
671 }
672
673 static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
674 __releases(priv->lock)
675 __acquires(priv->lock)
676 {
677 struct isp1760_hcd *priv = hcd_to_priv(hcd);
678
679 if (!urb->unlinked) {
680 if (urb->status == -EINPROGRESS)
681 urb->status = 0;
682 }
683
684 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
685 void *ptr;
686 for (ptr = urb->transfer_buffer;
687 ptr < urb->transfer_buffer + urb->transfer_buffer_length;
688 ptr += PAGE_SIZE)
689 flush_dcache_page(virt_to_page(ptr));
690 }
691
692 /* complete() can reenter this HCD */
693 usb_hcd_unlink_urb_from_ep(hcd, urb);
694 spin_unlock(&priv->lock);
695 usb_hcd_giveback_urb(hcd, urb, urb->status);
696 spin_lock(&priv->lock);
697 }
698
699 static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb,
700 u8 packet_type)
701 {
702 struct isp1760_qtd *qtd;
703
704 qtd = kmem_cache_zalloc(qtd_cachep, flags);
705 if (!qtd)
706 return NULL;
707
708 INIT_LIST_HEAD(&qtd->qtd_list);
709 qtd->urb = urb;
710 qtd->packet_type = packet_type;
711 qtd->status = QTD_ENQUEUED;
712 qtd->actual_length = 0;
713
714 return qtd;
715 }
716
717 static void qtd_free(struct isp1760_qtd *qtd)
718 {
719 WARN_ON(qtd->payload_addr);
720 kmem_cache_free(qtd_cachep, qtd);
721 }
722
723 static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot,
724 struct slotinfo *slots, struct isp1760_qtd *qtd,
725 struct isp1760_qh *qh, struct ptd *ptd)
726 {
727 struct isp1760_hcd *priv = hcd_to_priv(hcd);
728 int skip_map;
729
730 WARN_ON((slot < 0) || (slot > 31));
731 WARN_ON(qtd->length && !qtd->payload_addr);
732 WARN_ON(slots[slot].qtd);
733 WARN_ON(slots[slot].qh);
734 WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC);
735
736 /* Make sure done map has not triggered from some unlinked transfer */
737 if (ptd_offset == ATL_PTD_OFFSET) {
738 priv->atl_done_map |= reg_read32(hcd->regs,
739 HC_ATL_PTD_DONEMAP_REG);
740 priv->atl_done_map &= ~(1 << slot);
741 } else {
742 priv->int_done_map |= reg_read32(hcd->regs,
743 HC_INT_PTD_DONEMAP_REG);
744 priv->int_done_map &= ~(1 << slot);
745 }
746
747 qh->slot = slot;
748 qtd->status = QTD_XFER_STARTED;
749 slots[slot].timestamp = jiffies;
750 slots[slot].qtd = qtd;
751 slots[slot].qh = qh;
752 ptd_write(hcd->regs, ptd_offset, slot, ptd);
753
754 if (ptd_offset == ATL_PTD_OFFSET) {
755 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
756 skip_map &= ~(1 << qh->slot);
757 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
758 } else {
759 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
760 skip_map &= ~(1 << qh->slot);
761 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
762 }
763 }
764
765 static int is_short_bulk(struct isp1760_qtd *qtd)
766 {
767 return (usb_pipebulk(qtd->urb->pipe) &&
768 (qtd->actual_length < qtd->length));
769 }
770
771 static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh,
772 struct list_head *urb_list)
773 {
774 int last_qtd;
775 struct isp1760_qtd *qtd, *qtd_next;
776 struct urb_listitem *urb_listitem;
777
778 list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) {
779 if (qtd->status < QTD_XFER_COMPLETE)
780 break;
781
782 last_qtd = last_qtd_of_urb(qtd, qh);
783
784 if ((!last_qtd) && (qtd->status == QTD_RETIRE))
785 qtd_next->status = QTD_RETIRE;
786
787 if (qtd->status == QTD_XFER_COMPLETE) {
788 if (qtd->actual_length) {
789 switch (qtd->packet_type) {
790 case IN_PID:
791 mem_reads8(hcd->regs, qtd->payload_addr,
792 qtd->data_buffer,
793 qtd->actual_length);
794 /* Fall through (?) */
795 case OUT_PID:
796 qtd->urb->actual_length +=
797 qtd->actual_length;
798 /* Fall through ... */
799 case SETUP_PID:
800 break;
801 }
802 }
803
804 if (is_short_bulk(qtd)) {
805 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK)
806 qtd->urb->status = -EREMOTEIO;
807 if (!last_qtd)
808 qtd_next->status = QTD_RETIRE;
809 }
810 }
811
812 if (qtd->payload_addr)
813 free_mem(hcd, qtd);
814
815 if (last_qtd) {
816 if ((qtd->status == QTD_RETIRE) &&
817 (qtd->urb->status == -EINPROGRESS))
818 qtd->urb->status = -EPIPE;
819 /* Defer calling of urb_done() since it releases lock */
820 urb_listitem = kmem_cache_zalloc(urb_listitem_cachep,
821 GFP_ATOMIC);
822 if (unlikely(!urb_listitem))
823 break; /* Try again on next call */
824 urb_listitem->urb = qtd->urb;
825 list_add_tail(&urb_listitem->urb_list, urb_list);
826 }
827
828 list_del(&qtd->qtd_list);
829 qtd_free(qtd);
830 }
831 }
832
833 #define ENQUEUE_DEPTH 2
834 static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh)
835 {
836 struct isp1760_hcd *priv = hcd_to_priv(hcd);
837 int ptd_offset;
838 struct slotinfo *slots;
839 int curr_slot, free_slot;
840 int n;
841 struct ptd ptd;
842 struct isp1760_qtd *qtd;
843
844 if (unlikely(list_empty(&qh->qtd_list))) {
845 WARN_ON(1);
846 return;
847 }
848
849 /* Make sure this endpoint's TT buffer is clean before queueing ptds */
850 if (qh->tt_buffer_dirty)
851 return;
852
853 if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd,
854 qtd_list)->urb->pipe)) {
855 ptd_offset = INT_PTD_OFFSET;
856 slots = priv->int_slots;
857 } else {
858 ptd_offset = ATL_PTD_OFFSET;
859 slots = priv->atl_slots;
860 }
861
862 free_slot = -1;
863 for (curr_slot = 0; curr_slot < 32; curr_slot++) {
864 if ((free_slot == -1) && (slots[curr_slot].qtd == NULL))
865 free_slot = curr_slot;
866 if (slots[curr_slot].qh == qh)
867 break;
868 }
869
870 n = 0;
871 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
872 if (qtd->status == QTD_ENQUEUED) {
873 WARN_ON(qtd->payload_addr);
874 alloc_mem(hcd, qtd);
875 if ((qtd->length) && (!qtd->payload_addr))
876 break;
877
878 if ((qtd->length) &&
879 ((qtd->packet_type == SETUP_PID) ||
880 (qtd->packet_type == OUT_PID))) {
881 mem_writes8(hcd->regs, qtd->payload_addr,
882 qtd->data_buffer, qtd->length);
883 }
884
885 qtd->status = QTD_PAYLOAD_ALLOC;
886 }
887
888 if (qtd->status == QTD_PAYLOAD_ALLOC) {
889 /*
890 if ((curr_slot > 31) && (free_slot == -1))
891 dev_dbg(hcd->self.controller, "%s: No slot "
892 "available for transfer\n", __func__);
893 */
894 /* Start xfer for this endpoint if not already done */
895 if ((curr_slot > 31) && (free_slot > -1)) {
896 if (usb_pipeint(qtd->urb->pipe))
897 create_ptd_int(qh, qtd, &ptd);
898 else
899 create_ptd_atl(qh, qtd, &ptd);
900
901 start_bus_transfer(hcd, ptd_offset, free_slot,
902 slots, qtd, qh, &ptd);
903 curr_slot = free_slot;
904 }
905
906 n++;
907 if (n >= ENQUEUE_DEPTH)
908 break;
909 }
910 }
911 }
912
913 void schedule_ptds(struct usb_hcd *hcd)
914 {
915 struct isp1760_hcd *priv;
916 struct isp1760_qh *qh, *qh_next;
917 struct list_head *ep_queue;
918 struct usb_host_endpoint *ep;
919 LIST_HEAD(urb_list);
920 struct urb_listitem *urb_listitem, *urb_listitem_next;
921
922 if (!hcd) {
923 WARN_ON(1);
924 return;
925 }
926
927 priv = hcd_to_priv(hcd);
928
929 /*
930 * check finished/retired xfers, transfer payloads, call urb_done()
931 */
932 ep_queue = &priv->interruptqhs;
933 while (ep_queue) {
934 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) {
935 ep = list_entry(qh->qtd_list.next, struct isp1760_qtd,
936 qtd_list)->urb->ep;
937 collect_qtds(hcd, qh, &urb_list);
938 if (list_empty(&qh->qtd_list)) {
939 list_del(&qh->qh_list);
940 if (ep->hcpriv == NULL) {
941 /* Endpoint has been disabled, so we
942 can free the associated queue head. */
943 qh_free(qh);
944 }
945 }
946 }
947
948 if (ep_queue == &priv->interruptqhs)
949 ep_queue = &priv->controlqhs;
950 else if (ep_queue == &priv->controlqhs)
951 ep_queue = &priv->bulkqhs;
952 else
953 ep_queue = NULL;
954 }
955
956 list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list,
957 urb_list) {
958 isp1760_urb_done(hcd, urb_listitem->urb);
959 kmem_cache_free(urb_listitem_cachep, urb_listitem);
960 }
961
962 /*
963 * Schedule packets for transfer.
964 *
965 * According to USB2.0 specification:
966 *
967 * 1st prio: interrupt xfers, up to 80 % of bandwidth
968 * 2nd prio: control xfers
969 * 3rd prio: bulk xfers
970 *
971 * ... but let's use a simpler scheme here (mostly because ISP1761 doc
972 * is very unclear on how to prioritize traffic):
973 *
974 * 1) Enqueue any queued control transfers, as long as payload chip mem
975 * and PTD ATL slots are available.
976 * 2) Enqueue any queued INT transfers, as long as payload chip mem
977 * and PTD INT slots are available.
978 * 3) Enqueue any queued bulk transfers, as long as payload chip mem
979 * and PTD ATL slots are available.
980 *
981 * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between
982 * conservation of chip mem and performance.
983 *
984 * I'm sure this scheme could be improved upon!
985 */
986 ep_queue = &priv->controlqhs;
987 while (ep_queue) {
988 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list)
989 enqueue_qtds(hcd, qh);
990
991 if (ep_queue == &priv->controlqhs)
992 ep_queue = &priv->interruptqhs;
993 else if (ep_queue == &priv->interruptqhs)
994 ep_queue = &priv->bulkqhs;
995 else
996 ep_queue = NULL;
997 }
998 }
999
1000 #define PTD_STATE_QTD_DONE 1
1001 #define PTD_STATE_QTD_RELOAD 2
1002 #define PTD_STATE_URB_RETIRE 3
1003
1004 static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1005 struct urb *urb)
1006 {
1007 __dw dw4;
1008 int i;
1009
1010 dw4 = ptd->dw4;
1011 dw4 >>= 8;
1012
1013 /* FIXME: ISP1761 datasheet does not say what to do with these. Do we
1014 need to handle these errors? Is it done in hardware? */
1015
1016 if (ptd->dw3 & DW3_HALT_BIT) {
1017
1018 urb->status = -EPROTO; /* Default unknown error */
1019
1020 for (i = 0; i < 8; i++) {
1021 switch (dw4 & 0x7) {
1022 case INT_UNDERRUN:
1023 dev_dbg(hcd->self.controller, "%s: underrun "
1024 "during uFrame %d\n",
1025 __func__, i);
1026 urb->status = -ECOMM; /* Could not write data */
1027 break;
1028 case INT_EXACT:
1029 dev_dbg(hcd->self.controller, "%s: transaction "
1030 "error during uFrame %d\n",
1031 __func__, i);
1032 urb->status = -EPROTO; /* timeout, bad CRC, PID
1033 error etc. */
1034 break;
1035 case INT_BABBLE:
1036 dev_dbg(hcd->self.controller, "%s: babble "
1037 "error during uFrame %d\n",
1038 __func__, i);
1039 urb->status = -EOVERFLOW;
1040 break;
1041 }
1042 dw4 >>= 3;
1043 }
1044
1045 return PTD_STATE_URB_RETIRE;
1046 }
1047
1048 return PTD_STATE_QTD_DONE;
1049 }
1050
1051 static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1052 struct urb *urb)
1053 {
1054 WARN_ON(!ptd);
1055 if (ptd->dw3 & DW3_HALT_BIT) {
1056 if (ptd->dw3 & DW3_BABBLE_BIT)
1057 urb->status = -EOVERFLOW;
1058 else if (FROM_DW3_CERR(ptd->dw3))
1059 urb->status = -EPIPE; /* Stall */
1060 else if (ptd->dw3 & DW3_ERROR_BIT)
1061 urb->status = -EPROTO; /* XactErr */
1062 else
1063 urb->status = -EPROTO; /* Unknown */
1064 /*
1065 dev_dbg(hcd->self.controller, "%s: ptd error:\n"
1066 " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n"
1067 " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n",
1068 __func__,
1069 ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3,
1070 ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7);
1071 */
1072 return PTD_STATE_URB_RETIRE;
1073 }
1074
1075 if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1076 /* Transfer Error, *but* active and no HALT -> reload */
1077 dev_dbg(hcd->self.controller, "PID error; reloading ptd\n");
1078 return PTD_STATE_QTD_RELOAD;
1079 }
1080
1081 if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1082 /*
1083 * NAKs are handled in HW by the chip. Usually if the
1084 * device is not able to send data fast enough.
1085 * This happens mostly on slower hardware.
1086 */
1087 return PTD_STATE_QTD_RELOAD;
1088 }
1089
1090 return PTD_STATE_QTD_DONE;
1091 }
1092
1093 static void handle_done_ptds(struct usb_hcd *hcd)
1094 {
1095 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1096 struct ptd ptd;
1097 struct isp1760_qh *qh;
1098 int slot;
1099 int state;
1100 struct slotinfo *slots;
1101 u32 ptd_offset;
1102 struct isp1760_qtd *qtd;
1103 int modified;
1104 int skip_map;
1105
1106 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1107 priv->int_done_map &= ~skip_map;
1108 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1109 priv->atl_done_map &= ~skip_map;
1110
1111 modified = priv->int_done_map || priv->atl_done_map;
1112
1113 while (priv->int_done_map || priv->atl_done_map) {
1114 if (priv->int_done_map) {
1115 /* INT ptd */
1116 slot = __ffs(priv->int_done_map);
1117 priv->int_done_map &= ~(1 << slot);
1118 slots = priv->int_slots;
1119 /* This should not trigger, and could be removed if
1120 noone have any problems with it triggering: */
1121 if (!slots[slot].qh) {
1122 WARN_ON(1);
1123 continue;
1124 }
1125 ptd_offset = INT_PTD_OFFSET;
1126 ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
1127 state = check_int_transfer(hcd, &ptd,
1128 slots[slot].qtd->urb);
1129 } else {
1130 /* ATL ptd */
1131 slot = __ffs(priv->atl_done_map);
1132 priv->atl_done_map &= ~(1 << slot);
1133 slots = priv->atl_slots;
1134 /* This should not trigger, and could be removed if
1135 noone have any problems with it triggering: */
1136 if (!slots[slot].qh) {
1137 WARN_ON(1);
1138 continue;
1139 }
1140 ptd_offset = ATL_PTD_OFFSET;
1141 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1142 state = check_atl_transfer(hcd, &ptd,
1143 slots[slot].qtd->urb);
1144 }
1145
1146 qtd = slots[slot].qtd;
1147 slots[slot].qtd = NULL;
1148 qh = slots[slot].qh;
1149 slots[slot].qh = NULL;
1150 qh->slot = -1;
1151
1152 WARN_ON(qtd->status != QTD_XFER_STARTED);
1153
1154 switch (state) {
1155 case PTD_STATE_QTD_DONE:
1156 if ((usb_pipeint(qtd->urb->pipe)) &&
1157 (qtd->urb->dev->speed != USB_SPEED_HIGH))
1158 qtd->actual_length =
1159 FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3);
1160 else
1161 qtd->actual_length =
1162 FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3);
1163
1164 qtd->status = QTD_XFER_COMPLETE;
1165 if (list_is_last(&qtd->qtd_list, &qh->qtd_list) ||
1166 is_short_bulk(qtd))
1167 qtd = NULL;
1168 else
1169 qtd = list_entry(qtd->qtd_list.next,
1170 typeof(*qtd), qtd_list);
1171
1172 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1173 qh->ping = FROM_DW3_PING(ptd.dw3);
1174 break;
1175
1176 case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */
1177 qtd->status = QTD_PAYLOAD_ALLOC;
1178 ptd.dw0 |= DW0_VALID_BIT;
1179 /* RL counter = ERR counter */
1180 ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf);
1181 ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2));
1182 ptd.dw3 &= ~TO_DW3_CERR(3);
1183 ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER);
1184 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1185 qh->ping = FROM_DW3_PING(ptd.dw3);
1186 break;
1187
1188 case PTD_STATE_URB_RETIRE:
1189 qtd->status = QTD_RETIRE;
1190 if ((qtd->urb->dev->speed != USB_SPEED_HIGH) &&
1191 (qtd->urb->status != -EPIPE) &&
1192 (qtd->urb->status != -EREMOTEIO)) {
1193 qh->tt_buffer_dirty = 1;
1194 if (usb_hub_clear_tt_buffer(qtd->urb))
1195 /* Clear failed; let's hope things work
1196 anyway */
1197 qh->tt_buffer_dirty = 0;
1198 }
1199 qtd = NULL;
1200 qh->toggle = 0;
1201 qh->ping = 0;
1202 break;
1203
1204 default:
1205 WARN_ON(1);
1206 continue;
1207 }
1208
1209 if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) {
1210 if (slots == priv->int_slots) {
1211 if (state == PTD_STATE_QTD_RELOAD)
1212 dev_err(hcd->self.controller,
1213 "%s: PTD_STATE_QTD_RELOAD on "
1214 "interrupt packet\n", __func__);
1215 if (state != PTD_STATE_QTD_RELOAD)
1216 create_ptd_int(qh, qtd, &ptd);
1217 } else {
1218 if (state != PTD_STATE_QTD_RELOAD)
1219 create_ptd_atl(qh, qtd, &ptd);
1220 }
1221
1222 start_bus_transfer(hcd, ptd_offset, slot, slots, qtd,
1223 qh, &ptd);
1224 }
1225 }
1226
1227 if (modified)
1228 schedule_ptds(hcd);
1229 }
1230
1231 static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1232 {
1233 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1234 u32 imask;
1235 irqreturn_t irqret = IRQ_NONE;
1236
1237 spin_lock(&priv->lock);
1238
1239 if (!(hcd->state & HC_STATE_RUNNING))
1240 goto leave;
1241
1242 imask = reg_read32(hcd->regs, HC_INTERRUPT_REG);
1243 if (unlikely(!imask))
1244 goto leave;
1245 reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */
1246
1247 priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG);
1248 priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
1249
1250 handle_done_ptds(hcd);
1251
1252 irqret = IRQ_HANDLED;
1253 leave:
1254 spin_unlock(&priv->lock);
1255
1256 return irqret;
1257 }
1258
1259 /*
1260 * Workaround for problem described in chip errata 2:
1261 *
1262 * Sometimes interrupts are not generated when ATL (not INT?) completion occurs.
1263 * One solution suggested in the errata is to use SOF interrupts _instead_of_
1264 * ATL done interrupts (the "instead of" might be important since it seems
1265 * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget"
1266 * to set the PTD's done bit in addition to not generating an interrupt!).
1267 *
1268 * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their
1269 * done bit is not being set. This is bad - it blocks the endpoint until reboot.
1270 *
1271 * If we use SOF interrupts only, we get latency between ptd completion and the
1272 * actual handling. This is very noticeable in testusb runs which takes several
1273 * minutes longer without ATL interrupts.
1274 *
1275 * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it
1276 * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the
1277 * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered
1278 * completed and its done map bit is set.
1279 *
1280 * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen
1281 * not to cause too much lag when this HW bug occurs, while still hopefully
1282 * ensuring that the check does not falsely trigger.
1283 */
1284 #define SLOT_TIMEOUT 300
1285 #define SLOT_CHECK_PERIOD 200
1286 static struct timer_list errata2_timer;
1287
1288 void errata2_function(unsigned long data)
1289 {
1290 struct usb_hcd *hcd = (struct usb_hcd *) data;
1291 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1292 int slot;
1293 struct ptd ptd;
1294 unsigned long spinflags;
1295
1296 spin_lock_irqsave(&priv->lock, spinflags);
1297
1298 for (slot = 0; slot < 32; slot++)
1299 if (priv->atl_slots[slot].qh && time_after(jiffies,
1300 priv->atl_slots[slot].timestamp +
1301 SLOT_TIMEOUT * HZ / 1000)) {
1302 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1303 if (!FROM_DW0_VALID(ptd.dw0) &&
1304 !FROM_DW3_ACTIVE(ptd.dw3))
1305 priv->atl_done_map |= 1 << slot;
1306 }
1307
1308 if (priv->atl_done_map)
1309 handle_done_ptds(hcd);
1310
1311 spin_unlock_irqrestore(&priv->lock, spinflags);
1312
1313 errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000;
1314 add_timer(&errata2_timer);
1315 }
1316
1317 static int isp1760_run(struct usb_hcd *hcd)
1318 {
1319 int retval;
1320 u32 temp;
1321 u32 command;
1322 u32 chipid;
1323
1324 hcd->uses_new_polling = 1;
1325
1326 hcd->state = HC_STATE_RUNNING;
1327
1328 /* Set PTD interrupt AND & OR maps */
1329 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0);
1330 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff);
1331 reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0);
1332 reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff);
1333 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0);
1334 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff);
1335 /* step 23 passed */
1336
1337 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
1338 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN);
1339
1340 command = reg_read32(hcd->regs, HC_USBCMD);
1341 command &= ~(CMD_LRESET|CMD_RESET);
1342 command |= CMD_RUN;
1343 reg_write32(hcd->regs, HC_USBCMD, command);
1344
1345 retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000);
1346 if (retval)
1347 return retval;
1348
1349 /*
1350 * XXX
1351 * Spec says to write FLAG_CF as last config action, priv code grabs
1352 * the semaphore while doing so.
1353 */
1354 down_write(&ehci_cf_port_reset_rwsem);
1355 reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF);
1356
1357 retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000);
1358 up_write(&ehci_cf_port_reset_rwsem);
1359 if (retval)
1360 return retval;
1361
1362 init_timer(&errata2_timer);
1363 errata2_timer.function = errata2_function;
1364 errata2_timer.data = (unsigned long) hcd;
1365 errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000;
1366 add_timer(&errata2_timer);
1367
1368 chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG);
1369 dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n",
1370 chipid & 0xffff, chipid >> 16);
1371
1372 /* PTD Register Init Part 2, Step 28 */
1373
1374 /* Setup registers controlling PTD checking */
1375 reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000);
1376 reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000);
1377 reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001);
1378 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff);
1379 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff);
1380 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff);
1381 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG,
1382 ATL_BUF_FILL | INT_BUF_FILL);
1383
1384 /* GRR this is run-once init(), being done every time the HC starts.
1385 * So long as they're part of class devices, we can't do it init()
1386 * since the class device isn't created that early.
1387 */
1388 return 0;
1389 }
1390
1391 static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len)
1392 {
1393 qtd->data_buffer = databuffer;
1394
1395 if (len > MAX_PAYLOAD_SIZE)
1396 len = MAX_PAYLOAD_SIZE;
1397 qtd->length = len;
1398
1399 return qtd->length;
1400 }
1401
1402 static void qtd_list_free(struct list_head *qtd_list)
1403 {
1404 struct isp1760_qtd *qtd, *qtd_next;
1405
1406 list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) {
1407 list_del(&qtd->qtd_list);
1408 qtd_free(qtd);
1409 }
1410 }
1411
1412 /*
1413 * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize.
1414 * Also calculate the PID type (SETUP/IN/OUT) for each packet.
1415 */
1416 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1417 static void packetize_urb(struct usb_hcd *hcd,
1418 struct urb *urb, struct list_head *head, gfp_t flags)
1419 {
1420 struct isp1760_qtd *qtd;
1421 void *buf;
1422 int len, maxpacketsize;
1423 u8 packet_type;
1424
1425 /*
1426 * URBs map to sequences of QTDs: one logical transaction
1427 */
1428
1429 if (!urb->transfer_buffer && urb->transfer_buffer_length) {
1430 /* XXX This looks like usb storage / SCSI bug */
1431 dev_err(hcd->self.controller,
1432 "buf is null, dma is %08lx len is %d\n",
1433 (long unsigned)urb->transfer_dma,
1434 urb->transfer_buffer_length);
1435 WARN_ON(1);
1436 }
1437
1438 if (usb_pipein(urb->pipe))
1439 packet_type = IN_PID;
1440 else
1441 packet_type = OUT_PID;
1442
1443 if (usb_pipecontrol(urb->pipe)) {
1444 qtd = qtd_alloc(flags, urb, SETUP_PID);
1445 if (!qtd)
1446 goto cleanup;
1447 qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest));
1448 list_add_tail(&qtd->qtd_list, head);
1449
1450 /* for zero length DATA stages, STATUS is always IN */
1451 if (urb->transfer_buffer_length == 0)
1452 packet_type = IN_PID;
1453 }
1454
1455 maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe,
1456 usb_pipeout(urb->pipe)));
1457
1458 /*
1459 * buffer gets wrapped in one or more qtds;
1460 * last one may be "short" (including zero len)
1461 * and may serve as a control status ack
1462 */
1463 buf = urb->transfer_buffer;
1464 len = urb->transfer_buffer_length;
1465
1466 for (;;) {
1467 int this_qtd_len;
1468
1469 qtd = qtd_alloc(flags, urb, packet_type);
1470 if (!qtd)
1471 goto cleanup;
1472 this_qtd_len = qtd_fill(qtd, buf, len);
1473 list_add_tail(&qtd->qtd_list, head);
1474
1475 len -= this_qtd_len;
1476 buf += this_qtd_len;
1477
1478 if (len <= 0)
1479 break;
1480 }
1481
1482 /*
1483 * control requests may need a terminating data "status" ack;
1484 * bulk ones may need a terminating short packet (zero length).
1485 */
1486 if (urb->transfer_buffer_length != 0) {
1487 int one_more = 0;
1488
1489 if (usb_pipecontrol(urb->pipe)) {
1490 one_more = 1;
1491 if (packet_type == IN_PID)
1492 packet_type = OUT_PID;
1493 else
1494 packet_type = IN_PID;
1495 } else if (usb_pipebulk(urb->pipe)
1496 && (urb->transfer_flags & URB_ZERO_PACKET)
1497 && !(urb->transfer_buffer_length %
1498 maxpacketsize)) {
1499 one_more = 1;
1500 }
1501 if (one_more) {
1502 qtd = qtd_alloc(flags, urb, packet_type);
1503 if (!qtd)
1504 goto cleanup;
1505
1506 /* never any data in such packets */
1507 qtd_fill(qtd, NULL, 0);
1508 list_add_tail(&qtd->qtd_list, head);
1509 }
1510 }
1511
1512 return;
1513
1514 cleanup:
1515 qtd_list_free(head);
1516 }
1517
1518 static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1519 gfp_t mem_flags)
1520 {
1521 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1522 struct list_head *ep_queue;
1523 struct isp1760_qh *qh, *qhit;
1524 unsigned long spinflags;
1525 LIST_HEAD(new_qtds);
1526 int retval;
1527 int qh_in_queue;
1528
1529 switch (usb_pipetype(urb->pipe)) {
1530 case PIPE_CONTROL:
1531 ep_queue = &priv->controlqhs;
1532 break;
1533 case PIPE_BULK:
1534 ep_queue = &priv->bulkqhs;
1535 break;
1536 case PIPE_INTERRUPT:
1537 if (urb->interval < 0)
1538 return -EINVAL;
1539 /* FIXME: Check bandwidth */
1540 ep_queue = &priv->interruptqhs;
1541 break;
1542 case PIPE_ISOCHRONOUS:
1543 dev_err(hcd->self.controller, "%s: isochronous USB packets "
1544 "not yet supported\n",
1545 __func__);
1546 return -EPIPE;
1547 default:
1548 dev_err(hcd->self.controller, "%s: unknown pipe type\n",
1549 __func__);
1550 return -EPIPE;
1551 }
1552
1553 if (usb_pipein(urb->pipe))
1554 urb->actual_length = 0;
1555
1556 packetize_urb(hcd, urb, &new_qtds, mem_flags);
1557 if (list_empty(&new_qtds))
1558 return -ENOMEM;
1559
1560 retval = 0;
1561 spin_lock_irqsave(&priv->lock, spinflags);
1562
1563 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
1564 retval = -ESHUTDOWN;
1565 goto out;
1566 }
1567 retval = usb_hcd_link_urb_to_ep(hcd, urb);
1568 if (retval)
1569 goto out;
1570
1571 qh = urb->ep->hcpriv;
1572 if (qh) {
1573 qh_in_queue = 0;
1574 list_for_each_entry(qhit, ep_queue, qh_list) {
1575 if (qhit == qh) {
1576 qh_in_queue = 1;
1577 break;
1578 }
1579 }
1580 if (!qh_in_queue)
1581 list_add_tail(&qh->qh_list, ep_queue);
1582 } else {
1583 qh = qh_alloc(GFP_ATOMIC);
1584 if (!qh) {
1585 retval = -ENOMEM;
1586 usb_hcd_unlink_urb_from_ep(hcd, urb);
1587 goto out;
1588 }
1589 list_add_tail(&qh->qh_list, ep_queue);
1590 urb->ep->hcpriv = qh;
1591 }
1592
1593 list_splice_tail(&new_qtds, &qh->qtd_list);
1594 schedule_ptds(hcd);
1595
1596 out:
1597 spin_unlock_irqrestore(&priv->lock, spinflags);
1598 return retval;
1599 }
1600
1601 static void kill_transfer(struct usb_hcd *hcd, struct urb *urb,
1602 struct isp1760_qh *qh)
1603 {
1604 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1605 int skip_map;
1606
1607 WARN_ON(qh->slot == -1);
1608
1609 /* We need to forcefully reclaim the slot since some transfers never
1610 return, e.g. interrupt transfers and NAKed bulk transfers. */
1611 if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) {
1612 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1613 skip_map |= (1 << qh->slot);
1614 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
1615 priv->atl_slots[qh->slot].qh = NULL;
1616 priv->atl_slots[qh->slot].qtd = NULL;
1617 } else {
1618 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1619 skip_map |= (1 << qh->slot);
1620 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
1621 priv->int_slots[qh->slot].qh = NULL;
1622 priv->int_slots[qh->slot].qtd = NULL;
1623 }
1624
1625 qh->slot = -1;
1626 }
1627
1628 /*
1629 * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing
1630 * any active transfer belonging to the urb in the process.
1631 */
1632 static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
1633 struct isp1760_qtd *qtd)
1634 {
1635 struct urb *urb;
1636 int urb_was_running;
1637
1638 urb = qtd->urb;
1639 urb_was_running = 0;
1640 list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) {
1641 if (qtd->urb != urb)
1642 break;
1643
1644 if (qtd->status >= QTD_XFER_STARTED)
1645 urb_was_running = 1;
1646 if (last_qtd_of_urb(qtd, qh) &&
1647 (qtd->status >= QTD_XFER_COMPLETE))
1648 urb_was_running = 0;
1649
1650 if (qtd->status == QTD_XFER_STARTED)
1651 kill_transfer(hcd, urb, qh);
1652 qtd->status = QTD_RETIRE;
1653 }
1654
1655 if ((urb->dev->speed != USB_SPEED_HIGH) && urb_was_running) {
1656 qh->tt_buffer_dirty = 1;
1657 if (usb_hub_clear_tt_buffer(urb))
1658 /* Clear failed; let's hope things work anyway */
1659 qh->tt_buffer_dirty = 0;
1660 }
1661 }
1662
1663 static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1664 int status)
1665 {
1666 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1667 unsigned long spinflags;
1668 struct isp1760_qh *qh;
1669 struct isp1760_qtd *qtd;
1670 int retval = 0;
1671
1672 spin_lock_irqsave(&priv->lock, spinflags);
1673 retval = usb_hcd_check_unlink_urb(hcd, urb, status);
1674 if (retval)
1675 goto out;
1676
1677 qh = urb->ep->hcpriv;
1678 if (!qh) {
1679 retval = -EINVAL;
1680 goto out;
1681 }
1682
1683 list_for_each_entry(qtd, &qh->qtd_list, qtd_list)
1684 if (qtd->urb == urb) {
1685 dequeue_urb_from_qtd(hcd, qh, qtd);
1686 break;
1687 }
1688
1689 urb->status = status;
1690 schedule_ptds(hcd);
1691
1692 out:
1693 spin_unlock_irqrestore(&priv->lock, spinflags);
1694 return retval;
1695 }
1696
1697 static void isp1760_endpoint_disable(struct usb_hcd *hcd,
1698 struct usb_host_endpoint *ep)
1699 {
1700 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1701 unsigned long spinflags;
1702 struct isp1760_qh *qh;
1703 struct isp1760_qtd *qtd;
1704
1705 spin_lock_irqsave(&priv->lock, spinflags);
1706
1707 qh = ep->hcpriv;
1708 if (!qh)
1709 goto out;
1710
1711 list_for_each_entry(qtd, &qh->qtd_list, qtd_list)
1712 if (qtd->status != QTD_RETIRE) {
1713 dequeue_urb_from_qtd(hcd, qh, qtd);
1714 qtd->urb->status = -ECONNRESET;
1715 }
1716
1717 ep->hcpriv = NULL;
1718 /* Cannot free qh here since it will be parsed by schedule_ptds() */
1719
1720 schedule_ptds(hcd);
1721
1722 out:
1723 spin_unlock_irqrestore(&priv->lock, spinflags);
1724 }
1725
1726 static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1727 {
1728 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1729 u32 temp, status = 0;
1730 u32 mask;
1731 int retval = 1;
1732 unsigned long flags;
1733
1734 /* if !USB_SUSPEND, root hub timers won't get shut down ... */
1735 if (!HC_IS_RUNNING(hcd->state))
1736 return 0;
1737
1738 /* init status to no-changes */
1739 buf[0] = 0;
1740 mask = PORT_CSC;
1741
1742 spin_lock_irqsave(&priv->lock, flags);
1743 temp = reg_read32(hcd->regs, HC_PORTSC1);
1744
1745 if (temp & PORT_OWNER) {
1746 if (temp & PORT_CSC) {
1747 temp &= ~PORT_CSC;
1748 reg_write32(hcd->regs, HC_PORTSC1, temp);
1749 goto done;
1750 }
1751 }
1752
1753 /*
1754 * Return status information even for ports with OWNER set.
1755 * Otherwise khubd wouldn't see the disconnect event when a
1756 * high-speed device is switched over to the companion
1757 * controller by the user.
1758 */
1759
1760 if ((temp & mask) != 0
1761 || ((temp & PORT_RESUME) != 0
1762 && time_after_eq(jiffies,
1763 priv->reset_done))) {
1764 buf [0] |= 1 << (0 + 1);
1765 status = STS_PCD;
1766 }
1767 /* FIXME autosuspend idle root hubs */
1768 done:
1769 spin_unlock_irqrestore(&priv->lock, flags);
1770 return status ? retval : 0;
1771 }
1772
1773 static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1774 struct usb_hub_descriptor *desc)
1775 {
1776 int ports = HCS_N_PORTS(priv->hcs_params);
1777 u16 temp;
1778
1779 desc->bDescriptorType = 0x29;
1780 /* priv 1.0, 2.3.9 says 20ms max */
1781 desc->bPwrOn2PwrGood = 10;
1782 desc->bHubContrCurrent = 0;
1783
1784 desc->bNbrPorts = ports;
1785 temp = 1 + (ports / 8);
1786 desc->bDescLength = 7 + 2 * temp;
1787
1788 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1789 memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
1790 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
1791
1792 /* per-port overcurrent reporting */
1793 temp = 0x0008;
1794 if (HCS_PPC(priv->hcs_params))
1795 /* per-port power control */
1796 temp |= 0x0001;
1797 else
1798 /* no power switching */
1799 temp |= 0x0002;
1800 desc->wHubCharacteristics = cpu_to_le16(temp);
1801 }
1802
1803 #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1804
1805 static int check_reset_complete(struct usb_hcd *hcd, int index,
1806 int port_status)
1807 {
1808 if (!(port_status & PORT_CONNECT))
1809 return port_status;
1810
1811 /* if reset finished and it's still not enabled -- handoff */
1812 if (!(port_status & PORT_PE)) {
1813
1814 dev_info(hcd->self.controller,
1815 "port %d full speed --> companion\n",
1816 index + 1);
1817
1818 port_status |= PORT_OWNER;
1819 port_status &= ~PORT_RWC_BITS;
1820 reg_write32(hcd->regs, HC_PORTSC1, port_status);
1821
1822 } else
1823 dev_info(hcd->self.controller, "port %d high speed\n",
1824 index + 1);
1825
1826 return port_status;
1827 }
1828
1829 static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1830 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1831 {
1832 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1833 int ports = HCS_N_PORTS(priv->hcs_params);
1834 u32 temp, status;
1835 unsigned long flags;
1836 int retval = 0;
1837 unsigned selector;
1838
1839 /*
1840 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1841 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1842 * (track current state ourselves) ... blink for diagnostics,
1843 * power, "this is the one", etc. EHCI spec supports this.
1844 */
1845
1846 spin_lock_irqsave(&priv->lock, flags);
1847 switch (typeReq) {
1848 case ClearHubFeature:
1849 switch (wValue) {
1850 case C_HUB_LOCAL_POWER:
1851 case C_HUB_OVER_CURRENT:
1852 /* no hub-wide feature/status flags */
1853 break;
1854 default:
1855 goto error;
1856 }
1857 break;
1858 case ClearPortFeature:
1859 if (!wIndex || wIndex > ports)
1860 goto error;
1861 wIndex--;
1862 temp = reg_read32(hcd->regs, HC_PORTSC1);
1863
1864 /*
1865 * Even if OWNER is set, so the port is owned by the
1866 * companion controller, khubd needs to be able to clear
1867 * the port-change status bits (especially
1868 * USB_PORT_STAT_C_CONNECTION).
1869 */
1870
1871 switch (wValue) {
1872 case USB_PORT_FEAT_ENABLE:
1873 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE);
1874 break;
1875 case USB_PORT_FEAT_C_ENABLE:
1876 /* XXX error? */
1877 break;
1878 case USB_PORT_FEAT_SUSPEND:
1879 if (temp & PORT_RESET)
1880 goto error;
1881
1882 if (temp & PORT_SUSPEND) {
1883 if ((temp & PORT_PE) == 0)
1884 goto error;
1885 /* resume signaling for 20 msec */
1886 temp &= ~(PORT_RWC_BITS);
1887 reg_write32(hcd->regs, HC_PORTSC1,
1888 temp | PORT_RESUME);
1889 priv->reset_done = jiffies +
1890 msecs_to_jiffies(20);
1891 }
1892 break;
1893 case USB_PORT_FEAT_C_SUSPEND:
1894 /* we auto-clear this feature */
1895 break;
1896 case USB_PORT_FEAT_POWER:
1897 if (HCS_PPC(priv->hcs_params))
1898 reg_write32(hcd->regs, HC_PORTSC1,
1899 temp & ~PORT_POWER);
1900 break;
1901 case USB_PORT_FEAT_C_CONNECTION:
1902 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC);
1903 break;
1904 case USB_PORT_FEAT_C_OVER_CURRENT:
1905 /* XXX error ?*/
1906 break;
1907 case USB_PORT_FEAT_C_RESET:
1908 /* GetPortStatus clears reset */
1909 break;
1910 default:
1911 goto error;
1912 }
1913 reg_read32(hcd->regs, HC_USBCMD);
1914 break;
1915 case GetHubDescriptor:
1916 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1917 buf);
1918 break;
1919 case GetHubStatus:
1920 /* no hub-wide feature/status flags */
1921 memset(buf, 0, 4);
1922 break;
1923 case GetPortStatus:
1924 if (!wIndex || wIndex > ports)
1925 goto error;
1926 wIndex--;
1927 status = 0;
1928 temp = reg_read32(hcd->regs, HC_PORTSC1);
1929
1930 /* wPortChange bits */
1931 if (temp & PORT_CSC)
1932 status |= USB_PORT_STAT_C_CONNECTION << 16;
1933
1934
1935 /* whoever resumes must GetPortStatus to complete it!! */
1936 if (temp & PORT_RESUME) {
1937 dev_err(hcd->self.controller, "Port resume should be skipped.\n");
1938
1939 /* Remote Wakeup received? */
1940 if (!priv->reset_done) {
1941 /* resume signaling for 20 msec */
1942 priv->reset_done = jiffies
1943 + msecs_to_jiffies(20);
1944 /* check the port again */
1945 mod_timer(&hcd->rh_timer, priv->reset_done);
1946 }
1947
1948 /* resume completed? */
1949 else if (time_after_eq(jiffies,
1950 priv->reset_done)) {
1951 status |= USB_PORT_STAT_C_SUSPEND << 16;
1952 priv->reset_done = 0;
1953
1954 /* stop resume signaling */
1955 temp = reg_read32(hcd->regs, HC_PORTSC1);
1956 reg_write32(hcd->regs, HC_PORTSC1,
1957 temp & ~(PORT_RWC_BITS | PORT_RESUME));
1958 retval = handshake(hcd, HC_PORTSC1,
1959 PORT_RESUME, 0, 2000 /* 2msec */);
1960 if (retval != 0) {
1961 dev_err(hcd->self.controller,
1962 "port %d resume error %d\n",
1963 wIndex + 1, retval);
1964 goto error;
1965 }
1966 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
1967 }
1968 }
1969
1970 /* whoever resets must GetPortStatus to complete it!! */
1971 if ((temp & PORT_RESET)
1972 && time_after_eq(jiffies,
1973 priv->reset_done)) {
1974 status |= USB_PORT_STAT_C_RESET << 16;
1975 priv->reset_done = 0;
1976
1977 /* force reset to complete */
1978 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET);
1979 /* REVISIT: some hardware needs 550+ usec to clear
1980 * this bit; seems too long to spin routinely...
1981 */
1982 retval = handshake(hcd, HC_PORTSC1,
1983 PORT_RESET, 0, 750);
1984 if (retval != 0) {
1985 dev_err(hcd->self.controller, "port %d reset error %d\n",
1986 wIndex + 1, retval);
1987 goto error;
1988 }
1989
1990 /* see what we found out */
1991 temp = check_reset_complete(hcd, wIndex,
1992 reg_read32(hcd->regs, HC_PORTSC1));
1993 }
1994 /*
1995 * Even if OWNER is set, there's no harm letting khubd
1996 * see the wPortStatus values (they should all be 0 except
1997 * for PORT_POWER anyway).
1998 */
1999
2000 if (temp & PORT_OWNER)
2001 dev_err(hcd->self.controller, "PORT_OWNER is set\n");
2002
2003 if (temp & PORT_CONNECT) {
2004 status |= USB_PORT_STAT_CONNECTION;
2005 /* status may be from integrated TT */
2006 status |= USB_PORT_STAT_HIGH_SPEED;
2007 }
2008 if (temp & PORT_PE)
2009 status |= USB_PORT_STAT_ENABLE;
2010 if (temp & (PORT_SUSPEND|PORT_RESUME))
2011 status |= USB_PORT_STAT_SUSPEND;
2012 if (temp & PORT_RESET)
2013 status |= USB_PORT_STAT_RESET;
2014 if (temp & PORT_POWER)
2015 status |= USB_PORT_STAT_POWER;
2016
2017 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
2018 break;
2019 case SetHubFeature:
2020 switch (wValue) {
2021 case C_HUB_LOCAL_POWER:
2022 case C_HUB_OVER_CURRENT:
2023 /* no hub-wide feature/status flags */
2024 break;
2025 default:
2026 goto error;
2027 }
2028 break;
2029 case SetPortFeature:
2030 selector = wIndex >> 8;
2031 wIndex &= 0xff;
2032 if (!wIndex || wIndex > ports)
2033 goto error;
2034 wIndex--;
2035 temp = reg_read32(hcd->regs, HC_PORTSC1);
2036 if (temp & PORT_OWNER)
2037 break;
2038
2039 /* temp &= ~PORT_RWC_BITS; */
2040 switch (wValue) {
2041 case USB_PORT_FEAT_ENABLE:
2042 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE);
2043 break;
2044
2045 case USB_PORT_FEAT_SUSPEND:
2046 if ((temp & PORT_PE) == 0
2047 || (temp & PORT_RESET) != 0)
2048 goto error;
2049
2050 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND);
2051 break;
2052 case USB_PORT_FEAT_POWER:
2053 if (HCS_PPC(priv->hcs_params))
2054 reg_write32(hcd->regs, HC_PORTSC1,
2055 temp | PORT_POWER);
2056 break;
2057 case USB_PORT_FEAT_RESET:
2058 if (temp & PORT_RESUME)
2059 goto error;
2060 /* line status bits may report this as low speed,
2061 * which can be fine if this root hub has a
2062 * transaction translator built in.
2063 */
2064 if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
2065 && PORT_USB11(temp)) {
2066 temp |= PORT_OWNER;
2067 } else {
2068 temp |= PORT_RESET;
2069 temp &= ~PORT_PE;
2070
2071 /*
2072 * caller must wait, then call GetPortStatus
2073 * usb 2.0 spec says 50 ms resets on root
2074 */
2075 priv->reset_done = jiffies +
2076 msecs_to_jiffies(50);
2077 }
2078 reg_write32(hcd->regs, HC_PORTSC1, temp);
2079 break;
2080 default:
2081 goto error;
2082 }
2083 reg_read32(hcd->regs, HC_USBCMD);
2084 break;
2085
2086 default:
2087 error:
2088 /* "stall" on error */
2089 retval = -EPIPE;
2090 }
2091 spin_unlock_irqrestore(&priv->lock, flags);
2092 return retval;
2093 }
2094
2095 static int isp1760_get_frame(struct usb_hcd *hcd)
2096 {
2097 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2098 u32 fr;
2099
2100 fr = reg_read32(hcd->regs, HC_FRINDEX);
2101 return (fr >> 3) % priv->periodic_size;
2102 }
2103
2104 static void isp1760_stop(struct usb_hcd *hcd)
2105 {
2106 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2107 u32 temp;
2108
2109 del_timer(&errata2_timer);
2110
2111 isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2112 NULL, 0);
2113 mdelay(20);
2114
2115 spin_lock_irq(&priv->lock);
2116 ehci_reset(hcd);
2117 /* Disable IRQ */
2118 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2119 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2120 spin_unlock_irq(&priv->lock);
2121
2122 reg_write32(hcd->regs, HC_CONFIGFLAG, 0);
2123 }
2124
2125 static void isp1760_shutdown(struct usb_hcd *hcd)
2126 {
2127 u32 command, temp;
2128
2129 isp1760_stop(hcd);
2130 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2131 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2132
2133 command = reg_read32(hcd->regs, HC_USBCMD);
2134 command &= ~CMD_RUN;
2135 reg_write32(hcd->regs, HC_USBCMD, command);
2136 }
2137
2138 static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd,
2139 struct usb_host_endpoint *ep)
2140 {
2141 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2142 struct isp1760_qh *qh = ep->hcpriv;
2143 unsigned long spinflags;
2144
2145 if (!qh)
2146 return;
2147
2148 spin_lock_irqsave(&priv->lock, spinflags);
2149 qh->tt_buffer_dirty = 0;
2150 schedule_ptds(hcd);
2151 spin_unlock_irqrestore(&priv->lock, spinflags);
2152 }
2153
2154
2155 static const struct hc_driver isp1760_hc_driver = {
2156 .description = "isp1760-hcd",
2157 .product_desc = "NXP ISP1760 USB Host Controller",
2158 .hcd_priv_size = sizeof(struct isp1760_hcd),
2159 .irq = isp1760_irq,
2160 .flags = HCD_MEMORY | HCD_USB2,
2161 .reset = isp1760_hc_setup,
2162 .start = isp1760_run,
2163 .stop = isp1760_stop,
2164 .shutdown = isp1760_shutdown,
2165 .urb_enqueue = isp1760_urb_enqueue,
2166 .urb_dequeue = isp1760_urb_dequeue,
2167 .endpoint_disable = isp1760_endpoint_disable,
2168 .get_frame_number = isp1760_get_frame,
2169 .hub_status_data = isp1760_hub_status_data,
2170 .hub_control = isp1760_hub_control,
2171 .clear_tt_buffer_complete = isp1760_clear_tt_buffer_complete,
2172 };
2173
2174 int __init init_kmem_once(void)
2175 {
2176 urb_listitem_cachep = kmem_cache_create("isp1760 urb_listitem",
2177 sizeof(struct urb_listitem), 0, SLAB_TEMPORARY |
2178 SLAB_MEM_SPREAD, NULL);
2179
2180 if (!urb_listitem_cachep)
2181 return -ENOMEM;
2182
2183 qtd_cachep = kmem_cache_create("isp1760_qtd",
2184 sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2185 SLAB_MEM_SPREAD, NULL);
2186
2187 if (!qtd_cachep)
2188 return -ENOMEM;
2189
2190 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2191 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2192
2193 if (!qh_cachep) {
2194 kmem_cache_destroy(qtd_cachep);
2195 return -ENOMEM;
2196 }
2197
2198 return 0;
2199 }
2200
2201 void deinit_kmem_cache(void)
2202 {
2203 kmem_cache_destroy(qtd_cachep);
2204 kmem_cache_destroy(qh_cachep);
2205 kmem_cache_destroy(urb_listitem_cachep);
2206 }
2207
2208 struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len,
2209 int irq, unsigned long irqflags,
2210 struct device *dev, const char *busname,
2211 unsigned int devflags)
2212 {
2213 struct usb_hcd *hcd;
2214 struct isp1760_hcd *priv;
2215 int ret;
2216
2217 if (usb_disabled())
2218 return ERR_PTR(-ENODEV);
2219
2220 /* prevent usb-core allocating DMA pages */
2221 dev->dma_mask = NULL;
2222
2223 hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2224 if (!hcd)
2225 return ERR_PTR(-ENOMEM);
2226
2227 priv = hcd_to_priv(hcd);
2228 priv->devflags = devflags;
2229 init_memory(priv);
2230 hcd->regs = ioremap(res_start, res_len);
2231 if (!hcd->regs) {
2232 ret = -EIO;
2233 goto err_put;
2234 }
2235
2236 hcd->irq = irq;
2237 hcd->rsrc_start = res_start;
2238 hcd->rsrc_len = res_len;
2239
2240 ret = usb_add_hcd(hcd, irq, irqflags);
2241 if (ret)
2242 goto err_unmap;
2243
2244 return hcd;
2245
2246 err_unmap:
2247 iounmap(hcd->regs);
2248
2249 err_put:
2250 usb_put_hcd(hcd);
2251
2252 return ERR_PTR(ret);
2253 }
2254
2255 MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
2256 MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
2257 MODULE_LICENSE("GPL v2");
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