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Merge remote-tracking branch 'moduleh/module.h-split'
[linux-2.6/next.git] / drivers / video / omap2 / dss / dsi.c
blob7fdcc2047291e7876c87bfaa63824d53480c7318
1 /*
2 * linux/drivers/video/omap2/dss/dsi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #define DSS_SUBSYS_NAME "DSI"
21
22 #include <linux/kernel.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/module.h>
31 #include <linux/semaphore.h>
32 #include <linux/seq_file.h>
33 #include <linux/platform_device.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/wait.h>
36 #include <linux/workqueue.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/debugfs.h>
40 #include <linux/pm_runtime.h>
41
42 #include <video/omapdss.h>
43 #include <plat/clock.h>
44
45 #include "dss.h"
46 #include "dss_features.h"
47
48 /*#define VERBOSE_IRQ*/
49 #define DSI_CATCH_MISSING_TE
50
51 struct dsi_reg { u16 idx; };
52
53 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
54
55 #define DSI_SZ_REGS SZ_1K
56 /* DSI Protocol Engine */
57
58 #define DSI_REVISION DSI_REG(0x0000)
59 #define DSI_SYSCONFIG DSI_REG(0x0010)
60 #define DSI_SYSSTATUS DSI_REG(0x0014)
61 #define DSI_IRQSTATUS DSI_REG(0x0018)
62 #define DSI_IRQENABLE DSI_REG(0x001C)
63 #define DSI_CTRL DSI_REG(0x0040)
64 #define DSI_GNQ DSI_REG(0x0044)
65 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
66 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
67 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
68 #define DSI_CLK_CTRL DSI_REG(0x0054)
69 #define DSI_TIMING1 DSI_REG(0x0058)
70 #define DSI_TIMING2 DSI_REG(0x005C)
71 #define DSI_VM_TIMING1 DSI_REG(0x0060)
72 #define DSI_VM_TIMING2 DSI_REG(0x0064)
73 #define DSI_VM_TIMING3 DSI_REG(0x0068)
74 #define DSI_CLK_TIMING DSI_REG(0x006C)
75 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
76 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
77 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
78 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
79 #define DSI_VM_TIMING4 DSI_REG(0x0080)
80 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
81 #define DSI_VM_TIMING5 DSI_REG(0x0088)
82 #define DSI_VM_TIMING6 DSI_REG(0x008C)
83 #define DSI_VM_TIMING7 DSI_REG(0x0090)
84 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
85 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
86 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
87 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
88 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
89 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
90 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
91 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
92
93 /* DSIPHY_SCP */
94
95 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
96 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
97 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
98 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
99 #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028)
100
101 /* DSI_PLL_CTRL_SCP */
102
103 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
104 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
105 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
106 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
107 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
108
109 #define REG_GET(dsidev, idx, start, end) \
110 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
111
112 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
113 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
114
115 /* Global interrupts */
116 #define DSI_IRQ_VC0 (1 << 0)
117 #define DSI_IRQ_VC1 (1 << 1)
118 #define DSI_IRQ_VC2 (1 << 2)
119 #define DSI_IRQ_VC3 (1 << 3)
120 #define DSI_IRQ_WAKEUP (1 << 4)
121 #define DSI_IRQ_RESYNC (1 << 5)
122 #define DSI_IRQ_PLL_LOCK (1 << 7)
123 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
124 #define DSI_IRQ_PLL_RECALL (1 << 9)
125 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
126 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
127 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
128 #define DSI_IRQ_TE_TRIGGER (1 << 16)
129 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
130 #define DSI_IRQ_SYNC_LOST (1 << 18)
131 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
132 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
133 #define DSI_IRQ_ERROR_MASK \
134 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
135 DSI_IRQ_TA_TIMEOUT)
136 #define DSI_IRQ_CHANNEL_MASK 0xf
137
138 /* Virtual channel interrupts */
139 #define DSI_VC_IRQ_CS (1 << 0)
140 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
141 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
142 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
143 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
144 #define DSI_VC_IRQ_BTA (1 << 5)
145 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
146 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
147 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
148 #define DSI_VC_IRQ_ERROR_MASK \
149 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
150 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
151 DSI_VC_IRQ_FIFO_TX_UDF)
152
153 /* ComplexIO interrupts */
154 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
155 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
156 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
157 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
158 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
159 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
160 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
161 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
162 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
163 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
164 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
165 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
166 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
167 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
168 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
169 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
170 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
171 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
172 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
173 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
174 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
175 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
176 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
177 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
178 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
179 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
180 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
181 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
182 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
183 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
184 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
185 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
186 #define DSI_CIO_IRQ_ERROR_MASK \
187 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
188 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
189 DSI_CIO_IRQ_ERRSYNCESC5 | \
190 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
191 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
192 DSI_CIO_IRQ_ERRESC5 | \
193 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
194 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
195 DSI_CIO_IRQ_ERRCONTROL5 | \
196 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
197 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
198 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
199 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
200 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
201
202 #define DSI_DT_DCS_SHORT_WRITE_0 0x05
203 #define DSI_DT_DCS_SHORT_WRITE_1 0x15
204 #define DSI_DT_DCS_READ 0x06
205 #define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
206 #define DSI_DT_NULL_PACKET 0x09
207 #define DSI_DT_DCS_LONG_WRITE 0x39
208
209 #define DSI_DT_RX_ACK_WITH_ERR 0x02
210 #define DSI_DT_RX_DCS_LONG_READ 0x1c
211 #define DSI_DT_RX_SHORT_READ_1 0x21
212 #define DSI_DT_RX_SHORT_READ_2 0x22
213
214 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
215
216 #define DSI_MAX_NR_ISRS 2
217
218 struct dsi_isr_data {
219 omap_dsi_isr_t isr;
220 void *arg;
221 u32 mask;
222 };
223
224 enum fifo_size {
225 DSI_FIFO_SIZE_0 = 0,
226 DSI_FIFO_SIZE_32 = 1,
227 DSI_FIFO_SIZE_64 = 2,
228 DSI_FIFO_SIZE_96 = 3,
229 DSI_FIFO_SIZE_128 = 4,
230 };
231
232 enum dsi_vc_mode {
233 DSI_VC_MODE_L4 = 0,
234 DSI_VC_MODE_VP,
235 };
236
237 enum dsi_lane {
238 DSI_CLK_P = 1 << 0,
239 DSI_CLK_N = 1 << 1,
240 DSI_DATA1_P = 1 << 2,
241 DSI_DATA1_N = 1 << 3,
242 DSI_DATA2_P = 1 << 4,
243 DSI_DATA2_N = 1 << 5,
244 DSI_DATA3_P = 1 << 6,
245 DSI_DATA3_N = 1 << 7,
246 DSI_DATA4_P = 1 << 8,
247 DSI_DATA4_N = 1 << 9,
248 };
249
250 struct dsi_update_region {
251 u16 x, y, w, h;
252 struct omap_dss_device *device;
253 };
254
255 struct dsi_irq_stats {
256 unsigned long last_reset;
257 unsigned irq_count;
258 unsigned dsi_irqs[32];
259 unsigned vc_irqs[4][32];
260 unsigned cio_irqs[32];
261 };
262
263 struct dsi_isr_tables {
264 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
265 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
266 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
267 };
268
269 struct dsi_data {
270 struct platform_device *pdev;
271 void __iomem *base;
272
273 int irq;
274
275 struct clk *dss_clk;
276 struct clk *sys_clk;
277
278 void (*dsi_mux_pads)(bool enable);
279
280 struct dsi_clock_info current_cinfo;
281
282 bool vdds_dsi_enabled;
283 struct regulator *vdds_dsi_reg;
284
285 struct {
286 enum dsi_vc_mode mode;
287 struct omap_dss_device *dssdev;
288 enum fifo_size fifo_size;
289 int vc_id;
290 } vc[4];
291
292 struct mutex lock;
293 struct semaphore bus_lock;
294
295 unsigned pll_locked;
296
297 spinlock_t irq_lock;
298 struct dsi_isr_tables isr_tables;
299 /* space for a copy used by the interrupt handler */
300 struct dsi_isr_tables isr_tables_copy;
301
302 int update_channel;
303 struct dsi_update_region update_region;
304
305 bool te_enabled;
306 bool ulps_enabled;
307
308 void (*framedone_callback)(int, void *);
309 void *framedone_data;
310
311 struct delayed_work framedone_timeout_work;
312
313 #ifdef DSI_CATCH_MISSING_TE
314 struct timer_list te_timer;
315 #endif
316
317 unsigned long cache_req_pck;
318 unsigned long cache_clk_freq;
319 struct dsi_clock_info cache_cinfo;
320
321 u32 errors;
322 spinlock_t errors_lock;
323 #ifdef DEBUG
324 ktime_t perf_setup_time;
325 ktime_t perf_start_time;
326 #endif
327 int debug_read;
328 int debug_write;
329
330 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
331 spinlock_t irq_stats_lock;
332 struct dsi_irq_stats irq_stats;
333 #endif
334 /* DSI PLL Parameter Ranges */
335 unsigned long regm_max, regn_max;
336 unsigned long regm_dispc_max, regm_dsi_max;
337 unsigned long fint_min, fint_max;
338 unsigned long lpdiv_max;
339
340 int num_data_lanes;
341
342 unsigned scp_clk_refcount;
343 };
344
345 struct dsi_packet_sent_handler_data {
346 struct platform_device *dsidev;
347 struct completion *completion;
348 };
349
350 static struct platform_device *dsi_pdev_map[MAX_NUM_DSI];
351
352 #ifdef DEBUG
353 static unsigned int dsi_perf;
354 module_param_named(dsi_perf, dsi_perf, bool, 0644);
355 #endif
356
357 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
358 {
359 return dev_get_drvdata(&dsidev->dev);
360 }
361
362 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
363 {
364 return dsi_pdev_map[dssdev->phy.dsi.module];
365 }
366
367 struct platform_device *dsi_get_dsidev_from_id(int module)
368 {
369 return dsi_pdev_map[module];
370 }
371
372 static int dsi_get_dsidev_id(struct platform_device *dsidev)
373 {
374 /* TEMP: Pass 0 as the dsi module index till the time the dsi platform
375 * device names aren't changed to the form "omapdss_dsi.0",
376 * "omapdss_dsi.1" and so on */
377 BUG_ON(dsidev->id != -1);
378
379 return 0;
380 }
381
382 static inline void dsi_write_reg(struct platform_device *dsidev,
383 const struct dsi_reg idx, u32 val)
384 {
385 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
386
387 __raw_writel(val, dsi->base + idx.idx);
388 }
389
390 static inline u32 dsi_read_reg(struct platform_device *dsidev,
391 const struct dsi_reg idx)
392 {
393 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
394
395 return __raw_readl(dsi->base + idx.idx);
396 }
397
398 void dsi_bus_lock(struct omap_dss_device *dssdev)
399 {
400 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
401 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
402
403 down(&dsi->bus_lock);
404 }
405 EXPORT_SYMBOL(dsi_bus_lock);
406
407 void dsi_bus_unlock(struct omap_dss_device *dssdev)
408 {
409 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
410 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
411
412 up(&dsi->bus_lock);
413 }
414 EXPORT_SYMBOL(dsi_bus_unlock);
415
416 static bool dsi_bus_is_locked(struct platform_device *dsidev)
417 {
418 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
419
420 return dsi->bus_lock.count == 0;
421 }
422
423 static void dsi_completion_handler(void *data, u32 mask)
424 {
425 complete((struct completion *)data);
426 }
427
428 static inline int wait_for_bit_change(struct platform_device *dsidev,
429 const struct dsi_reg idx, int bitnum, int value)
430 {
431 int t = 100000;
432
433 while (REG_GET(dsidev, idx, bitnum, bitnum) != value) {
434 if (--t == 0)
435 return !value;
436 }
437
438 return value;
439 }
440
441 #ifdef DEBUG
442 static void dsi_perf_mark_setup(struct platform_device *dsidev)
443 {
444 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
445 dsi->perf_setup_time = ktime_get();
446 }
447
448 static void dsi_perf_mark_start(struct platform_device *dsidev)
449 {
450 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
451 dsi->perf_start_time = ktime_get();
452 }
453
454 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
455 {
456 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
457 ktime_t t, setup_time, trans_time;
458 u32 total_bytes;
459 u32 setup_us, trans_us, total_us;
460
461 if (!dsi_perf)
462 return;
463
464 t = ktime_get();
465
466 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
467 setup_us = (u32)ktime_to_us(setup_time);
468 if (setup_us == 0)
469 setup_us = 1;
470
471 trans_time = ktime_sub(t, dsi->perf_start_time);
472 trans_us = (u32)ktime_to_us(trans_time);
473 if (trans_us == 0)
474 trans_us = 1;
475
476 total_us = setup_us + trans_us;
477
478 total_bytes = dsi->update_region.w *
479 dsi->update_region.h *
480 dsi->update_region.device->ctrl.pixel_size / 8;
481
482 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
483 "%u bytes, %u kbytes/sec\n",
484 name,
485 setup_us,
486 trans_us,
487 total_us,
488 1000*1000 / total_us,
489 total_bytes,
490 total_bytes * 1000 / total_us);
491 }
492 #else
493 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
494 {
495 }
496
497 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
498 {
499 }
500
501 static inline void dsi_perf_show(struct platform_device *dsidev,
502 const char *name)
503 {
504 }
505 #endif
506
507 static void print_irq_status(u32 status)
508 {
509 if (status == 0)
510 return;
511
512 #ifndef VERBOSE_IRQ
513 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
514 return;
515 #endif
516 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
517
518 #define PIS(x) \
519 if (status & DSI_IRQ_##x) \
520 printk(#x " ");
521 #ifdef VERBOSE_IRQ
522 PIS(VC0);
523 PIS(VC1);
524 PIS(VC2);
525 PIS(VC3);
526 #endif
527 PIS(WAKEUP);
528 PIS(RESYNC);
529 PIS(PLL_LOCK);
530 PIS(PLL_UNLOCK);
531 PIS(PLL_RECALL);
532 PIS(COMPLEXIO_ERR);
533 PIS(HS_TX_TIMEOUT);
534 PIS(LP_RX_TIMEOUT);
535 PIS(TE_TRIGGER);
536 PIS(ACK_TRIGGER);
537 PIS(SYNC_LOST);
538 PIS(LDO_POWER_GOOD);
539 PIS(TA_TIMEOUT);
540 #undef PIS
541
542 printk("\n");
543 }
544
545 static void print_irq_status_vc(int channel, u32 status)
546 {
547 if (status == 0)
548 return;
549
550 #ifndef VERBOSE_IRQ
551 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
552 return;
553 #endif
554 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
555
556 #define PIS(x) \
557 if (status & DSI_VC_IRQ_##x) \
558 printk(#x " ");
559 PIS(CS);
560 PIS(ECC_CORR);
561 #ifdef VERBOSE_IRQ
562 PIS(PACKET_SENT);
563 #endif
564 PIS(FIFO_TX_OVF);
565 PIS(FIFO_RX_OVF);
566 PIS(BTA);
567 PIS(ECC_NO_CORR);
568 PIS(FIFO_TX_UDF);
569 PIS(PP_BUSY_CHANGE);
570 #undef PIS
571 printk("\n");
572 }
573
574 static void print_irq_status_cio(u32 status)
575 {
576 if (status == 0)
577 return;
578
579 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
580
581 #define PIS(x) \
582 if (status & DSI_CIO_IRQ_##x) \
583 printk(#x " ");
584 PIS(ERRSYNCESC1);
585 PIS(ERRSYNCESC2);
586 PIS(ERRSYNCESC3);
587 PIS(ERRESC1);
588 PIS(ERRESC2);
589 PIS(ERRESC3);
590 PIS(ERRCONTROL1);
591 PIS(ERRCONTROL2);
592 PIS(ERRCONTROL3);
593 PIS(STATEULPS1);
594 PIS(STATEULPS2);
595 PIS(STATEULPS3);
596 PIS(ERRCONTENTIONLP0_1);
597 PIS(ERRCONTENTIONLP1_1);
598 PIS(ERRCONTENTIONLP0_2);
599 PIS(ERRCONTENTIONLP1_2);
600 PIS(ERRCONTENTIONLP0_3);
601 PIS(ERRCONTENTIONLP1_3);
602 PIS(ULPSACTIVENOT_ALL0);
603 PIS(ULPSACTIVENOT_ALL1);
604 #undef PIS
605
606 printk("\n");
607 }
608
609 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
610 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
611 u32 *vcstatus, u32 ciostatus)
612 {
613 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
614 int i;
615
616 spin_lock(&dsi->irq_stats_lock);
617
618 dsi->irq_stats.irq_count++;
619 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
620
621 for (i = 0; i < 4; ++i)
622 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
623
624 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
625
626 spin_unlock(&dsi->irq_stats_lock);
627 }
628 #else
629 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
630 #endif
631
632 static int debug_irq;
633
634 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
635 u32 *vcstatus, u32 ciostatus)
636 {
637 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
638 int i;
639
640 if (irqstatus & DSI_IRQ_ERROR_MASK) {
641 DSSERR("DSI error, irqstatus %x\n", irqstatus);
642 print_irq_status(irqstatus);
643 spin_lock(&dsi->errors_lock);
644 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
645 spin_unlock(&dsi->errors_lock);
646 } else if (debug_irq) {
647 print_irq_status(irqstatus);
648 }
649
650 for (i = 0; i < 4; ++i) {
651 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
652 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
653 i, vcstatus[i]);
654 print_irq_status_vc(i, vcstatus[i]);
655 } else if (debug_irq) {
656 print_irq_status_vc(i, vcstatus[i]);
657 }
658 }
659
660 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
661 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
662 print_irq_status_cio(ciostatus);
663 } else if (debug_irq) {
664 print_irq_status_cio(ciostatus);
665 }
666 }
667
668 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
669 unsigned isr_array_size, u32 irqstatus)
670 {
671 struct dsi_isr_data *isr_data;
672 int i;
673
674 for (i = 0; i < isr_array_size; i++) {
675 isr_data = &isr_array[i];
676 if (isr_data->isr && isr_data->mask & irqstatus)
677 isr_data->isr(isr_data->arg, irqstatus);
678 }
679 }
680
681 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
682 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
683 {
684 int i;
685
686 dsi_call_isrs(isr_tables->isr_table,
687 ARRAY_SIZE(isr_tables->isr_table),
688 irqstatus);
689
690 for (i = 0; i < 4; ++i) {
691 if (vcstatus[i] == 0)
692 continue;
693 dsi_call_isrs(isr_tables->isr_table_vc[i],
694 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
695 vcstatus[i]);
696 }
697
698 if (ciostatus != 0)
699 dsi_call_isrs(isr_tables->isr_table_cio,
700 ARRAY_SIZE(isr_tables->isr_table_cio),
701 ciostatus);
702 }
703
704 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
705 {
706 struct platform_device *dsidev;
707 struct dsi_data *dsi;
708 u32 irqstatus, vcstatus[4], ciostatus;
709 int i;
710
711 dsidev = (struct platform_device *) arg;
712 dsi = dsi_get_dsidrv_data(dsidev);
713
714 spin_lock(&dsi->irq_lock);
715
716 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
717
718 /* IRQ is not for us */
719 if (!irqstatus) {
720 spin_unlock(&dsi->irq_lock);
721 return IRQ_NONE;
722 }
723
724 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
725 /* flush posted write */
726 dsi_read_reg(dsidev, DSI_IRQSTATUS);
727
728 for (i = 0; i < 4; ++i) {
729 if ((irqstatus & (1 << i)) == 0) {
730 vcstatus[i] = 0;
731 continue;
732 }
733
734 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
735
736 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
737 /* flush posted write */
738 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
739 }
740
741 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
742 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
743
744 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
745 /* flush posted write */
746 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
747 } else {
748 ciostatus = 0;
749 }
750
751 #ifdef DSI_CATCH_MISSING_TE
752 if (irqstatus & DSI_IRQ_TE_TRIGGER)
753 del_timer(&dsi->te_timer);
754 #endif
755
756 /* make a copy and unlock, so that isrs can unregister
757 * themselves */
758 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
759 sizeof(dsi->isr_tables));
760
761 spin_unlock(&dsi->irq_lock);
762
763 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
764
765 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
766
767 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
768
769 return IRQ_HANDLED;
770 }
771
772 /* dsi->irq_lock has to be locked by the caller */
773 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
774 struct dsi_isr_data *isr_array,
775 unsigned isr_array_size, u32 default_mask,
776 const struct dsi_reg enable_reg,
777 const struct dsi_reg status_reg)
778 {
779 struct dsi_isr_data *isr_data;
780 u32 mask;
781 u32 old_mask;
782 int i;
783
784 mask = default_mask;
785
786 for (i = 0; i < isr_array_size; i++) {
787 isr_data = &isr_array[i];
788
789 if (isr_data->isr == NULL)
790 continue;
791
792 mask |= isr_data->mask;
793 }
794
795 old_mask = dsi_read_reg(dsidev, enable_reg);
796 /* clear the irqstatus for newly enabled irqs */
797 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
798 dsi_write_reg(dsidev, enable_reg, mask);
799
800 /* flush posted writes */
801 dsi_read_reg(dsidev, enable_reg);
802 dsi_read_reg(dsidev, status_reg);
803 }
804
805 /* dsi->irq_lock has to be locked by the caller */
806 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
807 {
808 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
809 u32 mask = DSI_IRQ_ERROR_MASK;
810 #ifdef DSI_CATCH_MISSING_TE
811 mask |= DSI_IRQ_TE_TRIGGER;
812 #endif
813 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
814 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
815 DSI_IRQENABLE, DSI_IRQSTATUS);
816 }
817
818 /* dsi->irq_lock has to be locked by the caller */
819 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
820 {
821 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
822
823 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
824 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
825 DSI_VC_IRQ_ERROR_MASK,
826 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
827 }
828
829 /* dsi->irq_lock has to be locked by the caller */
830 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
831 {
832 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
833
834 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
835 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
836 DSI_CIO_IRQ_ERROR_MASK,
837 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
838 }
839
840 static void _dsi_initialize_irq(struct platform_device *dsidev)
841 {
842 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
843 unsigned long flags;
844 int vc;
845
846 spin_lock_irqsave(&dsi->irq_lock, flags);
847
848 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
849
850 _omap_dsi_set_irqs(dsidev);
851 for (vc = 0; vc < 4; ++vc)
852 _omap_dsi_set_irqs_vc(dsidev, vc);
853 _omap_dsi_set_irqs_cio(dsidev);
854
855 spin_unlock_irqrestore(&dsi->irq_lock, flags);
856 }
857
858 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
859 struct dsi_isr_data *isr_array, unsigned isr_array_size)
860 {
861 struct dsi_isr_data *isr_data;
862 int free_idx;
863 int i;
864
865 BUG_ON(isr == NULL);
866
867 /* check for duplicate entry and find a free slot */
868 free_idx = -1;
869 for (i = 0; i < isr_array_size; i++) {
870 isr_data = &isr_array[i];
871
872 if (isr_data->isr == isr && isr_data->arg == arg &&
873 isr_data->mask == mask) {
874 return -EINVAL;
875 }
876
877 if (isr_data->isr == NULL && free_idx == -1)
878 free_idx = i;
879 }
880
881 if (free_idx == -1)
882 return -EBUSY;
883
884 isr_data = &isr_array[free_idx];
885 isr_data->isr = isr;
886 isr_data->arg = arg;
887 isr_data->mask = mask;
888
889 return 0;
890 }
891
892 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
893 struct dsi_isr_data *isr_array, unsigned isr_array_size)
894 {
895 struct dsi_isr_data *isr_data;
896 int i;
897
898 for (i = 0; i < isr_array_size; i++) {
899 isr_data = &isr_array[i];
900 if (isr_data->isr != isr || isr_data->arg != arg ||
901 isr_data->mask != mask)
902 continue;
903
904 isr_data->isr = NULL;
905 isr_data->arg = NULL;
906 isr_data->mask = 0;
907
908 return 0;
909 }
910
911 return -EINVAL;
912 }
913
914 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
915 void *arg, u32 mask)
916 {
917 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
918 unsigned long flags;
919 int r;
920
921 spin_lock_irqsave(&dsi->irq_lock, flags);
922
923 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
924 ARRAY_SIZE(dsi->isr_tables.isr_table));
925
926 if (r == 0)
927 _omap_dsi_set_irqs(dsidev);
928
929 spin_unlock_irqrestore(&dsi->irq_lock, flags);
930
931 return r;
932 }
933
934 static int dsi_unregister_isr(struct platform_device *dsidev,
935 omap_dsi_isr_t isr, void *arg, u32 mask)
936 {
937 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
938 unsigned long flags;
939 int r;
940
941 spin_lock_irqsave(&dsi->irq_lock, flags);
942
943 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
944 ARRAY_SIZE(dsi->isr_tables.isr_table));
945
946 if (r == 0)
947 _omap_dsi_set_irqs(dsidev);
948
949 spin_unlock_irqrestore(&dsi->irq_lock, flags);
950
951 return r;
952 }
953
954 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
955 omap_dsi_isr_t isr, void *arg, u32 mask)
956 {
957 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
958 unsigned long flags;
959 int r;
960
961 spin_lock_irqsave(&dsi->irq_lock, flags);
962
963 r = _dsi_register_isr(isr, arg, mask,
964 dsi->isr_tables.isr_table_vc[channel],
965 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
966
967 if (r == 0)
968 _omap_dsi_set_irqs_vc(dsidev, channel);
969
970 spin_unlock_irqrestore(&dsi->irq_lock, flags);
971
972 return r;
973 }
974
975 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
976 omap_dsi_isr_t isr, void *arg, u32 mask)
977 {
978 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
979 unsigned long flags;
980 int r;
981
982 spin_lock_irqsave(&dsi->irq_lock, flags);
983
984 r = _dsi_unregister_isr(isr, arg, mask,
985 dsi->isr_tables.isr_table_vc[channel],
986 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
987
988 if (r == 0)
989 _omap_dsi_set_irqs_vc(dsidev, channel);
990
991 spin_unlock_irqrestore(&dsi->irq_lock, flags);
992
993 return r;
994 }
995
996 static int dsi_register_isr_cio(struct platform_device *dsidev,
997 omap_dsi_isr_t isr, void *arg, u32 mask)
998 {
999 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1000 unsigned long flags;
1001 int r;
1002
1003 spin_lock_irqsave(&dsi->irq_lock, flags);
1004
1005 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1006 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1007
1008 if (r == 0)
1009 _omap_dsi_set_irqs_cio(dsidev);
1010
1011 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1012
1013 return r;
1014 }
1015
1016 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1017 omap_dsi_isr_t isr, void *arg, u32 mask)
1018 {
1019 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1020 unsigned long flags;
1021 int r;
1022
1023 spin_lock_irqsave(&dsi->irq_lock, flags);
1024
1025 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1026 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1027
1028 if (r == 0)
1029 _omap_dsi_set_irqs_cio(dsidev);
1030
1031 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1032
1033 return r;
1034 }
1035
1036 static u32 dsi_get_errors(struct platform_device *dsidev)
1037 {
1038 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1039 unsigned long flags;
1040 u32 e;
1041 spin_lock_irqsave(&dsi->errors_lock, flags);
1042 e = dsi->errors;
1043 dsi->errors = 0;
1044 spin_unlock_irqrestore(&dsi->errors_lock, flags);
1045 return e;
1046 }
1047
1048 int dsi_runtime_get(struct platform_device *dsidev)
1049 {
1050 int r;
1051 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1052
1053 DSSDBG("dsi_runtime_get\n");
1054
1055 r = pm_runtime_get_sync(&dsi->pdev->dev);
1056 WARN_ON(r < 0);
1057 return r < 0 ? r : 0;
1058 }
1059
1060 void dsi_runtime_put(struct platform_device *dsidev)
1061 {
1062 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1063 int r;
1064
1065 DSSDBG("dsi_runtime_put\n");
1066
1067 r = pm_runtime_put(&dsi->pdev->dev);
1068 WARN_ON(r < 0);
1069 }
1070
1071 /* source clock for DSI PLL. this could also be PCLKFREE */
1072 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1073 bool enable)
1074 {
1075 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1076
1077 if (enable)
1078 clk_enable(dsi->sys_clk);
1079 else
1080 clk_disable(dsi->sys_clk);
1081
1082 if (enable && dsi->pll_locked) {
1083 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1084 DSSERR("cannot lock PLL when enabling clocks\n");
1085 }
1086 }
1087
1088 #ifdef DEBUG
1089 static void _dsi_print_reset_status(struct platform_device *dsidev)
1090 {
1091 u32 l;
1092 int b0, b1, b2;
1093
1094 if (!dss_debug)
1095 return;
1096
1097 /* A dummy read using the SCP interface to any DSIPHY register is
1098 * required after DSIPHY reset to complete the reset of the DSI complex
1099 * I/O. */
1100 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1101
1102 printk(KERN_DEBUG "DSI resets: ");
1103
1104 l = dsi_read_reg(dsidev, DSI_PLL_STATUS);
1105 printk("PLL (%d) ", FLD_GET(l, 0, 0));
1106
1107 l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1108 printk("CIO (%d) ", FLD_GET(l, 29, 29));
1109
1110 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1111 b0 = 28;
1112 b1 = 27;
1113 b2 = 26;
1114 } else {
1115 b0 = 24;
1116 b1 = 25;
1117 b2 = 26;
1118 }
1119
1120 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1121 printk("PHY (%x%x%x, %d, %d, %d)\n",
1122 FLD_GET(l, b0, b0),
1123 FLD_GET(l, b1, b1),
1124 FLD_GET(l, b2, b2),
1125 FLD_GET(l, 29, 29),
1126 FLD_GET(l, 30, 30),
1127 FLD_GET(l, 31, 31));
1128 }
1129 #else
1130 #define _dsi_print_reset_status(x)
1131 #endif
1132
1133 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1134 {
1135 DSSDBG("dsi_if_enable(%d)\n", enable);
1136
1137 enable = enable ? 1 : 0;
1138 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1139
1140 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1141 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1142 return -EIO;
1143 }
1144
1145 return 0;
1146 }
1147
1148 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1149 {
1150 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1151
1152 return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1153 }
1154
1155 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1156 {
1157 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1158
1159 return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1160 }
1161
1162 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1163 {
1164 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1165
1166 return dsi->current_cinfo.clkin4ddr / 16;
1167 }
1168
1169 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1170 {
1171 unsigned long r;
1172 int dsi_module = dsi_get_dsidev_id(dsidev);
1173 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1174
1175 if (dss_get_dsi_clk_source(dsi_module) == OMAP_DSS_CLK_SRC_FCK) {
1176 /* DSI FCLK source is DSS_CLK_FCK */
1177 r = clk_get_rate(dsi->dss_clk);
1178 } else {
1179 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1180 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1181 }
1182
1183 return r;
1184 }
1185
1186 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
1187 {
1188 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1189 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1190 unsigned long dsi_fclk;
1191 unsigned lp_clk_div;
1192 unsigned long lp_clk;
1193
1194 lp_clk_div = dssdev->clocks.dsi.lp_clk_div;
1195
1196 if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1197 return -EINVAL;
1198
1199 dsi_fclk = dsi_fclk_rate(dsidev);
1200
1201 lp_clk = dsi_fclk / 2 / lp_clk_div;
1202
1203 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1204 dsi->current_cinfo.lp_clk = lp_clk;
1205 dsi->current_cinfo.lp_clk_div = lp_clk_div;
1206
1207 /* LP_CLK_DIVISOR */
1208 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1209
1210 /* LP_RX_SYNCHRO_ENABLE */
1211 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1212
1213 return 0;
1214 }
1215
1216 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1217 {
1218 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1219
1220 if (dsi->scp_clk_refcount++ == 0)
1221 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1222 }
1223
1224 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1225 {
1226 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1227
1228 WARN_ON(dsi->scp_clk_refcount == 0);
1229 if (--dsi->scp_clk_refcount == 0)
1230 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1231 }
1232
1233 enum dsi_pll_power_state {
1234 DSI_PLL_POWER_OFF = 0x0,
1235 DSI_PLL_POWER_ON_HSCLK = 0x1,
1236 DSI_PLL_POWER_ON_ALL = 0x2,
1237 DSI_PLL_POWER_ON_DIV = 0x3,
1238 };
1239
1240 static int dsi_pll_power(struct platform_device *dsidev,
1241 enum dsi_pll_power_state state)
1242 {
1243 int t = 0;
1244
1245 /* DSI-PLL power command 0x3 is not working */
1246 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1247 state == DSI_PLL_POWER_ON_DIV)
1248 state = DSI_PLL_POWER_ON_ALL;
1249
1250 /* PLL_PWR_CMD */
1251 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1252
1253 /* PLL_PWR_STATUS */
1254 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1255 if (++t > 1000) {
1256 DSSERR("Failed to set DSI PLL power mode to %d\n",
1257 state);
1258 return -ENODEV;
1259 }
1260 udelay(1);
1261 }
1262
1263 return 0;
1264 }
1265
1266 /* calculate clock rates using dividers in cinfo */
1267 static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
1268 struct dsi_clock_info *cinfo)
1269 {
1270 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1271 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1272
1273 if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1274 return -EINVAL;
1275
1276 if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1277 return -EINVAL;
1278
1279 if (cinfo->regm_dispc > dsi->regm_dispc_max)
1280 return -EINVAL;
1281
1282 if (cinfo->regm_dsi > dsi->regm_dsi_max)
1283 return -EINVAL;
1284
1285 if (cinfo->use_sys_clk) {
1286 cinfo->clkin = clk_get_rate(dsi->sys_clk);
1287 /* XXX it is unclear if highfreq should be used
1288 * with DSS_SYS_CLK source also */
1289 cinfo->highfreq = 0;
1290 } else {
1291 cinfo->clkin = dispc_pclk_rate(dssdev->manager->id);
1292
1293 if (cinfo->clkin < 32000000)
1294 cinfo->highfreq = 0;
1295 else
1296 cinfo->highfreq = 1;
1297 }
1298
1299 cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
1300
1301 if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1302 return -EINVAL;
1303
1304 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1305
1306 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1307 return -EINVAL;
1308
1309 if (cinfo->regm_dispc > 0)
1310 cinfo->dsi_pll_hsdiv_dispc_clk =
1311 cinfo->clkin4ddr / cinfo->regm_dispc;
1312 else
1313 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1314
1315 if (cinfo->regm_dsi > 0)
1316 cinfo->dsi_pll_hsdiv_dsi_clk =
1317 cinfo->clkin4ddr / cinfo->regm_dsi;
1318 else
1319 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1320
1321 return 0;
1322 }
1323
1324 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
1325 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
1326 struct dispc_clock_info *dispc_cinfo)
1327 {
1328 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1329 struct dsi_clock_info cur, best;
1330 struct dispc_clock_info best_dispc;
1331 int min_fck_per_pck;
1332 int match = 0;
1333 unsigned long dss_sys_clk, max_dss_fck;
1334
1335 dss_sys_clk = clk_get_rate(dsi->sys_clk);
1336
1337 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1338
1339 if (req_pck == dsi->cache_req_pck &&
1340 dsi->cache_cinfo.clkin == dss_sys_clk) {
1341 DSSDBG("DSI clock info found from cache\n");
1342 *dsi_cinfo = dsi->cache_cinfo;
1343 dispc_find_clk_divs(is_tft, req_pck,
1344 dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo);
1345 return 0;
1346 }
1347
1348 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1349
1350 if (min_fck_per_pck &&
1351 req_pck * min_fck_per_pck > max_dss_fck) {
1352 DSSERR("Requested pixel clock not possible with the current "
1353 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1354 "the constraint off.\n");
1355 min_fck_per_pck = 0;
1356 }
1357
1358 DSSDBG("dsi_pll_calc\n");
1359
1360 retry:
1361 memset(&best, 0, sizeof(best));
1362 memset(&best_dispc, 0, sizeof(best_dispc));
1363
1364 memset(&cur, 0, sizeof(cur));
1365 cur.clkin = dss_sys_clk;
1366 cur.use_sys_clk = 1;
1367 cur.highfreq = 0;
1368
1369 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
1370 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
1371 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1372 for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1373 if (cur.highfreq == 0)
1374 cur.fint = cur.clkin / cur.regn;
1375 else
1376 cur.fint = cur.clkin / (2 * cur.regn);
1377
1378 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1379 continue;
1380
1381 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
1382 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1383 unsigned long a, b;
1384
1385 a = 2 * cur.regm * (cur.clkin/1000);
1386 b = cur.regn * (cur.highfreq + 1);
1387 cur.clkin4ddr = a / b * 1000;
1388
1389 if (cur.clkin4ddr > 1800 * 1000 * 1000)
1390 break;
1391
1392 /* dsi_pll_hsdiv_dispc_clk(MHz) =
1393 * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */
1394 for (cur.regm_dispc = 1; cur.regm_dispc <
1395 dsi->regm_dispc_max; ++cur.regm_dispc) {
1396 struct dispc_clock_info cur_dispc;
1397 cur.dsi_pll_hsdiv_dispc_clk =
1398 cur.clkin4ddr / cur.regm_dispc;
1399
1400 /* this will narrow down the search a bit,
1401 * but still give pixclocks below what was
1402 * requested */
1403 if (cur.dsi_pll_hsdiv_dispc_clk < req_pck)
1404 break;
1405
1406 if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
1407 continue;
1408
1409 if (min_fck_per_pck &&
1410 cur.dsi_pll_hsdiv_dispc_clk <
1411 req_pck * min_fck_per_pck)
1412 continue;
1413
1414 match = 1;
1415
1416 dispc_find_clk_divs(is_tft, req_pck,
1417 cur.dsi_pll_hsdiv_dispc_clk,
1418 &cur_dispc);
1419
1420 if (abs(cur_dispc.pck - req_pck) <
1421 abs(best_dispc.pck - req_pck)) {
1422 best = cur;
1423 best_dispc = cur_dispc;
1424
1425 if (cur_dispc.pck == req_pck)
1426 goto found;
1427 }
1428 }
1429 }
1430 }
1431 found:
1432 if (!match) {
1433 if (min_fck_per_pck) {
1434 DSSERR("Could not find suitable clock settings.\n"
1435 "Turning FCK/PCK constraint off and"
1436 "trying again.\n");
1437 min_fck_per_pck = 0;
1438 goto retry;
1439 }
1440
1441 DSSERR("Could not find suitable clock settings.\n");
1442
1443 return -EINVAL;
1444 }
1445
1446 /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1447 best.regm_dsi = 0;
1448 best.dsi_pll_hsdiv_dsi_clk = 0;
1449
1450 if (dsi_cinfo)
1451 *dsi_cinfo = best;
1452 if (dispc_cinfo)
1453 *dispc_cinfo = best_dispc;
1454
1455 dsi->cache_req_pck = req_pck;
1456 dsi->cache_clk_freq = 0;
1457 dsi->cache_cinfo = best;
1458
1459 return 0;
1460 }
1461
1462 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1463 struct dsi_clock_info *cinfo)
1464 {
1465 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1466 int r = 0;
1467 u32 l;
1468 int f = 0;
1469 u8 regn_start, regn_end, regm_start, regm_end;
1470 u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1471
1472 DSSDBGF();
1473
1474 dsi->current_cinfo.use_sys_clk = cinfo->use_sys_clk;
1475 dsi->current_cinfo.highfreq = cinfo->highfreq;
1476
1477 dsi->current_cinfo.fint = cinfo->fint;
1478 dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1479 dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1480 cinfo->dsi_pll_hsdiv_dispc_clk;
1481 dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1482 cinfo->dsi_pll_hsdiv_dsi_clk;
1483
1484 dsi->current_cinfo.regn = cinfo->regn;
1485 dsi->current_cinfo.regm = cinfo->regm;
1486 dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1487 dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1488
1489 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1490
1491 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1492 cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree",
1493 cinfo->clkin,
1494 cinfo->highfreq);
1495
1496 /* DSIPHY == CLKIN4DDR */
1497 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1498 cinfo->regm,
1499 cinfo->regn,
1500 cinfo->clkin,
1501 cinfo->highfreq + 1,
1502 cinfo->clkin4ddr);
1503
1504 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1505 cinfo->clkin4ddr / 1000 / 1000 / 2);
1506
1507 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1508
1509 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1510 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1511 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1512 cinfo->dsi_pll_hsdiv_dispc_clk);
1513 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1514 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1515 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1516 cinfo->dsi_pll_hsdiv_dsi_clk);
1517
1518 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
1519 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, &regm_start, &regm_end);
1520 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, &regm_dispc_start,
1521 &regm_dispc_end);
1522 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, &regm_dsi_start,
1523 &regm_dsi_end);
1524
1525 /* DSI_PLL_AUTOMODE = manual */
1526 REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1527
1528 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1529 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1530 /* DSI_PLL_REGN */
1531 l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1532 /* DSI_PLL_REGM */
1533 l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1534 /* DSI_CLOCK_DIV */
1535 l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1536 regm_dispc_start, regm_dispc_end);
1537 /* DSIPROTO_CLOCK_DIV */
1538 l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1539 regm_dsi_start, regm_dsi_end);
1540 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1541
1542 BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1543
1544 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1545 f = cinfo->fint < 1000000 ? 0x3 :
1546 cinfo->fint < 1250000 ? 0x4 :
1547 cinfo->fint < 1500000 ? 0x5 :
1548 cinfo->fint < 1750000 ? 0x6 :
1549 0x7;
1550 }
1551
1552 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1553
1554 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL))
1555 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1556 l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1,
1557 11, 11); /* DSI_PLL_CLKSEL */
1558 l = FLD_MOD(l, cinfo->highfreq,
1559 12, 12); /* DSI_PLL_HIGHFREQ */
1560 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1561 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1562 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1563 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1564
1565 REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1566
1567 if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1568 DSSERR("dsi pll go bit not going down.\n");
1569 r = -EIO;
1570 goto err;
1571 }
1572
1573 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1574 DSSERR("cannot lock PLL\n");
1575 r = -EIO;
1576 goto err;
1577 }
1578
1579 dsi->pll_locked = 1;
1580
1581 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1582 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1583 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1584 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1585 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1586 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1587 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1588 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1589 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1590 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1591 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1592 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1593 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1594 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1595 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1596 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1597
1598 DSSDBG("PLL config done\n");
1599 err:
1600 return r;
1601 }
1602
1603 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1604 bool enable_hsdiv)
1605 {
1606 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1607 int r = 0;
1608 enum dsi_pll_power_state pwstate;
1609
1610 DSSDBG("PLL init\n");
1611
1612 if (dsi->vdds_dsi_reg == NULL) {
1613 struct regulator *vdds_dsi;
1614
1615 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
1616
1617 if (IS_ERR(vdds_dsi)) {
1618 DSSERR("can't get VDDS_DSI regulator\n");
1619 return PTR_ERR(vdds_dsi);
1620 }
1621
1622 dsi->vdds_dsi_reg = vdds_dsi;
1623 }
1624
1625 dsi_enable_pll_clock(dsidev, 1);
1626 /*
1627 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1628 */
1629 dsi_enable_scp_clk(dsidev);
1630
1631 if (!dsi->vdds_dsi_enabled) {
1632 r = regulator_enable(dsi->vdds_dsi_reg);
1633 if (r)
1634 goto err0;
1635 dsi->vdds_dsi_enabled = true;
1636 }
1637
1638 /* XXX PLL does not come out of reset without this... */
1639 dispc_pck_free_enable(1);
1640
1641 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1642 DSSERR("PLL not coming out of reset.\n");
1643 r = -ENODEV;
1644 dispc_pck_free_enable(0);
1645 goto err1;
1646 }
1647
1648 /* XXX ... but if left on, we get problems when planes do not
1649 * fill the whole display. No idea about this */
1650 dispc_pck_free_enable(0);
1651
1652 if (enable_hsclk && enable_hsdiv)
1653 pwstate = DSI_PLL_POWER_ON_ALL;
1654 else if (enable_hsclk)
1655 pwstate = DSI_PLL_POWER_ON_HSCLK;
1656 else if (enable_hsdiv)
1657 pwstate = DSI_PLL_POWER_ON_DIV;
1658 else
1659 pwstate = DSI_PLL_POWER_OFF;
1660
1661 r = dsi_pll_power(dsidev, pwstate);
1662
1663 if (r)
1664 goto err1;
1665
1666 DSSDBG("PLL init done\n");
1667
1668 return 0;
1669 err1:
1670 if (dsi->vdds_dsi_enabled) {
1671 regulator_disable(dsi->vdds_dsi_reg);
1672 dsi->vdds_dsi_enabled = false;
1673 }
1674 err0:
1675 dsi_disable_scp_clk(dsidev);
1676 dsi_enable_pll_clock(dsidev, 0);
1677 return r;
1678 }
1679
1680 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1681 {
1682 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1683
1684 dsi->pll_locked = 0;
1685 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1686 if (disconnect_lanes) {
1687 WARN_ON(!dsi->vdds_dsi_enabled);
1688 regulator_disable(dsi->vdds_dsi_reg);
1689 dsi->vdds_dsi_enabled = false;
1690 }
1691
1692 dsi_disable_scp_clk(dsidev);
1693 dsi_enable_pll_clock(dsidev, 0);
1694
1695 DSSDBG("PLL uninit done\n");
1696 }
1697
1698 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1699 struct seq_file *s)
1700 {
1701 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1702 struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1703 enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1704 int dsi_module = dsi_get_dsidev_id(dsidev);
1705
1706 dispc_clk_src = dss_get_dispc_clk_source();
1707 dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1708
1709 if (dsi_runtime_get(dsidev))
1710 return;
1711
1712 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
1713
1714 seq_printf(s, "dsi pll source = %s\n",
1715 cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree");
1716
1717 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1718
1719 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1720 cinfo->clkin4ddr, cinfo->regm);
1721
1722 seq_printf(s, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n",
1723 dss_get_generic_clk_source_name(dispc_clk_src),
1724 dss_feat_get_clk_source_name(dispc_clk_src),
1725 cinfo->dsi_pll_hsdiv_dispc_clk,
1726 cinfo->regm_dispc,
1727 dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1728 "off" : "on");
1729
1730 seq_printf(s, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n",
1731 dss_get_generic_clk_source_name(dsi_clk_src),
1732 dss_feat_get_clk_source_name(dsi_clk_src),
1733 cinfo->dsi_pll_hsdiv_dsi_clk,
1734 cinfo->regm_dsi,
1735 dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1736 "off" : "on");
1737
1738 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1739
1740 seq_printf(s, "dsi fclk source = %s (%s)\n",
1741 dss_get_generic_clk_source_name(dsi_clk_src),
1742 dss_feat_get_clk_source_name(dsi_clk_src));
1743
1744 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1745
1746 seq_printf(s, "DDR_CLK\t\t%lu\n",
1747 cinfo->clkin4ddr / 4);
1748
1749 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1750
1751 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1752
1753 dsi_runtime_put(dsidev);
1754 }
1755
1756 void dsi_dump_clocks(struct seq_file *s)
1757 {
1758 struct platform_device *dsidev;
1759 int i;
1760
1761 for (i = 0; i < MAX_NUM_DSI; i++) {
1762 dsidev = dsi_get_dsidev_from_id(i);
1763 if (dsidev)
1764 dsi_dump_dsidev_clocks(dsidev, s);
1765 }
1766 }
1767
1768 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1769 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1770 struct seq_file *s)
1771 {
1772 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1773 unsigned long flags;
1774 struct dsi_irq_stats stats;
1775 int dsi_module = dsi_get_dsidev_id(dsidev);
1776
1777 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1778
1779 stats = dsi->irq_stats;
1780 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1781 dsi->irq_stats.last_reset = jiffies;
1782
1783 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1784
1785 seq_printf(s, "period %u ms\n",
1786 jiffies_to_msecs(jiffies - stats.last_reset));
1787
1788 seq_printf(s, "irqs %d\n", stats.irq_count);
1789 #define PIS(x) \
1790 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1791
1792 seq_printf(s, "-- DSI%d interrupts --\n", dsi_module + 1);
1793 PIS(VC0);
1794 PIS(VC1);
1795 PIS(VC2);
1796 PIS(VC3);
1797 PIS(WAKEUP);
1798 PIS(RESYNC);
1799 PIS(PLL_LOCK);
1800 PIS(PLL_UNLOCK);
1801 PIS(PLL_RECALL);
1802 PIS(COMPLEXIO_ERR);
1803 PIS(HS_TX_TIMEOUT);
1804 PIS(LP_RX_TIMEOUT);
1805 PIS(TE_TRIGGER);
1806 PIS(ACK_TRIGGER);
1807 PIS(SYNC_LOST);
1808 PIS(LDO_POWER_GOOD);
1809 PIS(TA_TIMEOUT);
1810 #undef PIS
1811
1812 #define PIS(x) \
1813 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1814 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1815 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1816 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1817 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1818
1819 seq_printf(s, "-- VC interrupts --\n");
1820 PIS(CS);
1821 PIS(ECC_CORR);
1822 PIS(PACKET_SENT);
1823 PIS(FIFO_TX_OVF);
1824 PIS(FIFO_RX_OVF);
1825 PIS(BTA);
1826 PIS(ECC_NO_CORR);
1827 PIS(FIFO_TX_UDF);
1828 PIS(PP_BUSY_CHANGE);
1829 #undef PIS
1830
1831 #define PIS(x) \
1832 seq_printf(s, "%-20s %10d\n", #x, \
1833 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1834
1835 seq_printf(s, "-- CIO interrupts --\n");
1836 PIS(ERRSYNCESC1);
1837 PIS(ERRSYNCESC2);
1838 PIS(ERRSYNCESC3);
1839 PIS(ERRESC1);
1840 PIS(ERRESC2);
1841 PIS(ERRESC3);
1842 PIS(ERRCONTROL1);
1843 PIS(ERRCONTROL2);
1844 PIS(ERRCONTROL3);
1845 PIS(STATEULPS1);
1846 PIS(STATEULPS2);
1847 PIS(STATEULPS3);
1848 PIS(ERRCONTENTIONLP0_1);
1849 PIS(ERRCONTENTIONLP1_1);
1850 PIS(ERRCONTENTIONLP0_2);
1851 PIS(ERRCONTENTIONLP1_2);
1852 PIS(ERRCONTENTIONLP0_3);
1853 PIS(ERRCONTENTIONLP1_3);
1854 PIS(ULPSACTIVENOT_ALL0);
1855 PIS(ULPSACTIVENOT_ALL1);
1856 #undef PIS
1857 }
1858
1859 static void dsi1_dump_irqs(struct seq_file *s)
1860 {
1861 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1862
1863 dsi_dump_dsidev_irqs(dsidev, s);
1864 }
1865
1866 static void dsi2_dump_irqs(struct seq_file *s)
1867 {
1868 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1869
1870 dsi_dump_dsidev_irqs(dsidev, s);
1871 }
1872
1873 void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
1874 const struct file_operations *debug_fops)
1875 {
1876 struct platform_device *dsidev;
1877
1878 dsidev = dsi_get_dsidev_from_id(0);
1879 if (dsidev)
1880 debugfs_create_file("dsi1_irqs", S_IRUGO, debugfs_dir,
1881 &dsi1_dump_irqs, debug_fops);
1882
1883 dsidev = dsi_get_dsidev_from_id(1);
1884 if (dsidev)
1885 debugfs_create_file("dsi2_irqs", S_IRUGO, debugfs_dir,
1886 &dsi2_dump_irqs, debug_fops);
1887 }
1888 #endif
1889
1890 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1891 struct seq_file *s)
1892 {
1893 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1894
1895 if (dsi_runtime_get(dsidev))
1896 return;
1897 dsi_enable_scp_clk(dsidev);
1898
1899 DUMPREG(DSI_REVISION);
1900 DUMPREG(DSI_SYSCONFIG);
1901 DUMPREG(DSI_SYSSTATUS);
1902 DUMPREG(DSI_IRQSTATUS);
1903 DUMPREG(DSI_IRQENABLE);
1904 DUMPREG(DSI_CTRL);
1905 DUMPREG(DSI_COMPLEXIO_CFG1);
1906 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1907 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1908 DUMPREG(DSI_CLK_CTRL);
1909 DUMPREG(DSI_TIMING1);
1910 DUMPREG(DSI_TIMING2);
1911 DUMPREG(DSI_VM_TIMING1);
1912 DUMPREG(DSI_VM_TIMING2);
1913 DUMPREG(DSI_VM_TIMING3);
1914 DUMPREG(DSI_CLK_TIMING);
1915 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1916 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1917 DUMPREG(DSI_COMPLEXIO_CFG2);
1918 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1919 DUMPREG(DSI_VM_TIMING4);
1920 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1921 DUMPREG(DSI_VM_TIMING5);
1922 DUMPREG(DSI_VM_TIMING6);
1923 DUMPREG(DSI_VM_TIMING7);
1924 DUMPREG(DSI_STOPCLK_TIMING);
1925
1926 DUMPREG(DSI_VC_CTRL(0));
1927 DUMPREG(DSI_VC_TE(0));
1928 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1929 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1930 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1931 DUMPREG(DSI_VC_IRQSTATUS(0));
1932 DUMPREG(DSI_VC_IRQENABLE(0));
1933
1934 DUMPREG(DSI_VC_CTRL(1));
1935 DUMPREG(DSI_VC_TE(1));
1936 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1937 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1938 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1939 DUMPREG(DSI_VC_IRQSTATUS(1));
1940 DUMPREG(DSI_VC_IRQENABLE(1));
1941
1942 DUMPREG(DSI_VC_CTRL(2));
1943 DUMPREG(DSI_VC_TE(2));
1944 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1945 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1946 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1947 DUMPREG(DSI_VC_IRQSTATUS(2));
1948 DUMPREG(DSI_VC_IRQENABLE(2));
1949
1950 DUMPREG(DSI_VC_CTRL(3));
1951 DUMPREG(DSI_VC_TE(3));
1952 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1953 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1954 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1955 DUMPREG(DSI_VC_IRQSTATUS(3));
1956 DUMPREG(DSI_VC_IRQENABLE(3));
1957
1958 DUMPREG(DSI_DSIPHY_CFG0);
1959 DUMPREG(DSI_DSIPHY_CFG1);
1960 DUMPREG(DSI_DSIPHY_CFG2);
1961 DUMPREG(DSI_DSIPHY_CFG5);
1962
1963 DUMPREG(DSI_PLL_CONTROL);
1964 DUMPREG(DSI_PLL_STATUS);
1965 DUMPREG(DSI_PLL_GO);
1966 DUMPREG(DSI_PLL_CONFIGURATION1);
1967 DUMPREG(DSI_PLL_CONFIGURATION2);
1968
1969 dsi_disable_scp_clk(dsidev);
1970 dsi_runtime_put(dsidev);
1971 #undef DUMPREG
1972 }
1973
1974 static void dsi1_dump_regs(struct seq_file *s)
1975 {
1976 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1977
1978 dsi_dump_dsidev_regs(dsidev, s);
1979 }
1980
1981 static void dsi2_dump_regs(struct seq_file *s)
1982 {
1983 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1984
1985 dsi_dump_dsidev_regs(dsidev, s);
1986 }
1987
1988 void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
1989 const struct file_operations *debug_fops)
1990 {
1991 struct platform_device *dsidev;
1992
1993 dsidev = dsi_get_dsidev_from_id(0);
1994 if (dsidev)
1995 debugfs_create_file("dsi1_regs", S_IRUGO, debugfs_dir,
1996 &dsi1_dump_regs, debug_fops);
1997
1998 dsidev = dsi_get_dsidev_from_id(1);
1999 if (dsidev)
2000 debugfs_create_file("dsi2_regs", S_IRUGO, debugfs_dir,
2001 &dsi2_dump_regs, debug_fops);
2002 }
2003 enum dsi_cio_power_state {
2004 DSI_COMPLEXIO_POWER_OFF = 0x0,
2005 DSI_COMPLEXIO_POWER_ON = 0x1,
2006 DSI_COMPLEXIO_POWER_ULPS = 0x2,
2007 };
2008
2009 static int dsi_cio_power(struct platform_device *dsidev,
2010 enum dsi_cio_power_state state)
2011 {
2012 int t = 0;
2013
2014 /* PWR_CMD */
2015 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
2016
2017 /* PWR_STATUS */
2018 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
2019 26, 25) != state) {
2020 if (++t > 1000) {
2021 DSSERR("failed to set complexio power state to "
2022 "%d\n", state);
2023 return -ENODEV;
2024 }
2025 udelay(1);
2026 }
2027
2028 return 0;
2029 }
2030
2031 /* Number of data lanes present on DSI interface */
2032 static inline int dsi_get_num_data_lanes(struct platform_device *dsidev)
2033 {
2034 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
2035 * of data lanes as 2 by default */
2036 if (dss_has_feature(FEAT_DSI_GNQ))
2037 return REG_GET(dsidev, DSI_GNQ, 11, 9); /* NB_DATA_LANES */
2038 else
2039 return 2;
2040 }
2041
2042 /* Number of data lanes used by the dss device */
2043 static inline int dsi_get_num_data_lanes_dssdev(struct omap_dss_device *dssdev)
2044 {
2045 int num_data_lanes = 0;
2046
2047 if (dssdev->phy.dsi.data1_lane != 0)
2048 num_data_lanes++;
2049 if (dssdev->phy.dsi.data2_lane != 0)
2050 num_data_lanes++;
2051 if (dssdev->phy.dsi.data3_lane != 0)
2052 num_data_lanes++;
2053 if (dssdev->phy.dsi.data4_lane != 0)
2054 num_data_lanes++;
2055
2056 return num_data_lanes;
2057 }
2058
2059 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
2060 {
2061 int val;
2062
2063 /* line buffer on OMAP3 is 1024 x 24bits */
2064 /* XXX: for some reason using full buffer size causes
2065 * considerable TX slowdown with update sizes that fill the
2066 * whole buffer */
2067 if (!dss_has_feature(FEAT_DSI_GNQ))
2068 return 1023 * 3;
2069
2070 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2071
2072 switch (val) {
2073 case 1:
2074 return 512 * 3; /* 512x24 bits */
2075 case 2:
2076 return 682 * 3; /* 682x24 bits */
2077 case 3:
2078 return 853 * 3; /* 853x24 bits */
2079 case 4:
2080 return 1024 * 3; /* 1024x24 bits */
2081 case 5:
2082 return 1194 * 3; /* 1194x24 bits */
2083 case 6:
2084 return 1365 * 3; /* 1365x24 bits */
2085 default:
2086 BUG();
2087 }
2088 }
2089
2090 static void dsi_set_lane_config(struct omap_dss_device *dssdev)
2091 {
2092 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2093 u32 r;
2094 int num_data_lanes_dssdev = dsi_get_num_data_lanes_dssdev(dssdev);
2095
2096 int clk_lane = dssdev->phy.dsi.clk_lane;
2097 int data1_lane = dssdev->phy.dsi.data1_lane;
2098 int data2_lane = dssdev->phy.dsi.data2_lane;
2099 int clk_pol = dssdev->phy.dsi.clk_pol;
2100 int data1_pol = dssdev->phy.dsi.data1_pol;
2101 int data2_pol = dssdev->phy.dsi.data2_pol;
2102
2103 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2104 r = FLD_MOD(r, clk_lane, 2, 0);
2105 r = FLD_MOD(r, clk_pol, 3, 3);
2106 r = FLD_MOD(r, data1_lane, 6, 4);
2107 r = FLD_MOD(r, data1_pol, 7, 7);
2108 r = FLD_MOD(r, data2_lane, 10, 8);
2109 r = FLD_MOD(r, data2_pol, 11, 11);
2110 if (num_data_lanes_dssdev > 2) {
2111 int data3_lane = dssdev->phy.dsi.data3_lane;
2112 int data3_pol = dssdev->phy.dsi.data3_pol;
2113
2114 r = FLD_MOD(r, data3_lane, 14, 12);
2115 r = FLD_MOD(r, data3_pol, 15, 15);
2116 }
2117 if (num_data_lanes_dssdev > 3) {
2118 int data4_lane = dssdev->phy.dsi.data4_lane;
2119 int data4_pol = dssdev->phy.dsi.data4_pol;
2120
2121 r = FLD_MOD(r, data4_lane, 18, 16);
2122 r = FLD_MOD(r, data4_pol, 19, 19);
2123 }
2124 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2125
2126 /* The configuration of the DSI complex I/O (number of data lanes,
2127 position, differential order) should not be changed while
2128 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
2129 the hardware to take into account a new configuration of the complex
2130 I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
2131 follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
2132 then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
2133 DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
2134 DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
2135 DSI complex I/O configuration is unknown. */
2136
2137 /*
2138 REG_FLD_MOD(dsidev, DSI_CTRL, 1, 0, 0);
2139 REG_FLD_MOD(dsidev, DSI_CTRL, 0, 0, 0);
2140 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20);
2141 REG_FLD_MOD(dsidev, DSI_CTRL, 1, 0, 0);
2142 */
2143 }
2144
2145 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2146 {
2147 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2148
2149 /* convert time in ns to ddr ticks, rounding up */
2150 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2151 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2152 }
2153
2154 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2155 {
2156 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2157
2158 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2159 return ddr * 1000 * 1000 / (ddr_clk / 1000);
2160 }
2161
2162 static void dsi_cio_timings(struct platform_device *dsidev)
2163 {
2164 u32 r;
2165 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2166 u32 tlpx_half, tclk_trail, tclk_zero;
2167 u32 tclk_prepare;
2168
2169 /* calculate timings */
2170
2171 /* 1 * DDR_CLK = 2 * UI */
2172
2173 /* min 40ns + 4*UI max 85ns + 6*UI */
2174 ths_prepare = ns2ddr(dsidev, 70) + 2;
2175
2176 /* min 145ns + 10*UI */
2177 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2178
2179 /* min max(8*UI, 60ns+4*UI) */
2180 ths_trail = ns2ddr(dsidev, 60) + 5;
2181
2182 /* min 100ns */
2183 ths_exit = ns2ddr(dsidev, 145);
2184
2185 /* tlpx min 50n */
2186 tlpx_half = ns2ddr(dsidev, 25);
2187
2188 /* min 60ns */
2189 tclk_trail = ns2ddr(dsidev, 60) + 2;
2190
2191 /* min 38ns, max 95ns */
2192 tclk_prepare = ns2ddr(dsidev, 65);
2193
2194 /* min tclk-prepare + tclk-zero = 300ns */
2195 tclk_zero = ns2ddr(dsidev, 260);
2196
2197 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2198 ths_prepare, ddr2ns(dsidev, ths_prepare),
2199 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2200 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2201 ths_trail, ddr2ns(dsidev, ths_trail),
2202 ths_exit, ddr2ns(dsidev, ths_exit));
2203
2204 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2205 "tclk_zero %u (%uns)\n",
2206 tlpx_half, ddr2ns(dsidev, tlpx_half),
2207 tclk_trail, ddr2ns(dsidev, tclk_trail),
2208 tclk_zero, ddr2ns(dsidev, tclk_zero));
2209 DSSDBG("tclk_prepare %u (%uns)\n",
2210 tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2211
2212 /* program timings */
2213
2214 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2215 r = FLD_MOD(r, ths_prepare, 31, 24);
2216 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2217 r = FLD_MOD(r, ths_trail, 15, 8);
2218 r = FLD_MOD(r, ths_exit, 7, 0);
2219 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2220
2221 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2222 r = FLD_MOD(r, tlpx_half, 22, 16);
2223 r = FLD_MOD(r, tclk_trail, 15, 8);
2224 r = FLD_MOD(r, tclk_zero, 7, 0);
2225 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2226
2227 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2228 r = FLD_MOD(r, tclk_prepare, 7, 0);
2229 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2230 }
2231
2232 static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev,
2233 enum dsi_lane lanes)
2234 {
2235 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2236 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2237 int clk_lane = dssdev->phy.dsi.clk_lane;
2238 int data1_lane = dssdev->phy.dsi.data1_lane;
2239 int data2_lane = dssdev->phy.dsi.data2_lane;
2240 int data3_lane = dssdev->phy.dsi.data3_lane;
2241 int data4_lane = dssdev->phy.dsi.data4_lane;
2242 int clk_pol = dssdev->phy.dsi.clk_pol;
2243 int data1_pol = dssdev->phy.dsi.data1_pol;
2244 int data2_pol = dssdev->phy.dsi.data2_pol;
2245 int data3_pol = dssdev->phy.dsi.data3_pol;
2246 int data4_pol = dssdev->phy.dsi.data4_pol;
2247
2248 u32 l = 0;
2249 u8 lptxscp_start = dsi->num_data_lanes == 2 ? 22 : 26;
2250
2251 if (lanes & DSI_CLK_P)
2252 l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 0 : 1));
2253 if (lanes & DSI_CLK_N)
2254 l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 1 : 0));
2255
2256 if (lanes & DSI_DATA1_P)
2257 l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 0 : 1));
2258 if (lanes & DSI_DATA1_N)
2259 l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 1 : 0));
2260
2261 if (lanes & DSI_DATA2_P)
2262 l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 0 : 1));
2263 if (lanes & DSI_DATA2_N)
2264 l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 1 : 0));
2265
2266 if (lanes & DSI_DATA3_P)
2267 l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 0 : 1));
2268 if (lanes & DSI_DATA3_N)
2269 l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 1 : 0));
2270
2271 if (lanes & DSI_DATA4_P)
2272 l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 0 : 1));
2273 if (lanes & DSI_DATA4_N)
2274 l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 1 : 0));
2275 /*
2276 * Bits in REGLPTXSCPDAT4TO0DXDY:
2277 * 17: DY0 18: DX0
2278 * 19: DY1 20: DX1
2279 * 21: DY2 22: DX2
2280 * 23: DY3 24: DX3
2281 * 25: DY4 26: DX4
2282 */
2283
2284 /* Set the lane override configuration */
2285
2286 /* REGLPTXSCPDAT4TO0DXDY */
2287 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2288
2289 /* Enable lane override */
2290
2291 /* ENLPTXSCPDAT */
2292 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2293 }
2294
2295 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2296 {
2297 /* Disable lane override */
2298 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2299 /* Reset the lane override configuration */
2300 /* REGLPTXSCPDAT4TO0DXDY */
2301 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2302 }
2303
2304 static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev)
2305 {
2306 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2307 int t;
2308 int bits[3];
2309 bool in_use[3];
2310
2311 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
2312 bits[0] = 28;
2313 bits[1] = 27;
2314 bits[2] = 26;
2315 } else {
2316 bits[0] = 24;
2317 bits[1] = 25;
2318 bits[2] = 26;
2319 }
2320
2321 in_use[0] = false;
2322 in_use[1] = false;
2323 in_use[2] = false;
2324
2325 if (dssdev->phy.dsi.clk_lane != 0)
2326 in_use[dssdev->phy.dsi.clk_lane - 1] = true;
2327 if (dssdev->phy.dsi.data1_lane != 0)
2328 in_use[dssdev->phy.dsi.data1_lane - 1] = true;
2329 if (dssdev->phy.dsi.data2_lane != 0)
2330 in_use[dssdev->phy.dsi.data2_lane - 1] = true;
2331
2332 t = 100000;
2333 while (true) {
2334 u32 l;
2335 int i;
2336 int ok;
2337
2338 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2339
2340 ok = 0;
2341 for (i = 0; i < 3; ++i) {
2342 if (!in_use[i] || (l & (1 << bits[i])))
2343 ok++;
2344 }
2345
2346 if (ok == 3)
2347 break;
2348
2349 if (--t == 0) {
2350 for (i = 0; i < 3; ++i) {
2351 if (!in_use[i] || (l & (1 << bits[i])))
2352 continue;
2353
2354 DSSERR("CIO TXCLKESC%d domain not coming " \
2355 "out of reset\n", i);
2356 }
2357 return -EIO;
2358 }
2359 }
2360
2361 return 0;
2362 }
2363
2364 static int dsi_cio_init(struct omap_dss_device *dssdev)
2365 {
2366 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2367 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2368 int r;
2369 int num_data_lanes_dssdev = dsi_get_num_data_lanes_dssdev(dssdev);
2370 u32 l;
2371
2372 DSSDBGF();
2373
2374 if (dsi->dsi_mux_pads)
2375 dsi->dsi_mux_pads(true);
2376
2377 dsi_enable_scp_clk(dsidev);
2378
2379 /* A dummy read using the SCP interface to any DSIPHY register is
2380 * required after DSIPHY reset to complete the reset of the DSI complex
2381 * I/O. */
2382 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2383
2384 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2385 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2386 r = -EIO;
2387 goto err_scp_clk_dom;
2388 }
2389
2390 dsi_set_lane_config(dssdev);
2391
2392 /* set TX STOP MODE timer to maximum for this operation */
2393 l = dsi_read_reg(dsidev, DSI_TIMING1);
2394 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2395 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2396 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2397 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2398 dsi_write_reg(dsidev, DSI_TIMING1, l);
2399
2400 if (dsi->ulps_enabled) {
2401 u32 lane_mask = DSI_CLK_P | DSI_DATA1_P | DSI_DATA2_P;
2402
2403 DSSDBG("manual ulps exit\n");
2404
2405 /* ULPS is exited by Mark-1 state for 1ms, followed by
2406 * stop state. DSS HW cannot do this via the normal
2407 * ULPS exit sequence, as after reset the DSS HW thinks
2408 * that we are not in ULPS mode, and refuses to send the
2409 * sequence. So we need to send the ULPS exit sequence
2410 * manually.
2411 */
2412
2413 if (num_data_lanes_dssdev > 2)
2414 lane_mask |= DSI_DATA3_P;
2415
2416 if (num_data_lanes_dssdev > 3)
2417 lane_mask |= DSI_DATA4_P;
2418
2419 dsi_cio_enable_lane_override(dssdev, lane_mask);
2420 }
2421
2422 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2423 if (r)
2424 goto err_cio_pwr;
2425
2426 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2427 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2428 r = -ENODEV;
2429 goto err_cio_pwr_dom;
2430 }
2431
2432 dsi_if_enable(dsidev, true);
2433 dsi_if_enable(dsidev, false);
2434 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2435
2436 r = dsi_cio_wait_tx_clk_esc_reset(dssdev);
2437 if (r)
2438 goto err_tx_clk_esc_rst;
2439
2440 if (dsi->ulps_enabled) {
2441 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2442 ktime_t wait = ns_to_ktime(1000 * 1000);
2443 set_current_state(TASK_UNINTERRUPTIBLE);
2444 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2445
2446 /* Disable the override. The lanes should be set to Mark-11
2447 * state by the HW */
2448 dsi_cio_disable_lane_override(dsidev);
2449 }
2450
2451 /* FORCE_TX_STOP_MODE_IO */
2452 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2453
2454 dsi_cio_timings(dsidev);
2455
2456 dsi->ulps_enabled = false;
2457
2458 DSSDBG("CIO init done\n");
2459
2460 return 0;
2461
2462 err_tx_clk_esc_rst:
2463 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2464 err_cio_pwr_dom:
2465 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2466 err_cio_pwr:
2467 if (dsi->ulps_enabled)
2468 dsi_cio_disable_lane_override(dsidev);
2469 err_scp_clk_dom:
2470 dsi_disable_scp_clk(dsidev);
2471 if (dsi->dsi_mux_pads)
2472 dsi->dsi_mux_pads(false);
2473 return r;
2474 }
2475
2476 static void dsi_cio_uninit(struct platform_device *dsidev)
2477 {
2478 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2479
2480 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2481 dsi_disable_scp_clk(dsidev);
2482 if (dsi->dsi_mux_pads)
2483 dsi->dsi_mux_pads(false);
2484 }
2485
2486 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2487 enum fifo_size size1, enum fifo_size size2,
2488 enum fifo_size size3, enum fifo_size size4)
2489 {
2490 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2491 u32 r = 0;
2492 int add = 0;
2493 int i;
2494
2495 dsi->vc[0].fifo_size = size1;
2496 dsi->vc[1].fifo_size = size2;
2497 dsi->vc[2].fifo_size = size3;
2498 dsi->vc[3].fifo_size = size4;
2499
2500 for (i = 0; i < 4; i++) {
2501 u8 v;
2502 int size = dsi->vc[i].fifo_size;
2503
2504 if (add + size > 4) {
2505 DSSERR("Illegal FIFO configuration\n");
2506 BUG();
2507 }
2508
2509 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2510 r |= v << (8 * i);
2511 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2512 add += size;
2513 }
2514
2515 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2516 }
2517
2518 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2519 enum fifo_size size1, enum fifo_size size2,
2520 enum fifo_size size3, enum fifo_size size4)
2521 {
2522 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2523 u32 r = 0;
2524 int add = 0;
2525 int i;
2526
2527 dsi->vc[0].fifo_size = size1;
2528 dsi->vc[1].fifo_size = size2;
2529 dsi->vc[2].fifo_size = size3;
2530 dsi->vc[3].fifo_size = size4;
2531
2532 for (i = 0; i < 4; i++) {
2533 u8 v;
2534 int size = dsi->vc[i].fifo_size;
2535
2536 if (add + size > 4) {
2537 DSSERR("Illegal FIFO configuration\n");
2538 BUG();
2539 }
2540
2541 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2542 r |= v << (8 * i);
2543 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2544 add += size;
2545 }
2546
2547 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2548 }
2549
2550 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2551 {
2552 u32 r;
2553
2554 r = dsi_read_reg(dsidev, DSI_TIMING1);
2555 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2556 dsi_write_reg(dsidev, DSI_TIMING1, r);
2557
2558 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2559 DSSERR("TX_STOP bit not going down\n");
2560 return -EIO;
2561 }
2562
2563 return 0;
2564 }
2565
2566 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2567 {
2568 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2569 }
2570
2571 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2572 {
2573 struct dsi_packet_sent_handler_data *vp_data =
2574 (struct dsi_packet_sent_handler_data *) data;
2575 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2576 const int channel = dsi->update_channel;
2577 u8 bit = dsi->te_enabled ? 30 : 31;
2578
2579 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2580 complete(vp_data->completion);
2581 }
2582
2583 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2584 {
2585 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2586 DECLARE_COMPLETION_ONSTACK(completion);
2587 struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2588 int r = 0;
2589 u8 bit;
2590
2591 bit = dsi->te_enabled ? 30 : 31;
2592
2593 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2594 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2595 if (r)
2596 goto err0;
2597
2598 /* Wait for completion only if TE_EN/TE_START is still set */
2599 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2600 if (wait_for_completion_timeout(&completion,
2601 msecs_to_jiffies(10)) == 0) {
2602 DSSERR("Failed to complete previous frame transfer\n");
2603 r = -EIO;
2604 goto err1;
2605 }
2606 }
2607
2608 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2609 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2610
2611 return 0;
2612 err1:
2613 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2614 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2615 err0:
2616 return r;
2617 }
2618
2619 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2620 {
2621 struct dsi_packet_sent_handler_data *l4_data =
2622 (struct dsi_packet_sent_handler_data *) data;
2623 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2624 const int channel = dsi->update_channel;
2625
2626 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2627 complete(l4_data->completion);
2628 }
2629
2630 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2631 {
2632 DECLARE_COMPLETION_ONSTACK(completion);
2633 struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2634 int r = 0;
2635
2636 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2637 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2638 if (r)
2639 goto err0;
2640
2641 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2642 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2643 if (wait_for_completion_timeout(&completion,
2644 msecs_to_jiffies(10)) == 0) {
2645 DSSERR("Failed to complete previous l4 transfer\n");
2646 r = -EIO;
2647 goto err1;
2648 }
2649 }
2650
2651 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2652 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2653
2654 return 0;
2655 err1:
2656 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2657 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2658 err0:
2659 return r;
2660 }
2661
2662 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2663 {
2664 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2665
2666 WARN_ON(!dsi_bus_is_locked(dsidev));
2667
2668 WARN_ON(in_interrupt());
2669
2670 if (!dsi_vc_is_enabled(dsidev, channel))
2671 return 0;
2672
2673 switch (dsi->vc[channel].mode) {
2674 case DSI_VC_MODE_VP:
2675 return dsi_sync_vc_vp(dsidev, channel);
2676 case DSI_VC_MODE_L4:
2677 return dsi_sync_vc_l4(dsidev, channel);
2678 default:
2679 BUG();
2680 }
2681 }
2682
2683 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2684 bool enable)
2685 {
2686 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2687 channel, enable);
2688
2689 enable = enable ? 1 : 0;
2690
2691 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2692
2693 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2694 0, enable) != enable) {
2695 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2696 return -EIO;
2697 }
2698
2699 return 0;
2700 }
2701
2702 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2703 {
2704 u32 r;
2705
2706 DSSDBGF("%d", channel);
2707
2708 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2709
2710 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2711 DSSERR("VC(%d) busy when trying to configure it!\n",
2712 channel);
2713
2714 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2715 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2716 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2717 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2718 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2719 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2720 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2721 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2722 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2723
2724 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2725 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2726
2727 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2728 }
2729
2730 static int dsi_vc_config_l4(struct platform_device *dsidev, int channel)
2731 {
2732 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2733
2734 if (dsi->vc[channel].mode == DSI_VC_MODE_L4)
2735 return 0;
2736
2737 DSSDBGF("%d", channel);
2738
2739 dsi_sync_vc(dsidev, channel);
2740
2741 dsi_vc_enable(dsidev, channel, 0);
2742
2743 /* VC_BUSY */
2744 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2745 DSSERR("vc(%d) busy when trying to config for L4\n", channel);
2746 return -EIO;
2747 }
2748
2749 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
2750
2751 /* DCS_CMD_ENABLE */
2752 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC))
2753 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 30, 30);
2754
2755 dsi_vc_enable(dsidev, channel, 1);
2756
2757 dsi->vc[channel].mode = DSI_VC_MODE_L4;
2758
2759 return 0;
2760 }
2761
2762 static int dsi_vc_config_vp(struct platform_device *dsidev, int channel)
2763 {
2764 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2765
2766 if (dsi->vc[channel].mode == DSI_VC_MODE_VP)
2767 return 0;
2768
2769 DSSDBGF("%d", channel);
2770
2771 dsi_sync_vc(dsidev, channel);
2772
2773 dsi_vc_enable(dsidev, channel, 0);
2774
2775 /* VC_BUSY */
2776 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2777 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2778 return -EIO;
2779 }
2780
2781 /* SOURCE, 1 = video port */
2782 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 1, 1);
2783
2784 /* DCS_CMD_ENABLE */
2785 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC))
2786 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 30, 30);
2787
2788 dsi_vc_enable(dsidev, channel, 1);
2789
2790 dsi->vc[channel].mode = DSI_VC_MODE_VP;
2791
2792 return 0;
2793 }
2794
2795
2796 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2797 bool enable)
2798 {
2799 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2800
2801 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2802
2803 WARN_ON(!dsi_bus_is_locked(dsidev));
2804
2805 dsi_vc_enable(dsidev, channel, 0);
2806 dsi_if_enable(dsidev, 0);
2807
2808 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2809
2810 dsi_vc_enable(dsidev, channel, 1);
2811 dsi_if_enable(dsidev, 1);
2812
2813 dsi_force_tx_stop_mode_io(dsidev);
2814 }
2815 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2816
2817 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2818 {
2819 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2820 u32 val;
2821 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2822 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2823 (val >> 0) & 0xff,
2824 (val >> 8) & 0xff,
2825 (val >> 16) & 0xff,
2826 (val >> 24) & 0xff);
2827 }
2828 }
2829
2830 static void dsi_show_rx_ack_with_err(u16 err)
2831 {
2832 DSSERR("\tACK with ERROR (%#x):\n", err);
2833 if (err & (1 << 0))
2834 DSSERR("\t\tSoT Error\n");
2835 if (err & (1 << 1))
2836 DSSERR("\t\tSoT Sync Error\n");
2837 if (err & (1 << 2))
2838 DSSERR("\t\tEoT Sync Error\n");
2839 if (err & (1 << 3))
2840 DSSERR("\t\tEscape Mode Entry Command Error\n");
2841 if (err & (1 << 4))
2842 DSSERR("\t\tLP Transmit Sync Error\n");
2843 if (err & (1 << 5))
2844 DSSERR("\t\tHS Receive Timeout Error\n");
2845 if (err & (1 << 6))
2846 DSSERR("\t\tFalse Control Error\n");
2847 if (err & (1 << 7))
2848 DSSERR("\t\t(reserved7)\n");
2849 if (err & (1 << 8))
2850 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2851 if (err & (1 << 9))
2852 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2853 if (err & (1 << 10))
2854 DSSERR("\t\tChecksum Error\n");
2855 if (err & (1 << 11))
2856 DSSERR("\t\tData type not recognized\n");
2857 if (err & (1 << 12))
2858 DSSERR("\t\tInvalid VC ID\n");
2859 if (err & (1 << 13))
2860 DSSERR("\t\tInvalid Transmission Length\n");
2861 if (err & (1 << 14))
2862 DSSERR("\t\t(reserved14)\n");
2863 if (err & (1 << 15))
2864 DSSERR("\t\tDSI Protocol Violation\n");
2865 }
2866
2867 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2868 int channel)
2869 {
2870 /* RX_FIFO_NOT_EMPTY */
2871 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2872 u32 val;
2873 u8 dt;
2874 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2875 DSSERR("\trawval %#08x\n", val);
2876 dt = FLD_GET(val, 5, 0);
2877 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
2878 u16 err = FLD_GET(val, 23, 8);
2879 dsi_show_rx_ack_with_err(err);
2880 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
2881 DSSERR("\tDCS short response, 1 byte: %#x\n",
2882 FLD_GET(val, 23, 8));
2883 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
2884 DSSERR("\tDCS short response, 2 byte: %#x\n",
2885 FLD_GET(val, 23, 8));
2886 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
2887 DSSERR("\tDCS long response, len %d\n",
2888 FLD_GET(val, 23, 8));
2889 dsi_vc_flush_long_data(dsidev, channel);
2890 } else {
2891 DSSERR("\tunknown datatype 0x%02x\n", dt);
2892 }
2893 }
2894 return 0;
2895 }
2896
2897 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2898 {
2899 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2900
2901 if (dsi->debug_write || dsi->debug_read)
2902 DSSDBG("dsi_vc_send_bta %d\n", channel);
2903
2904 WARN_ON(!dsi_bus_is_locked(dsidev));
2905
2906 /* RX_FIFO_NOT_EMPTY */
2907 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2908 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2909 dsi_vc_flush_receive_data(dsidev, channel);
2910 }
2911
2912 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2913
2914 return 0;
2915 }
2916
2917 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2918 {
2919 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2920 DECLARE_COMPLETION_ONSTACK(completion);
2921 int r = 0;
2922 u32 err;
2923
2924 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2925 &completion, DSI_VC_IRQ_BTA);
2926 if (r)
2927 goto err0;
2928
2929 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2930 DSI_IRQ_ERROR_MASK);
2931 if (r)
2932 goto err1;
2933
2934 r = dsi_vc_send_bta(dsidev, channel);
2935 if (r)
2936 goto err2;
2937
2938 if (wait_for_completion_timeout(&completion,
2939 msecs_to_jiffies(500)) == 0) {
2940 DSSERR("Failed to receive BTA\n");
2941 r = -EIO;
2942 goto err2;
2943 }
2944
2945 err = dsi_get_errors(dsidev);
2946 if (err) {
2947 DSSERR("Error while sending BTA: %x\n", err);
2948 r = -EIO;
2949 goto err2;
2950 }
2951 err2:
2952 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2953 DSI_IRQ_ERROR_MASK);
2954 err1:
2955 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2956 &completion, DSI_VC_IRQ_BTA);
2957 err0:
2958 return r;
2959 }
2960 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
2961
2962 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2963 int channel, u8 data_type, u16 len, u8 ecc)
2964 {
2965 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2966 u32 val;
2967 u8 data_id;
2968
2969 WARN_ON(!dsi_bus_is_locked(dsidev));
2970
2971 data_id = data_type | dsi->vc[channel].vc_id << 6;
2972
2973 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2974 FLD_VAL(ecc, 31, 24);
2975
2976 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2977 }
2978
2979 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2980 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2981 {
2982 u32 val;
2983
2984 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2985
2986 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2987 b1, b2, b3, b4, val); */
2988
2989 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2990 }
2991
2992 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2993 u8 data_type, u8 *data, u16 len, u8 ecc)
2994 {
2995 /*u32 val; */
2996 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2997 int i;
2998 u8 *p;
2999 int r = 0;
3000 u8 b1, b2, b3, b4;
3001
3002 if (dsi->debug_write)
3003 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
3004
3005 /* len + header */
3006 if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
3007 DSSERR("unable to send long packet: packet too long.\n");
3008 return -EINVAL;
3009 }
3010
3011 dsi_vc_config_l4(dsidev, channel);
3012
3013 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
3014
3015 p = data;
3016 for (i = 0; i < len >> 2; i++) {
3017 if (dsi->debug_write)
3018 DSSDBG("\tsending full packet %d\n", i);
3019
3020 b1 = *p++;
3021 b2 = *p++;
3022 b3 = *p++;
3023 b4 = *p++;
3024
3025 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
3026 }
3027
3028 i = len % 4;
3029 if (i) {
3030 b1 = 0; b2 = 0; b3 = 0;
3031
3032 if (dsi->debug_write)
3033 DSSDBG("\tsending remainder bytes %d\n", i);
3034
3035 switch (i) {
3036 case 3:
3037 b1 = *p++;
3038 b2 = *p++;
3039 b3 = *p++;
3040 break;
3041 case 2:
3042 b1 = *p++;
3043 b2 = *p++;
3044 break;
3045 case 1:
3046 b1 = *p++;
3047 break;
3048 }
3049
3050 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
3051 }
3052
3053 return r;
3054 }
3055
3056 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
3057 u8 data_type, u16 data, u8 ecc)
3058 {
3059 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3060 u32 r;
3061 u8 data_id;
3062
3063 WARN_ON(!dsi_bus_is_locked(dsidev));
3064
3065 if (dsi->debug_write)
3066 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
3067 channel,
3068 data_type, data & 0xff, (data >> 8) & 0xff);
3069
3070 dsi_vc_config_l4(dsidev, channel);
3071
3072 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
3073 DSSERR("ERROR FIFO FULL, aborting transfer\n");
3074 return -EINVAL;
3075 }
3076
3077 data_id = data_type | dsi->vc[channel].vc_id << 6;
3078
3079 r = (data_id << 0) | (data << 8) | (ecc << 24);
3080
3081 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
3082
3083 return 0;
3084 }
3085
3086 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
3087 {
3088 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3089 u8 nullpkg[] = {0, 0, 0, 0};
3090
3091 return dsi_vc_send_long(dsidev, channel, DSI_DT_NULL_PACKET, nullpkg,
3092 4, 0);
3093 }
3094 EXPORT_SYMBOL(dsi_vc_send_null);
3095
3096 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3097 u8 *data, int len)
3098 {
3099 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3100 int r;
3101
3102 BUG_ON(len == 0);
3103
3104 if (len == 1) {
3105 r = dsi_vc_send_short(dsidev, channel, DSI_DT_DCS_SHORT_WRITE_0,
3106 data[0], 0);
3107 } else if (len == 2) {
3108 r = dsi_vc_send_short(dsidev, channel, DSI_DT_DCS_SHORT_WRITE_1,
3109 data[0] | (data[1] << 8), 0);
3110 } else {
3111 /* 0x39 = DCS Long Write */
3112 r = dsi_vc_send_long(dsidev, channel, DSI_DT_DCS_LONG_WRITE,
3113 data, len, 0);
3114 }
3115
3116 return r;
3117 }
3118 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
3119
3120 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3121 int len)
3122 {
3123 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3124 int r;
3125
3126 r = dsi_vc_dcs_write_nosync(dssdev, channel, data, len);
3127 if (r)
3128 goto err;
3129
3130 r = dsi_vc_send_bta_sync(dssdev, channel);
3131 if (r)
3132 goto err;
3133
3134 /* RX_FIFO_NOT_EMPTY */
3135 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3136 DSSERR("rx fifo not empty after write, dumping data:\n");
3137 dsi_vc_flush_receive_data(dsidev, channel);
3138 r = -EIO;
3139 goto err;
3140 }
3141
3142 return 0;
3143 err:
3144 DSSERR("dsi_vc_dcs_write(ch %d, cmd 0x%02x, len %d) failed\n",
3145 channel, data[0], len);
3146 return r;
3147 }
3148 EXPORT_SYMBOL(dsi_vc_dcs_write);
3149
3150 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
3151 {
3152 return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
3153 }
3154 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
3155
3156 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3157 u8 param)
3158 {
3159 u8 buf[2];
3160 buf[0] = dcs_cmd;
3161 buf[1] = param;
3162 return dsi_vc_dcs_write(dssdev, channel, buf, 2);
3163 }
3164 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
3165
3166 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3167 u8 *buf, int buflen)
3168 {
3169 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3170 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3171 u32 val;
3172 u8 dt;
3173 int r;
3174
3175 if (dsi->debug_read)
3176 DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd);
3177
3178 r = dsi_vc_send_short(dsidev, channel, DSI_DT_DCS_READ, dcs_cmd, 0);
3179 if (r)
3180 goto err;
3181
3182 r = dsi_vc_send_bta_sync(dssdev, channel);
3183 if (r)
3184 goto err;
3185
3186 /* RX_FIFO_NOT_EMPTY */
3187 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3188 DSSERR("RX fifo empty when trying to read.\n");
3189 r = -EIO;
3190 goto err;
3191 }
3192
3193 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3194 if (dsi->debug_read)
3195 DSSDBG("\theader: %08x\n", val);
3196 dt = FLD_GET(val, 5, 0);
3197 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
3198 u16 err = FLD_GET(val, 23, 8);
3199 dsi_show_rx_ack_with_err(err);
3200 r = -EIO;
3201 goto err;
3202
3203 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
3204 u8 data = FLD_GET(val, 15, 8);
3205 if (dsi->debug_read)
3206 DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
3207
3208 if (buflen < 1) {
3209 r = -EIO;
3210 goto err;
3211 }
3212
3213 buf[0] = data;
3214
3215 return 1;
3216 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
3217 u16 data = FLD_GET(val, 23, 8);
3218 if (dsi->debug_read)
3219 DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
3220
3221 if (buflen < 2) {
3222 r = -EIO;
3223 goto err;
3224 }
3225
3226 buf[0] = data & 0xff;
3227 buf[1] = (data >> 8) & 0xff;
3228
3229 return 2;
3230 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
3231 int w;
3232 int len = FLD_GET(val, 23, 8);
3233 if (dsi->debug_read)
3234 DSSDBG("\tDCS long response, len %d\n", len);
3235
3236 if (len > buflen) {
3237 r = -EIO;
3238 goto err;
3239 }
3240
3241 /* two byte checksum ends the packet, not included in len */
3242 for (w = 0; w < len + 2;) {
3243 int b;
3244 val = dsi_read_reg(dsidev,
3245 DSI_VC_SHORT_PACKET_HEADER(channel));
3246 if (dsi->debug_read)
3247 DSSDBG("\t\t%02x %02x %02x %02x\n",
3248 (val >> 0) & 0xff,
3249 (val >> 8) & 0xff,
3250 (val >> 16) & 0xff,
3251 (val >> 24) & 0xff);
3252
3253 for (b = 0; b < 4; ++b) {
3254 if (w < len)
3255 buf[w] = (val >> (b * 8)) & 0xff;
3256 /* we discard the 2 byte checksum */
3257 ++w;
3258 }
3259 }
3260
3261 return len;
3262 } else {
3263 DSSERR("\tunknown datatype 0x%02x\n", dt);
3264 r = -EIO;
3265 goto err;
3266 }
3267
3268 BUG();
3269 err:
3270 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n",
3271 channel, dcs_cmd);
3272 return r;
3273
3274 }
3275 EXPORT_SYMBOL(dsi_vc_dcs_read);
3276
3277 int dsi_vc_dcs_read_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3278 u8 *data)
3279 {
3280 int r;
3281
3282 r = dsi_vc_dcs_read(dssdev, channel, dcs_cmd, data, 1);
3283
3284 if (r < 0)
3285 return r;
3286
3287 if (r != 1)
3288 return -EIO;
3289
3290 return 0;
3291 }
3292 EXPORT_SYMBOL(dsi_vc_dcs_read_1);
3293
3294 int dsi_vc_dcs_read_2(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3295 u8 *data1, u8 *data2)
3296 {
3297 u8 buf[2];
3298 int r;
3299
3300 r = dsi_vc_dcs_read(dssdev, channel, dcs_cmd, buf, 2);
3301
3302 if (r < 0)
3303 return r;
3304
3305 if (r != 2)
3306 return -EIO;
3307
3308 *data1 = buf[0];
3309 *data2 = buf[1];
3310
3311 return 0;
3312 }
3313 EXPORT_SYMBOL(dsi_vc_dcs_read_2);
3314
3315 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3316 u16 len)
3317 {
3318 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3319
3320 return dsi_vc_send_short(dsidev, channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
3321 len, 0);
3322 }
3323 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
3324
3325 static int dsi_enter_ulps(struct platform_device *dsidev)
3326 {
3327 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3328 DECLARE_COMPLETION_ONSTACK(completion);
3329 int r;
3330
3331 DSSDBGF();
3332
3333 WARN_ON(!dsi_bus_is_locked(dsidev));
3334
3335 WARN_ON(dsi->ulps_enabled);
3336
3337 if (dsi->ulps_enabled)
3338 return 0;
3339
3340 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3341 DSSERR("DDR_CLK_ALWAYS_ON enabled when entering ULPS\n");
3342 return -EIO;
3343 }
3344
3345 dsi_sync_vc(dsidev, 0);
3346 dsi_sync_vc(dsidev, 1);
3347 dsi_sync_vc(dsidev, 2);
3348 dsi_sync_vc(dsidev, 3);
3349
3350 dsi_force_tx_stop_mode_io(dsidev);
3351
3352 dsi_vc_enable(dsidev, 0, false);
3353 dsi_vc_enable(dsidev, 1, false);
3354 dsi_vc_enable(dsidev, 2, false);
3355 dsi_vc_enable(dsidev, 3, false);
3356
3357 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3358 DSSERR("HS busy when enabling ULPS\n");
3359 return -EIO;
3360 }
3361
3362 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3363 DSSERR("LP busy when enabling ULPS\n");
3364 return -EIO;
3365 }
3366
3367 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3368 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3369 if (r)
3370 return r;
3371
3372 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3373 /* LANEx_ULPS_SIG2 */
3374 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (1 << 0) | (1 << 1) | (1 << 2),
3375 7, 5);
3376
3377 if (wait_for_completion_timeout(&completion,
3378 msecs_to_jiffies(1000)) == 0) {
3379 DSSERR("ULPS enable timeout\n");
3380 r = -EIO;
3381 goto err;
3382 }
3383
3384 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3385 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3386
3387 /* Reset LANEx_ULPS_SIG2 */
3388 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (0 << 0) | (0 << 1) | (0 << 2),
3389 7, 5);
3390
3391 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3392
3393 dsi_if_enable(dsidev, false);
3394
3395 dsi->ulps_enabled = true;
3396
3397 return 0;
3398
3399 err:
3400 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3401 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3402 return r;
3403 }
3404
3405 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3406 unsigned ticks, bool x4, bool x16)
3407 {
3408 unsigned long fck;
3409 unsigned long total_ticks;
3410 u32 r;
3411
3412 BUG_ON(ticks > 0x1fff);
3413
3414 /* ticks in DSI_FCK */
3415 fck = dsi_fclk_rate(dsidev);
3416
3417 r = dsi_read_reg(dsidev, DSI_TIMING2);
3418 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3419 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3420 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3421 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3422 dsi_write_reg(dsidev, DSI_TIMING2, r);
3423
3424 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3425
3426 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3427 total_ticks,
3428 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3429 (total_ticks * 1000) / (fck / 1000 / 1000));
3430 }
3431
3432 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3433 bool x8, bool x16)
3434 {
3435 unsigned long fck;
3436 unsigned long total_ticks;
3437 u32 r;
3438
3439 BUG_ON(ticks > 0x1fff);
3440
3441 /* ticks in DSI_FCK */
3442 fck = dsi_fclk_rate(dsidev);
3443
3444 r = dsi_read_reg(dsidev, DSI_TIMING1);
3445 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3446 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3447 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3448 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3449 dsi_write_reg(dsidev, DSI_TIMING1, r);
3450
3451 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3452
3453 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3454 total_ticks,
3455 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3456 (total_ticks * 1000) / (fck / 1000 / 1000));
3457 }
3458
3459 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3460 unsigned ticks, bool x4, bool x16)
3461 {
3462 unsigned long fck;
3463 unsigned long total_ticks;
3464 u32 r;
3465
3466 BUG_ON(ticks > 0x1fff);
3467
3468 /* ticks in DSI_FCK */
3469 fck = dsi_fclk_rate(dsidev);
3470
3471 r = dsi_read_reg(dsidev, DSI_TIMING1);
3472 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3473 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3474 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3475 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3476 dsi_write_reg(dsidev, DSI_TIMING1, r);
3477
3478 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3479
3480 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3481 total_ticks,
3482 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3483 (total_ticks * 1000) / (fck / 1000 / 1000));
3484 }
3485
3486 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3487 unsigned ticks, bool x4, bool x16)
3488 {
3489 unsigned long fck;
3490 unsigned long total_ticks;
3491 u32 r;
3492
3493 BUG_ON(ticks > 0x1fff);
3494
3495 /* ticks in TxByteClkHS */
3496 fck = dsi_get_txbyteclkhs(dsidev);
3497
3498 r = dsi_read_reg(dsidev, DSI_TIMING2);
3499 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3500 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3501 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3502 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3503 dsi_write_reg(dsidev, DSI_TIMING2, r);
3504
3505 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3506
3507 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3508 total_ticks,
3509 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3510 (total_ticks * 1000) / (fck / 1000 / 1000));
3511 }
3512 static int dsi_proto_config(struct omap_dss_device *dssdev)
3513 {
3514 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3515 u32 r;
3516 int buswidth = 0;
3517
3518 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3519 DSI_FIFO_SIZE_32,
3520 DSI_FIFO_SIZE_32,
3521 DSI_FIFO_SIZE_32);
3522
3523 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3524 DSI_FIFO_SIZE_32,
3525 DSI_FIFO_SIZE_32,
3526 DSI_FIFO_SIZE_32);
3527
3528 /* XXX what values for the timeouts? */
3529 dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3530 dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3531 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3532 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3533
3534 switch (dssdev->ctrl.pixel_size) {
3535 case 16:
3536 buswidth = 0;
3537 break;
3538 case 18:
3539 buswidth = 1;
3540 break;
3541 case 24:
3542 buswidth = 2;
3543 break;
3544 default:
3545 BUG();
3546 }
3547
3548 r = dsi_read_reg(dsidev, DSI_CTRL);
3549 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
3550 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
3551 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3552 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3553 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3554 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
3555 r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
3556 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
3557 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
3558 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3559 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
3560 /* DCS_CMD_CODE, 1=start, 0=continue */
3561 r = FLD_MOD(r, 0, 25, 25);
3562 }
3563
3564 dsi_write_reg(dsidev, DSI_CTRL, r);
3565
3566 dsi_vc_initial_config(dsidev, 0);
3567 dsi_vc_initial_config(dsidev, 1);
3568 dsi_vc_initial_config(dsidev, 2);
3569 dsi_vc_initial_config(dsidev, 3);
3570
3571 return 0;
3572 }
3573
3574 static void dsi_proto_timings(struct omap_dss_device *dssdev)
3575 {
3576 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3577 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3578 unsigned tclk_pre, tclk_post;
3579 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3580 unsigned ths_trail, ths_exit;
3581 unsigned ddr_clk_pre, ddr_clk_post;
3582 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3583 unsigned ths_eot;
3584 u32 r;
3585
3586 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3587 ths_prepare = FLD_GET(r, 31, 24);
3588 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3589 ths_zero = ths_prepare_ths_zero - ths_prepare;
3590 ths_trail = FLD_GET(r, 15, 8);
3591 ths_exit = FLD_GET(r, 7, 0);
3592
3593 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3594 tlpx = FLD_GET(r, 22, 16) * 2;
3595 tclk_trail = FLD_GET(r, 15, 8);
3596 tclk_zero = FLD_GET(r, 7, 0);
3597
3598 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3599 tclk_prepare = FLD_GET(r, 7, 0);
3600
3601 /* min 8*UI */
3602 tclk_pre = 20;
3603 /* min 60ns + 52*UI */
3604 tclk_post = ns2ddr(dsidev, 60) + 26;
3605
3606 ths_eot = DIV_ROUND_UP(4, dsi_get_num_data_lanes_dssdev(dssdev));
3607
3608 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3609 4);
3610 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3611
3612 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3613 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3614
3615 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3616 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3617 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3618 dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3619
3620 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3621 ddr_clk_pre,
3622 ddr_clk_post);
3623
3624 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3625 DIV_ROUND_UP(ths_prepare, 4) +
3626 DIV_ROUND_UP(ths_zero + 3, 4);
3627
3628 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3629
3630 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3631 FLD_VAL(exit_hs_mode_lat, 15, 0);
3632 dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3633
3634 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3635 enter_hs_mode_lat, exit_hs_mode_lat);
3636 }
3637
3638
3639 #define DSI_DECL_VARS \
3640 int __dsi_cb = 0; u32 __dsi_cv = 0;
3641
3642 #define DSI_FLUSH(dsidev, ch) \
3643 if (__dsi_cb > 0) { \
3644 /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
3645 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
3646 __dsi_cb = __dsi_cv = 0; \
3647 }
3648
3649 #define DSI_PUSH(dsidev, ch, data) \
3650 do { \
3651 __dsi_cv |= (data) << (__dsi_cb * 8); \
3652 /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
3653 if (++__dsi_cb > 3) \
3654 DSI_FLUSH(dsidev, ch); \
3655 } while (0)
3656
3657 static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
3658 int x, int y, int w, int h)
3659 {
3660 /* Note: supports only 24bit colors in 32bit container */
3661 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3662 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3663 int first = 1;
3664 int fifo_stalls = 0;
3665 int max_dsi_packet_size;
3666 int max_data_per_packet;
3667 int max_pixels_per_packet;
3668 int pixels_left;
3669 int bytespp = dssdev->ctrl.pixel_size / 8;
3670 int scr_width;
3671 u32 __iomem *data;
3672 int start_offset;
3673 int horiz_inc;
3674 int current_x;
3675 struct omap_overlay *ovl;
3676
3677 debug_irq = 0;
3678
3679 DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
3680 x, y, w, h);
3681
3682 ovl = dssdev->manager->overlays[0];
3683
3684 if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
3685 return -EINVAL;
3686
3687 if (dssdev->ctrl.pixel_size != 24)
3688 return -EINVAL;
3689
3690 scr_width = ovl->info.screen_width;
3691 data = ovl->info.vaddr;
3692
3693 start_offset = scr_width * y + x;
3694 horiz_inc = scr_width - w;
3695 current_x = x;
3696
3697 /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
3698 * in fifo */
3699
3700 /* When using CPU, max long packet size is TX buffer size */
3701 max_dsi_packet_size = dsi->vc[0].fifo_size * 32 * 4;
3702
3703 /* we seem to get better perf if we divide the tx fifo to half,
3704 and while the other half is being sent, we fill the other half
3705 max_dsi_packet_size /= 2; */
3706
3707 max_data_per_packet = max_dsi_packet_size - 4 - 1;
3708
3709 max_pixels_per_packet = max_data_per_packet / bytespp;
3710
3711 DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
3712
3713 pixels_left = w * h;
3714
3715 DSSDBG("total pixels %d\n", pixels_left);
3716
3717 data += start_offset;
3718
3719 while (pixels_left > 0) {
3720 /* 0x2c = write_memory_start */
3721 /* 0x3c = write_memory_continue */
3722 u8 dcs_cmd = first ? 0x2c : 0x3c;
3723 int pixels;
3724 DSI_DECL_VARS;
3725 first = 0;
3726
3727 #if 1
3728 /* using fifo not empty */
3729 /* TX_FIFO_NOT_EMPTY */
3730 while (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(0)), 5, 5)) {
3731 fifo_stalls++;
3732 if (fifo_stalls > 0xfffff) {
3733 DSSERR("fifo stalls overflow, pixels left %d\n",
3734 pixels_left);
3735 dsi_if_enable(dsidev, 0);
3736 return -EIO;
3737 }
3738 udelay(1);
3739 }
3740 #elif 1
3741 /* using fifo emptiness */
3742 while ((REG_GET(dsidev, DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
3743 max_dsi_packet_size) {
3744 fifo_stalls++;
3745 if (fifo_stalls > 0xfffff) {
3746 DSSERR("fifo stalls overflow, pixels left %d\n",
3747 pixels_left);
3748 dsi_if_enable(dsidev, 0);
3749 return -EIO;
3750 }
3751 }
3752 #else
3753 while ((REG_GET(dsidev, DSI_TX_FIFO_VC_EMPTINESS,
3754 7, 0) + 1) * 4 == 0) {
3755 fifo_stalls++;
3756 if (fifo_stalls > 0xfffff) {
3757 DSSERR("fifo stalls overflow, pixels left %d\n",
3758 pixels_left);
3759 dsi_if_enable(dsidev, 0);
3760 return -EIO;
3761 }
3762 }
3763 #endif
3764 pixels = min(max_pixels_per_packet, pixels_left);
3765
3766 pixels_left -= pixels;
3767
3768 dsi_vc_write_long_header(dsidev, 0, DSI_DT_DCS_LONG_WRITE,
3769 1 + pixels * bytespp, 0);
3770
3771 DSI_PUSH(dsidev, 0, dcs_cmd);
3772
3773 while (pixels-- > 0) {
3774 u32 pix = __raw_readl(data++);
3775
3776 DSI_PUSH(dsidev, 0, (pix >> 16) & 0xff);
3777 DSI_PUSH(dsidev, 0, (pix >> 8) & 0xff);
3778 DSI_PUSH(dsidev, 0, (pix >> 0) & 0xff);
3779
3780 current_x++;
3781 if (current_x == x+w) {
3782 current_x = x;
3783 data += horiz_inc;
3784 }
3785 }
3786
3787 DSI_FLUSH(dsidev, 0);
3788 }
3789
3790 return 0;
3791 }
3792
3793 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
3794 u16 x, u16 y, u16 w, u16 h)
3795 {
3796 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3797 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3798 unsigned bytespp;
3799 unsigned bytespl;
3800 unsigned bytespf;
3801 unsigned total_len;
3802 unsigned packet_payload;
3803 unsigned packet_len;
3804 u32 l;
3805 int r;
3806 const unsigned channel = dsi->update_channel;
3807 const unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
3808
3809 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
3810 x, y, w, h);
3811
3812 dsi_vc_config_vp(dsidev, channel);
3813
3814 bytespp = dssdev->ctrl.pixel_size / 8;
3815 bytespl = w * bytespp;
3816 bytespf = bytespl * h;
3817
3818 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
3819 * number of lines in a packet. See errata about VP_CLK_RATIO */
3820
3821 if (bytespf < line_buf_size)
3822 packet_payload = bytespf;
3823 else
3824 packet_payload = (line_buf_size) / bytespl * bytespl;
3825
3826 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
3827 total_len = (bytespf / packet_payload) * packet_len;
3828
3829 if (bytespf % packet_payload)
3830 total_len += (bytespf % packet_payload) + 1;
3831
3832 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
3833 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
3834
3835 dsi_vc_write_long_header(dsidev, channel, DSI_DT_DCS_LONG_WRITE,
3836 packet_len, 0);
3837
3838 if (dsi->te_enabled)
3839 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
3840 else
3841 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
3842 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
3843
3844 /* We put SIDLEMODE to no-idle for the duration of the transfer,
3845 * because DSS interrupts are not capable of waking up the CPU and the
3846 * framedone interrupt could be delayed for quite a long time. I think
3847 * the same goes for any DSS interrupts, but for some reason I have not
3848 * seen the problem anywhere else than here.
3849 */
3850 dispc_disable_sidle();
3851
3852 dsi_perf_mark_start(dsidev);
3853
3854 r = schedule_delayed_work(&dsi->framedone_timeout_work,
3855 msecs_to_jiffies(250));
3856 BUG_ON(r == 0);
3857
3858 dss_start_update(dssdev);
3859
3860 if (dsi->te_enabled) {
3861 /* disable LP_RX_TO, so that we can receive TE. Time to wait
3862 * for TE is longer than the timer allows */
3863 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
3864
3865 dsi_vc_send_bta(dsidev, channel);
3866
3867 #ifdef DSI_CATCH_MISSING_TE
3868 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
3869 #endif
3870 }
3871 }
3872
3873 #ifdef DSI_CATCH_MISSING_TE
3874 static void dsi_te_timeout(unsigned long arg)
3875 {
3876 DSSERR("TE not received for 250ms!\n");
3877 }
3878 #endif
3879
3880 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
3881 {
3882 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3883
3884 /* SIDLEMODE back to smart-idle */
3885 dispc_enable_sidle();
3886
3887 if (dsi->te_enabled) {
3888 /* enable LP_RX_TO again after the TE */
3889 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
3890 }
3891
3892 dsi->framedone_callback(error, dsi->framedone_data);
3893
3894 if (!error)
3895 dsi_perf_show(dsidev, "DISPC");
3896 }
3897
3898 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
3899 {
3900 struct dsi_data *dsi = container_of(work, struct dsi_data,
3901 framedone_timeout_work.work);
3902 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
3903 * 250ms which would conflict with this timeout work. What should be
3904 * done is first cancel the transfer on the HW, and then cancel the
3905 * possibly scheduled framedone work. However, cancelling the transfer
3906 * on the HW is buggy, and would probably require resetting the whole
3907 * DSI */
3908
3909 DSSERR("Framedone not received for 250ms!\n");
3910
3911 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
3912 }
3913
3914 static void dsi_framedone_irq_callback(void *data, u32 mask)
3915 {
3916 struct omap_dss_device *dssdev = (struct omap_dss_device *) data;
3917 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3918 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3919
3920 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
3921 * turns itself off. However, DSI still has the pixels in its buffers,
3922 * and is sending the data.
3923 */
3924
3925 __cancel_delayed_work(&dsi->framedone_timeout_work);
3926
3927 dsi_handle_framedone(dsidev, 0);
3928
3929 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3930 dispc_fake_vsync_irq();
3931 #endif
3932 }
3933
3934 int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
3935 u16 *x, u16 *y, u16 *w, u16 *h,
3936 bool enlarge_update_area)
3937 {
3938 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3939 u16 dw, dh;
3940
3941 dssdev->driver->get_resolution(dssdev, &dw, &dh);
3942
3943 if (*x > dw || *y > dh)
3944 return -EINVAL;
3945
3946 if (*x + *w > dw)
3947 return -EINVAL;
3948
3949 if (*y + *h > dh)
3950 return -EINVAL;
3951
3952 if (*w == 1)
3953 return -EINVAL;
3954
3955 if (*w == 0 || *h == 0)
3956 return -EINVAL;
3957
3958 dsi_perf_mark_setup(dsidev);
3959
3960 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
3961 dss_setup_partial_planes(dssdev, x, y, w, h,
3962 enlarge_update_area);
3963 dispc_set_lcd_size(dssdev->manager->id, *w, *h);
3964 }
3965
3966 return 0;
3967 }
3968 EXPORT_SYMBOL(omap_dsi_prepare_update);
3969
3970 int omap_dsi_update(struct omap_dss_device *dssdev,
3971 int channel,
3972 u16 x, u16 y, u16 w, u16 h,
3973 void (*callback)(int, void *), void *data)
3974 {
3975 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3976 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3977
3978 dsi->update_channel = channel;
3979
3980 /* OMAP DSS cannot send updates of odd widths.
3981 * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
3982 * here to make sure we catch erroneous updates. Otherwise we'll only
3983 * see rather obscure HW error happening, as DSS halts. */
3984 BUG_ON(x % 2 == 1);
3985
3986 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
3987 dsi->framedone_callback = callback;
3988 dsi->framedone_data = data;
3989
3990 dsi->update_region.x = x;
3991 dsi->update_region.y = y;
3992 dsi->update_region.w = w;
3993 dsi->update_region.h = h;
3994 dsi->update_region.device = dssdev;
3995
3996 dsi_update_screen_dispc(dssdev, x, y, w, h);
3997 } else {
3998 int r;
3999
4000 r = dsi_update_screen_l4(dssdev, x, y, w, h);
4001 if (r)
4002 return r;
4003
4004 dsi_perf_show(dsidev, "L4");
4005 callback(0, data);
4006 }
4007
4008 return 0;
4009 }
4010 EXPORT_SYMBOL(omap_dsi_update);
4011
4012 /* Display funcs */
4013
4014 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
4015 {
4016 int r;
4017 u32 irq;
4018
4019 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4020 DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4021
4022 r = omap_dispc_register_isr(dsi_framedone_irq_callback, (void *) dssdev,
4023 irq);
4024 if (r) {
4025 DSSERR("can't get FRAMEDONE irq\n");
4026 return r;
4027 }
4028
4029 dispc_set_lcd_display_type(dssdev->manager->id,
4030 OMAP_DSS_LCD_DISPLAY_TFT);
4031
4032 dispc_set_parallel_interface_mode(dssdev->manager->id,
4033 OMAP_DSS_PARALLELMODE_DSI);
4034 dispc_enable_fifohandcheck(dssdev->manager->id, 1);
4035
4036 dispc_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size);
4037
4038 {
4039 struct omap_video_timings timings = {
4040 .hsw = 1,
4041 .hfp = 1,
4042 .hbp = 1,
4043 .vsw = 1,
4044 .vfp = 0,
4045 .vbp = 0,
4046 };
4047
4048 dispc_set_lcd_timings(dssdev->manager->id, &timings);
4049 }
4050
4051 return 0;
4052 }
4053
4054 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
4055 {
4056 u32 irq;
4057
4058 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4059 DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4060
4061 omap_dispc_unregister_isr(dsi_framedone_irq_callback, (void *) dssdev,
4062 irq);
4063 }
4064
4065 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
4066 {
4067 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4068 struct dsi_clock_info cinfo;
4069 int r;
4070
4071 /* we always use DSS_CLK_SYSCK as input clock */
4072 cinfo.use_sys_clk = true;
4073 cinfo.regn = dssdev->clocks.dsi.regn;
4074 cinfo.regm = dssdev->clocks.dsi.regm;
4075 cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc;
4076 cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi;
4077 r = dsi_calc_clock_rates(dssdev, &cinfo);
4078 if (r) {
4079 DSSERR("Failed to calc dsi clocks\n");
4080 return r;
4081 }
4082
4083 r = dsi_pll_set_clock_div(dsidev, &cinfo);
4084 if (r) {
4085 DSSERR("Failed to set dsi clocks\n");
4086 return r;
4087 }
4088
4089 return 0;
4090 }
4091
4092 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
4093 {
4094 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4095 struct dispc_clock_info dispc_cinfo;
4096 int r;
4097 unsigned long long fck;
4098
4099 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4100
4101 dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
4102 dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
4103
4104 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4105 if (r) {
4106 DSSERR("Failed to calc dispc clocks\n");
4107 return r;
4108 }
4109
4110 r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
4111 if (r) {
4112 DSSERR("Failed to set dispc clocks\n");
4113 return r;
4114 }
4115
4116 return 0;
4117 }
4118
4119 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
4120 {
4121 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4122 int dsi_module = dsi_get_dsidev_id(dsidev);
4123 int r;
4124
4125 r = dsi_pll_init(dsidev, true, true);
4126 if (r)
4127 goto err0;
4128
4129 r = dsi_configure_dsi_clocks(dssdev);
4130 if (r)
4131 goto err1;
4132
4133 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
4134 dss_select_dsi_clk_source(dsi_module, dssdev->clocks.dsi.dsi_fclk_src);
4135 dss_select_lcd_clk_source(dssdev->manager->id,
4136 dssdev->clocks.dispc.channel.lcd_clk_src);
4137
4138 DSSDBG("PLL OK\n");
4139
4140 r = dsi_configure_dispc_clocks(dssdev);
4141 if (r)
4142 goto err2;
4143
4144 r = dsi_cio_init(dssdev);
4145 if (r)
4146 goto err2;
4147
4148 _dsi_print_reset_status(dsidev);
4149
4150 dsi_proto_timings(dssdev);
4151 dsi_set_lp_clk_divisor(dssdev);
4152
4153 if (1)
4154 _dsi_print_reset_status(dsidev);
4155
4156 r = dsi_proto_config(dssdev);
4157 if (r)
4158 goto err3;
4159
4160 /* enable interface */
4161 dsi_vc_enable(dsidev, 0, 1);
4162 dsi_vc_enable(dsidev, 1, 1);
4163 dsi_vc_enable(dsidev, 2, 1);
4164 dsi_vc_enable(dsidev, 3, 1);
4165 dsi_if_enable(dsidev, 1);
4166 dsi_force_tx_stop_mode_io(dsidev);
4167
4168 return 0;
4169 err3:
4170 dsi_cio_uninit(dsidev);
4171 err2:
4172 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4173 dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4174 err1:
4175 dsi_pll_uninit(dsidev, true);
4176 err0:
4177 return r;
4178 }
4179
4180 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev,
4181 bool disconnect_lanes, bool enter_ulps)
4182 {
4183 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4184 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4185 int dsi_module = dsi_get_dsidev_id(dsidev);
4186
4187 if (enter_ulps && !dsi->ulps_enabled)
4188 dsi_enter_ulps(dsidev);
4189
4190 /* disable interface */
4191 dsi_if_enable(dsidev, 0);
4192 dsi_vc_enable(dsidev, 0, 0);
4193 dsi_vc_enable(dsidev, 1, 0);
4194 dsi_vc_enable(dsidev, 2, 0);
4195 dsi_vc_enable(dsidev, 3, 0);
4196
4197 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4198 dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4199 dsi_cio_uninit(dsidev);
4200 dsi_pll_uninit(dsidev, disconnect_lanes);
4201 }
4202
4203 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
4204 {
4205 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4206 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4207 int r = 0;
4208
4209 DSSDBG("dsi_display_enable\n");
4210
4211 WARN_ON(!dsi_bus_is_locked(dsidev));
4212
4213 mutex_lock(&dsi->lock);
4214
4215 r = omap_dss_start_device(dssdev);
4216 if (r) {
4217 DSSERR("failed to start device\n");
4218 goto err_start_dev;
4219 }
4220
4221 r = dsi_runtime_get(dsidev);
4222 if (r)
4223 goto err_get_dsi;
4224
4225 dsi_enable_pll_clock(dsidev, 1);
4226
4227 _dsi_initialize_irq(dsidev);
4228
4229 r = dsi_display_init_dispc(dssdev);
4230 if (r)
4231 goto err_init_dispc;
4232
4233 r = dsi_display_init_dsi(dssdev);
4234 if (r)
4235 goto err_init_dsi;
4236
4237 mutex_unlock(&dsi->lock);
4238
4239 return 0;
4240
4241 err_init_dsi:
4242 dsi_display_uninit_dispc(dssdev);
4243 err_init_dispc:
4244 dsi_enable_pll_clock(dsidev, 0);
4245 dsi_runtime_put(dsidev);
4246 err_get_dsi:
4247 omap_dss_stop_device(dssdev);
4248 err_start_dev:
4249 mutex_unlock(&dsi->lock);
4250 DSSDBG("dsi_display_enable FAILED\n");
4251 return r;
4252 }
4253 EXPORT_SYMBOL(omapdss_dsi_display_enable);
4254
4255 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
4256 bool disconnect_lanes, bool enter_ulps)
4257 {
4258 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4259 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4260
4261 DSSDBG("dsi_display_disable\n");
4262
4263 WARN_ON(!dsi_bus_is_locked(dsidev));
4264
4265 mutex_lock(&dsi->lock);
4266
4267 dsi_sync_vc(dsidev, 0);
4268 dsi_sync_vc(dsidev, 1);
4269 dsi_sync_vc(dsidev, 2);
4270 dsi_sync_vc(dsidev, 3);
4271
4272 dsi_display_uninit_dispc(dssdev);
4273
4274 dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps);
4275
4276 dsi_runtime_put(dsidev);
4277 dsi_enable_pll_clock(dsidev, 0);
4278
4279 omap_dss_stop_device(dssdev);
4280
4281 mutex_unlock(&dsi->lock);
4282 }
4283 EXPORT_SYMBOL(omapdss_dsi_display_disable);
4284
4285 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4286 {
4287 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4288 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4289
4290 dsi->te_enabled = enable;
4291 return 0;
4292 }
4293 EXPORT_SYMBOL(omapdss_dsi_enable_te);
4294
4295 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
4296 u32 fifo_size, u32 burst_size,
4297 u32 *fifo_low, u32 *fifo_high)
4298 {
4299 *fifo_high = fifo_size - burst_size;
4300 *fifo_low = fifo_size - burst_size * 2;
4301 }
4302
4303 int dsi_init_display(struct omap_dss_device *dssdev)
4304 {
4305 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4306 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4307 int dsi_module = dsi_get_dsidev_id(dsidev);
4308
4309 DSSDBG("DSI init\n");
4310
4311 /* XXX these should be figured out dynamically */
4312 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
4313 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
4314
4315 if (dsi->vdds_dsi_reg == NULL) {
4316 struct regulator *vdds_dsi;
4317
4318 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
4319
4320 if (IS_ERR(vdds_dsi)) {
4321 DSSERR("can't get VDDS_DSI regulator\n");
4322 return PTR_ERR(vdds_dsi);
4323 }
4324
4325 dsi->vdds_dsi_reg = vdds_dsi;
4326 }
4327
4328 if (dsi_get_num_data_lanes_dssdev(dssdev) > dsi->num_data_lanes) {
4329 DSSERR("DSI%d can't support more than %d data lanes\n",
4330 dsi_module + 1, dsi->num_data_lanes);
4331 return -EINVAL;
4332 }
4333
4334 return 0;
4335 }
4336
4337 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4338 {
4339 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4340 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4341 int i;
4342
4343 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4344 if (!dsi->vc[i].dssdev) {
4345 dsi->vc[i].dssdev = dssdev;
4346 *channel = i;
4347 return 0;
4348 }
4349 }
4350
4351 DSSERR("cannot get VC for display %s", dssdev->name);
4352 return -ENOSPC;
4353 }
4354 EXPORT_SYMBOL(omap_dsi_request_vc);
4355
4356 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4357 {
4358 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4359 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4360
4361 if (vc_id < 0 || vc_id > 3) {
4362 DSSERR("VC ID out of range\n");
4363 return -EINVAL;
4364 }
4365
4366 if (channel < 0 || channel > 3) {
4367 DSSERR("Virtual Channel out of range\n");
4368 return -EINVAL;
4369 }
4370
4371 if (dsi->vc[channel].dssdev != dssdev) {
4372 DSSERR("Virtual Channel not allocated to display %s\n",
4373 dssdev->name);
4374 return -EINVAL;
4375 }
4376
4377 dsi->vc[channel].vc_id = vc_id;
4378
4379 return 0;
4380 }
4381 EXPORT_SYMBOL(omap_dsi_set_vc_id);
4382
4383 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4384 {
4385 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4386 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4387
4388 if ((channel >= 0 && channel <= 3) &&
4389 dsi->vc[channel].dssdev == dssdev) {
4390 dsi->vc[channel].dssdev = NULL;
4391 dsi->vc[channel].vc_id = 0;
4392 }
4393 }
4394 EXPORT_SYMBOL(omap_dsi_release_vc);
4395
4396 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
4397 {
4398 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
4399 DSSERR("%s (%s) not active\n",
4400 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
4401 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
4402 }
4403
4404 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
4405 {
4406 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
4407 DSSERR("%s (%s) not active\n",
4408 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
4409 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
4410 }
4411
4412 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
4413 {
4414 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4415
4416 dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
4417 dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
4418 dsi->regm_dispc_max =
4419 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
4420 dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
4421 dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
4422 dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
4423 dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
4424 }
4425
4426 static int dsi_get_clocks(struct platform_device *dsidev)
4427 {
4428 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4429 struct clk *clk;
4430
4431 clk = clk_get(&dsidev->dev, "fck");
4432 if (IS_ERR(clk)) {
4433 DSSERR("can't get fck\n");
4434 return PTR_ERR(clk);
4435 }
4436
4437 dsi->dss_clk = clk;
4438
4439 if (cpu_is_omap34xx() || cpu_is_omap3630())
4440 clk = clk_get(&dsidev->dev, "dss2_alwon_fck");
4441 else
4442 clk = clk_get(&dsidev->dev, "sys_clk");
4443 if (IS_ERR(clk)) {
4444 DSSERR("can't get sys_clk\n");
4445 clk_put(dsi->dss_clk);
4446 dsi->dss_clk = NULL;
4447 return PTR_ERR(clk);
4448 }
4449
4450 dsi->sys_clk = clk;
4451
4452 return 0;
4453 }
4454
4455 static void dsi_put_clocks(struct platform_device *dsidev)
4456 {
4457 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4458
4459 if (dsi->dss_clk)
4460 clk_put(dsi->dss_clk);
4461 if (dsi->sys_clk)
4462 clk_put(dsi->sys_clk);
4463 }
4464
4465 /* DSI1 HW IP initialisation */
4466 static int omap_dsi1hw_probe(struct platform_device *dsidev)
4467 {
4468 struct omap_display_platform_data *dss_plat_data;
4469 struct omap_dss_board_info *board_info;
4470 u32 rev;
4471 int r, i, dsi_module = dsi_get_dsidev_id(dsidev);
4472 struct resource *dsi_mem;
4473 struct dsi_data *dsi;
4474
4475 dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
4476 if (!dsi) {
4477 r = -ENOMEM;
4478 goto err_alloc;
4479 }
4480
4481 dsi->pdev = dsidev;
4482 dsi_pdev_map[dsi_module] = dsidev;
4483 dev_set_drvdata(&dsidev->dev, dsi);
4484
4485 dss_plat_data = dsidev->dev.platform_data;
4486 board_info = dss_plat_data->board_data;
4487 dsi->dsi_mux_pads = board_info->dsi_mux_pads;
4488
4489 spin_lock_init(&dsi->irq_lock);
4490 spin_lock_init(&dsi->errors_lock);
4491 dsi->errors = 0;
4492
4493 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4494 spin_lock_init(&dsi->irq_stats_lock);
4495 dsi->irq_stats.last_reset = jiffies;
4496 #endif
4497
4498 mutex_init(&dsi->lock);
4499 sema_init(&dsi->bus_lock, 1);
4500
4501 r = dsi_get_clocks(dsidev);
4502 if (r)
4503 goto err_get_clk;
4504
4505 pm_runtime_enable(&dsidev->dev);
4506
4507 INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work,
4508 dsi_framedone_timeout_work_callback);
4509
4510 #ifdef DSI_CATCH_MISSING_TE
4511 init_timer(&dsi->te_timer);
4512 dsi->te_timer.function = dsi_te_timeout;
4513 dsi->te_timer.data = 0;
4514 #endif
4515 dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
4516 if (!dsi_mem) {
4517 DSSERR("can't get IORESOURCE_MEM DSI\n");
4518 r = -EINVAL;
4519 goto err_ioremap;
4520 }
4521 dsi->base = ioremap(dsi_mem->start, resource_size(dsi_mem));
4522 if (!dsi->base) {
4523 DSSERR("can't ioremap DSI\n");
4524 r = -ENOMEM;
4525 goto err_ioremap;
4526 }
4527 dsi->irq = platform_get_irq(dsi->pdev, 0);
4528 if (dsi->irq < 0) {
4529 DSSERR("platform_get_irq failed\n");
4530 r = -ENODEV;
4531 goto err_get_irq;
4532 }
4533
4534 r = request_irq(dsi->irq, omap_dsi_irq_handler, IRQF_SHARED,
4535 dev_name(&dsidev->dev), dsi->pdev);
4536 if (r < 0) {
4537 DSSERR("request_irq failed\n");
4538 goto err_get_irq;
4539 }
4540
4541 /* DSI VCs initialization */
4542 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4543 dsi->vc[i].mode = DSI_VC_MODE_L4;
4544 dsi->vc[i].dssdev = NULL;
4545 dsi->vc[i].vc_id = 0;
4546 }
4547
4548 dsi_calc_clock_param_ranges(dsidev);
4549
4550 r = dsi_runtime_get(dsidev);
4551 if (r)
4552 goto err_get_dsi;
4553
4554 rev = dsi_read_reg(dsidev, DSI_REVISION);
4555 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
4556 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4557
4558 dsi->num_data_lanes = dsi_get_num_data_lanes(dsidev);
4559
4560 dsi_runtime_put(dsidev);
4561
4562 return 0;
4563
4564 err_get_dsi:
4565 free_irq(dsi->irq, dsi->pdev);
4566 err_get_irq:
4567 iounmap(dsi->base);
4568 err_ioremap:
4569 pm_runtime_disable(&dsidev->dev);
4570 err_get_clk:
4571 kfree(dsi);
4572 err_alloc:
4573 return r;
4574 }
4575
4576 static int omap_dsi1hw_remove(struct platform_device *dsidev)
4577 {
4578 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4579
4580 WARN_ON(dsi->scp_clk_refcount > 0);
4581
4582 pm_runtime_disable(&dsidev->dev);
4583
4584 dsi_put_clocks(dsidev);
4585
4586 if (dsi->vdds_dsi_reg != NULL) {
4587 if (dsi->vdds_dsi_enabled) {
4588 regulator_disable(dsi->vdds_dsi_reg);
4589 dsi->vdds_dsi_enabled = false;
4590 }
4591
4592 regulator_put(dsi->vdds_dsi_reg);
4593 dsi->vdds_dsi_reg = NULL;
4594 }
4595
4596 free_irq(dsi->irq, dsi->pdev);
4597 iounmap(dsi->base);
4598
4599 kfree(dsi);
4600
4601 return 0;
4602 }
4603
4604 static int dsi_runtime_suspend(struct device *dev)
4605 {
4606 struct dsi_data *dsi = dsi_get_dsidrv_data(to_platform_device(dev));
4607
4608 clk_disable(dsi->dss_clk);
4609
4610 dispc_runtime_put();
4611 dss_runtime_put();
4612
4613 return 0;
4614 }
4615
4616 static int dsi_runtime_resume(struct device *dev)
4617 {
4618 struct dsi_data *dsi = dsi_get_dsidrv_data(to_platform_device(dev));
4619 int r;
4620
4621 r = dss_runtime_get();
4622 if (r)
4623 goto err_get_dss;
4624
4625 r = dispc_runtime_get();
4626 if (r)
4627 goto err_get_dispc;
4628
4629 clk_enable(dsi->dss_clk);
4630
4631 return 0;
4632
4633 err_get_dispc:
4634 dss_runtime_put();
4635 err_get_dss:
4636 return r;
4637 }
4638
4639 static const struct dev_pm_ops dsi_pm_ops = {
4640 .runtime_suspend = dsi_runtime_suspend,
4641 .runtime_resume = dsi_runtime_resume,
4642 };
4643
4644 static struct platform_driver omap_dsi1hw_driver = {
4645 .probe = omap_dsi1hw_probe,
4646 .remove = omap_dsi1hw_remove,
4647 .driver = {
4648 .name = "omapdss_dsi1",
4649 .owner = THIS_MODULE,
4650 .pm = &dsi_pm_ops,
4651 },
4652 };
4653
4654 int dsi_init_platform_driver(void)
4655 {
4656 return platform_driver_register(&omap_dsi1hw_driver);
4657 }
4658
4659 void dsi_uninit_platform_driver(void)
4660 {
4661 return platform_driver_unregister(&omap_dsi1hw_driver);
4662 }
linux-next