drivers/video/omap2/dss/hdmi.h

   1 /*
   2  * hdmi.h
   3  *
   4  * HDMI driver definition for TI OMAP4 processors.
   5  *
   6  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published by
  10  * the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef _OMAP4_DSS_HDMI_H_
  22 #define _OMAP4_DSS_HDMI_H_
  23
  24 #include <linux/string.h>
  25 #include <video/omapdss.h>
  26
  27 #define HDMI_WP         0x0
  28 #define HDMI_CORE_SYS           0x400
  29 #define HDMI_CORE_AV            0x900
  30 #define HDMI_PLLCTRL            0x200
  31 #define HDMI_PHY                0x300
  32
  33 struct hdmi_reg { u16 idx; };
  34
  35 #define HDMI_REG(idx)                   ((const struct hdmi_reg) { idx })
  36
  37 /* HDMI Wrapper */
  38 #define HDMI_WP_REG(idx)                        HDMI_REG(HDMI_WP + idx)
  39
  40 #define HDMI_WP_REVISION                        HDMI_WP_REG(0x0)
  41 #define HDMI_WP_SYSCONFIG                       HDMI_WP_REG(0x10)
  42 #define HDMI_WP_IRQSTATUS_RAW                   HDMI_WP_REG(0x24)
  43 #define HDMI_WP_IRQSTATUS                       HDMI_WP_REG(0x28)
  44 #define HDMI_WP_PWR_CTRL                        HDMI_WP_REG(0x40)
  45 #define HDMI_WP_IRQENABLE_SET                   HDMI_WP_REG(0x2C)
  46 #define HDMI_WP_VIDEO_CFG                       HDMI_WP_REG(0x50)
  47 #define HDMI_WP_VIDEO_SIZE                      HDMI_WP_REG(0x60)
  48 #define HDMI_WP_VIDEO_TIMING_H                  HDMI_WP_REG(0x68)
  49 #define HDMI_WP_VIDEO_TIMING_V                  HDMI_WP_REG(0x6C)
  50 #define HDMI_WP_WP_CLK                          HDMI_WP_REG(0x70)
  51 #define HDMI_WP_AUDIO_CFG                       HDMI_WP_REG(0x80)
  52 #define HDMI_WP_AUDIO_CFG2                      HDMI_WP_REG(0x84)
  53 #define HDMI_WP_AUDIO_CTRL                      HDMI_WP_REG(0x88)
  54 #define HDMI_WP_AUDIO_DATA                      HDMI_WP_REG(0x8C)
  55
  56 /* HDMI IP Core System */
  57 #define HDMI_CORE_SYS_REG(idx)                  HDMI_REG(HDMI_CORE_SYS + idx)
  58
  59 #define HDMI_CORE_SYS_VND_IDL                   HDMI_CORE_SYS_REG(0x0)
  60 #define HDMI_CORE_SYS_DEV_IDL                   HDMI_CORE_SYS_REG(0x8)
  61 #define HDMI_CORE_SYS_DEV_IDH                   HDMI_CORE_SYS_REG(0xC)
  62 #define HDMI_CORE_SYS_DEV_REV                   HDMI_CORE_SYS_REG(0x10)
  63 #define HDMI_CORE_SYS_SRST                      HDMI_CORE_SYS_REG(0x14)
  64 #define HDMI_CORE_CTRL1                 HDMI_CORE_SYS_REG(0x20)
  65 #define HDMI_CORE_SYS_SYS_STAT                  HDMI_CORE_SYS_REG(0x24)
  66 #define HDMI_CORE_SYS_VID_ACEN                  HDMI_CORE_SYS_REG(0x124)
  67 #define HDMI_CORE_SYS_VID_MODE                  HDMI_CORE_SYS_REG(0x128)
  68 #define HDMI_CORE_SYS_INTR_STATE                HDMI_CORE_SYS_REG(0x1C0)
  69 #define HDMI_CORE_SYS_INTR1                     HDMI_CORE_SYS_REG(0x1C4)
  70 #define HDMI_CORE_SYS_INTR2                     HDMI_CORE_SYS_REG(0x1C8)
  71 #define HDMI_CORE_SYS_INTR3                     HDMI_CORE_SYS_REG(0x1CC)
  72 #define HDMI_CORE_SYS_INTR4                     HDMI_CORE_SYS_REG(0x1D0)
  73 #define HDMI_CORE_SYS_UMASK1                    HDMI_CORE_SYS_REG(0x1D4)
  74 #define HDMI_CORE_SYS_TMDS_CTRL         HDMI_CORE_SYS_REG(0x208)
  75 #define HDMI_CORE_SYS_DE_DLY                    HDMI_CORE_SYS_REG(0xC8)
  76 #define HDMI_CORE_SYS_DE_CTRL                   HDMI_CORE_SYS_REG(0xCC)
  77 #define HDMI_CORE_SYS_DE_TOP                    HDMI_CORE_SYS_REG(0xD0)
  78 #define HDMI_CORE_SYS_DE_CNTL                   HDMI_CORE_SYS_REG(0xD8)
  79 #define HDMI_CORE_SYS_DE_CNTH                   HDMI_CORE_SYS_REG(0xDC)
  80 #define HDMI_CORE_SYS_DE_LINL                   HDMI_CORE_SYS_REG(0xE0)
  81 #define HDMI_CORE_SYS_DE_LINH_1         HDMI_CORE_SYS_REG(0xE4)
  82 #define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1
  83 #define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1
  84 #define HDMI_CORE_CTRL1_BSEL_24BITBUS           0x1
  85 #define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1
  86
  87 /* HDMI DDC E-DID */
  88 #define HDMI_CORE_DDC_CMD                       HDMI_CORE_SYS_REG(0x3CC)
  89 #define HDMI_CORE_DDC_STATUS                    HDMI_CORE_SYS_REG(0x3C8)
  90 #define HDMI_CORE_DDC_ADDR                      HDMI_CORE_SYS_REG(0x3B4)
  91 #define HDMI_CORE_DDC_OFFSET                    HDMI_CORE_SYS_REG(0x3BC)
  92 #define HDMI_CORE_DDC_COUNT1                    HDMI_CORE_SYS_REG(0x3C0)
  93 #define HDMI_CORE_DDC_COUNT2                    HDMI_CORE_SYS_REG(0x3C4)
  94 #define HDMI_CORE_DDC_DATA                      HDMI_CORE_SYS_REG(0x3D0)
  95 #define HDMI_CORE_DDC_SEGM                      HDMI_CORE_SYS_REG(0x3B8)
  96
  97 /* HDMI IP Core Audio Video */
  98 #define HDMI_CORE_AV_REG(idx)                   HDMI_REG(HDMI_CORE_AV + idx)
  99
 100 #define HDMI_CORE_AV_HDMI_CTRL                  HDMI_CORE_AV_REG(0xBC)
 101 #define HDMI_CORE_AV_DPD                        HDMI_CORE_AV_REG(0xF4)
 102 #define HDMI_CORE_AV_PB_CTRL1                   HDMI_CORE_AV_REG(0xF8)
 103 #define HDMI_CORE_AV_PB_CTRL2                   HDMI_CORE_AV_REG(0xFC)
 104 #define HDMI_CORE_AV_AVI_TYPE                   HDMI_CORE_AV_REG(0x100)
 105 #define HDMI_CORE_AV_AVI_VERS                   HDMI_CORE_AV_REG(0x104)
 106 #define HDMI_CORE_AV_AVI_LEN                    HDMI_CORE_AV_REG(0x108)
 107 #define HDMI_CORE_AV_AVI_CHSUM                  HDMI_CORE_AV_REG(0x10C)
 108 #define HDMI_CORE_AV_AVI_DBYTE(n)               HDMI_CORE_AV_REG(n * 4 + 0x110)
 109 #define HDMI_CORE_AV_AVI_DBYTE_NELEMS           HDMI_CORE_AV_REG(15)
 110 #define HDMI_CORE_AV_SPD_DBYTE                  HDMI_CORE_AV_REG(0x190)
 111 #define HDMI_CORE_AV_SPD_DBYTE_NELEMS           HDMI_CORE_AV_REG(27)
 112 #define HDMI_CORE_AV_AUD_DBYTE(n)               HDMI_CORE_AV_REG(n * 4 + 0x210)
 113 #define HDMI_CORE_AV_AUD_DBYTE_NELEMS           HDMI_CORE_AV_REG(10)
 114 #define HDMI_CORE_AV_MPEG_DBYTE         HDMI_CORE_AV_REG(0x290)
 115 #define HDMI_CORE_AV_MPEG_DBYTE_NELEMS          HDMI_CORE_AV_REG(27)
 116 #define HDMI_CORE_AV_GEN_DBYTE                  HDMI_CORE_AV_REG(0x300)
 117 #define HDMI_CORE_AV_GEN_DBYTE_NELEMS           HDMI_CORE_AV_REG(31)
 118 #define HDMI_CORE_AV_GEN2_DBYTE         HDMI_CORE_AV_REG(0x380)
 119 #define HDMI_CORE_AV_GEN2_DBYTE_NELEMS          HDMI_CORE_AV_REG(31)
 120 #define HDMI_CORE_AV_ACR_CTRL                   HDMI_CORE_AV_REG(0x4)
 121 #define HDMI_CORE_AV_FREQ_SVAL                  HDMI_CORE_AV_REG(0x8)
 122 #define HDMI_CORE_AV_N_SVAL1                    HDMI_CORE_AV_REG(0xC)
 123 #define HDMI_CORE_AV_N_SVAL2                    HDMI_CORE_AV_REG(0x10)
 124 #define HDMI_CORE_AV_N_SVAL3                    HDMI_CORE_AV_REG(0x14)
 125 #define HDMI_CORE_AV_CTS_SVAL1                  HDMI_CORE_AV_REG(0x18)
 126 #define HDMI_CORE_AV_CTS_SVAL2                  HDMI_CORE_AV_REG(0x1C)
 127 #define HDMI_CORE_AV_CTS_SVAL3                  HDMI_CORE_AV_REG(0x20)
 128 #define HDMI_CORE_AV_CTS_HVAL1                  HDMI_CORE_AV_REG(0x24)
 129 #define HDMI_CORE_AV_CTS_HVAL2                  HDMI_CORE_AV_REG(0x28)
 130 #define HDMI_CORE_AV_CTS_HVAL3                  HDMI_CORE_AV_REG(0x2C)
 131 #define HDMI_CORE_AV_AUD_MODE                   HDMI_CORE_AV_REG(0x50)
 132 #define HDMI_CORE_AV_SPDIF_CTRL         HDMI_CORE_AV_REG(0x54)
 133 #define HDMI_CORE_AV_HW_SPDIF_FS                HDMI_CORE_AV_REG(0x60)
 134 #define HDMI_CORE_AV_SWAP_I2S                   HDMI_CORE_AV_REG(0x64)
 135 #define HDMI_CORE_AV_SPDIF_ERTH         HDMI_CORE_AV_REG(0x6C)
 136 #define HDMI_CORE_AV_I2S_IN_MAP         HDMI_CORE_AV_REG(0x70)
 137 #define HDMI_CORE_AV_I2S_IN_CTRL                HDMI_CORE_AV_REG(0x74)
 138 #define HDMI_CORE_AV_I2S_CHST0                  HDMI_CORE_AV_REG(0x78)
 139 #define HDMI_CORE_AV_I2S_CHST1                  HDMI_CORE_AV_REG(0x7C)
 140 #define HDMI_CORE_AV_I2S_CHST2                  HDMI_CORE_AV_REG(0x80)
 141 #define HDMI_CORE_AV_I2S_CHST4                  HDMI_CORE_AV_REG(0x84)
 142 #define HDMI_CORE_AV_I2S_CHST5                  HDMI_CORE_AV_REG(0x88)
 143 #define HDMI_CORE_AV_ASRC                       HDMI_CORE_AV_REG(0x8C)
 144 #define HDMI_CORE_AV_I2S_IN_LEN         HDMI_CORE_AV_REG(0x90)
 145 #define HDMI_CORE_AV_HDMI_CTRL                  HDMI_CORE_AV_REG(0xBC)
 146 #define HDMI_CORE_AV_AUDO_TXSTAT                HDMI_CORE_AV_REG(0xC0)
 147 #define HDMI_CORE_AV_AUD_PAR_BUSCLK_1           HDMI_CORE_AV_REG(0xCC)
 148 #define HDMI_CORE_AV_AUD_PAR_BUSCLK_2           HDMI_CORE_AV_REG(0xD0)
 149 #define HDMI_CORE_AV_AUD_PAR_BUSCLK_3           HDMI_CORE_AV_REG(0xD4)
 150 #define HDMI_CORE_AV_TEST_TXCTRL                HDMI_CORE_AV_REG(0xF0)
 151 #define HDMI_CORE_AV_DPD                        HDMI_CORE_AV_REG(0xF4)
 152 #define HDMI_CORE_AV_PB_CTRL1                   HDMI_CORE_AV_REG(0xF8)
 153 #define HDMI_CORE_AV_PB_CTRL2                   HDMI_CORE_AV_REG(0xFC)
 154 #define HDMI_CORE_AV_AVI_TYPE                   HDMI_CORE_AV_REG(0x100)
 155 #define HDMI_CORE_AV_AVI_VERS                   HDMI_CORE_AV_REG(0x104)
 156 #define HDMI_CORE_AV_AVI_LEN                    HDMI_CORE_AV_REG(0x108)
 157 #define HDMI_CORE_AV_AVI_CHSUM                  HDMI_CORE_AV_REG(0x10C)
 158 #define HDMI_CORE_AV_SPD_TYPE                   HDMI_CORE_AV_REG(0x180)
 159 #define HDMI_CORE_AV_SPD_VERS                   HDMI_CORE_AV_REG(0x184)
 160 #define HDMI_CORE_AV_SPD_LEN                    HDMI_CORE_AV_REG(0x188)
 161 #define HDMI_CORE_AV_SPD_CHSUM                  HDMI_CORE_AV_REG(0x18C)
 162 #define HDMI_CORE_AV_AUDIO_TYPE         HDMI_CORE_AV_REG(0x200)
 163 #define HDMI_CORE_AV_AUDIO_VERS         HDMI_CORE_AV_REG(0x204)
 164 #define HDMI_CORE_AV_AUDIO_LEN                  HDMI_CORE_AV_REG(0x208)
 165 #define HDMI_CORE_AV_AUDIO_CHSUM                HDMI_CORE_AV_REG(0x20C)
 166 #define HDMI_CORE_AV_MPEG_TYPE                  HDMI_CORE_AV_REG(0x280)
 167 #define HDMI_CORE_AV_MPEG_VERS                  HDMI_CORE_AV_REG(0x284)
 168 #define HDMI_CORE_AV_MPEG_LEN                   HDMI_CORE_AV_REG(0x288)
 169 #define HDMI_CORE_AV_MPEG_CHSUM         HDMI_CORE_AV_REG(0x28C)
 170 #define HDMI_CORE_AV_CP_BYTE1                   HDMI_CORE_AV_REG(0x37C)
 171 #define HDMI_CORE_AV_CEC_ADDR_ID                HDMI_CORE_AV_REG(0x3FC)
 172 #define HDMI_CORE_AV_SPD_DBYTE_ELSIZE           0x4
 173 #define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE          0x4
 174 #define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE          0x4
 175 #define HDMI_CORE_AV_GEN_DBYTE_ELSIZE           0x4
 176
 177 /* PLL */
 178 #define HDMI_PLL_REG(idx)                       HDMI_REG(HDMI_PLLCTRL + idx)
 179
 180 #define PLLCTRL_PLL_CONTROL                     HDMI_PLL_REG(0x0)
 181 #define PLLCTRL_PLL_STATUS                      HDMI_PLL_REG(0x4)
 182 #define PLLCTRL_PLL_GO                          HDMI_PLL_REG(0x8)
 183 #define PLLCTRL_CFG1                            HDMI_PLL_REG(0xC)
 184 #define PLLCTRL_CFG2                            HDMI_PLL_REG(0x10)
 185 #define PLLCTRL_CFG3                            HDMI_PLL_REG(0x14)
 186 #define PLLCTRL_CFG4                            HDMI_PLL_REG(0x20)
 187
 188 /* HDMI PHY */
 189 #define HDMI_PHY_REG(idx)                       HDMI_REG(HDMI_PHY + idx)
 190
 191 #define HDMI_TXPHY_TX_CTRL                      HDMI_PHY_REG(0x0)
 192 #define HDMI_TXPHY_DIGITAL_CTRL         HDMI_PHY_REG(0x4)
 193 #define HDMI_TXPHY_POWER_CTRL                   HDMI_PHY_REG(0x8)
 194 #define HDMI_TXPHY_PAD_CFG_CTRL         HDMI_PHY_REG(0xC)
 195
 196 /* HDMI EDID Length  */
 197 #define HDMI_EDID_MAX_LENGTH                    256
 198 #define EDID_TIMING_DESCRIPTOR_SIZE             0x12
 199 #define EDID_DESCRIPTOR_BLOCK0_ADDRESS          0x36
 200 #define EDID_DESCRIPTOR_BLOCK1_ADDRESS          0x80
 201 #define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR      4
 202 #define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR      4
 203
 204 #define OMAP_HDMI_TIMINGS_NB                    34
 205
 206 #define REG_FLD_MOD(idx, val, start, end) \
 207         hdmi_write_reg(idx, FLD_MOD(hdmi_read_reg(idx), val, start, end))
 208 #define REG_GET(idx, start, end) \
 209         FLD_GET(hdmi_read_reg(idx), start, end)
 210
 211 /* HDMI timing structure */
 212 struct hdmi_timings {
 213         struct omap_video_timings timings;
 214         int vsync_pol;
 215         int hsync_pol;
 216 };
 217
 218 enum hdmi_phy_pwr {
 219         HDMI_PHYPWRCMD_OFF = 0,
 220         HDMI_PHYPWRCMD_LDOON = 1,
 221         HDMI_PHYPWRCMD_TXON = 2
 222 };
 223
 224 enum hdmi_pll_pwr {
 225         HDMI_PLLPWRCMD_ALLOFF = 0,
 226         HDMI_PLLPWRCMD_PLLONLY = 1,
 227         HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
 228         HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
 229 };
 230
 231 enum hdmi_clk_refsel {
 232         HDMI_REFSEL_PCLK = 0,
 233         HDMI_REFSEL_REF1 = 1,
 234         HDMI_REFSEL_REF2 = 2,
 235         HDMI_REFSEL_SYSCLK = 3
 236 };
 237
 238 enum hdmi_core_inputbus_width {
 239         HDMI_INPUT_8BIT = 0,
 240         HDMI_INPUT_10BIT = 1,
 241         HDMI_INPUT_12BIT = 2
 242 };
 243
 244 enum hdmi_core_dither_trunc {
 245         HDMI_OUTPUTTRUNCATION_8BIT = 0,
 246         HDMI_OUTPUTTRUNCATION_10BIT = 1,
 247         HDMI_OUTPUTTRUNCATION_12BIT = 2,
 248         HDMI_OUTPUTDITHER_8BIT = 3,
 249         HDMI_OUTPUTDITHER_10BIT = 4,
 250         HDMI_OUTPUTDITHER_12BIT = 5
 251 };
 252
 253 enum hdmi_core_deepcolor_ed {
 254         HDMI_DEEPCOLORPACKECTDISABLE = 0,
 255         HDMI_DEEPCOLORPACKECTENABLE = 1
 256 };
 257
 258 enum hdmi_core_packet_mode {
 259         HDMI_PACKETMODERESERVEDVALUE = 0,
 260         HDMI_PACKETMODE24BITPERPIXEL = 4,
 261         HDMI_PACKETMODE30BITPERPIXEL = 5,
 262         HDMI_PACKETMODE36BITPERPIXEL = 6,
 263         HDMI_PACKETMODE48BITPERPIXEL = 7
 264 };
 265
 266 enum hdmi_core_hdmi_dvi {
 267         HDMI_DVI = 0,
 268         HDMI_HDMI = 1
 269 };
 270
 271 enum hdmi_core_tclkselclkmult {
 272         HDMI_FPLL05IDCK = 0,
 273         HDMI_FPLL10IDCK = 1,
 274         HDMI_FPLL20IDCK = 2,
 275         HDMI_FPLL40IDCK = 3
 276 };
 277
 278 enum hdmi_core_packet_ctrl {
 279         HDMI_PACKETENABLE = 1,
 280         HDMI_PACKETDISABLE = 0,
 281         HDMI_PACKETREPEATON = 1,
 282         HDMI_PACKETREPEATOFF = 0
 283 };
 284
 285 /* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */
 286 enum hdmi_core_infoframe {
 287         HDMI_INFOFRAME_AVI_DB1Y_RGB = 0,
 288         HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1,
 289         HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2,
 290         HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,
 291         HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON =  1,
 292         HDMI_INFOFRAME_AVI_DB1B_NO = 0,
 293         HDMI_INFOFRAME_AVI_DB1B_VERT = 1,
 294         HDMI_INFOFRAME_AVI_DB1B_HORI = 2,
 295         HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3,
 296         HDMI_INFOFRAME_AVI_DB1S_0 = 0,
 297         HDMI_INFOFRAME_AVI_DB1S_1 = 1,
 298         HDMI_INFOFRAME_AVI_DB1S_2 = 2,
 299         HDMI_INFOFRAME_AVI_DB2C_NO = 0,
 300         HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1,
 301         HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2,
 302         HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,
 303         HDMI_INFOFRAME_AVI_DB2M_NO = 0,
 304         HDMI_INFOFRAME_AVI_DB2M_43 = 1,
 305         HDMI_INFOFRAME_AVI_DB2M_169 = 2,
 306         HDMI_INFOFRAME_AVI_DB2R_SAME = 8,
 307         HDMI_INFOFRAME_AVI_DB2R_43 = 9,
 308         HDMI_INFOFRAME_AVI_DB2R_169 = 10,
 309         HDMI_INFOFRAME_AVI_DB2R_149 = 11,
 310         HDMI_INFOFRAME_AVI_DB3ITC_NO = 0,
 311         HDMI_INFOFRAME_AVI_DB3ITC_YES = 1,
 312         HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0,
 313         HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1,
 314         HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0,
 315         HDMI_INFOFRAME_AVI_DB3Q_LR = 1,
 316         HDMI_INFOFRAME_AVI_DB3Q_FR = 2,
 317         HDMI_INFOFRAME_AVI_DB3SC_NO = 0,
 318         HDMI_INFOFRAME_AVI_DB3SC_HORI = 1,
 319         HDMI_INFOFRAME_AVI_DB3SC_VERT = 2,
 320         HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3,
 321         HDMI_INFOFRAME_AVI_DB5PR_NO = 0,
 322         HDMI_INFOFRAME_AVI_DB5PR_2 = 1,
 323         HDMI_INFOFRAME_AVI_DB5PR_3 = 2,
 324         HDMI_INFOFRAME_AVI_DB5PR_4 = 3,
 325         HDMI_INFOFRAME_AVI_DB5PR_5 = 4,
 326         HDMI_INFOFRAME_AVI_DB5PR_6 = 5,
 327         HDMI_INFOFRAME_AVI_DB5PR_7 = 6,
 328         HDMI_INFOFRAME_AVI_DB5PR_8 = 7,
 329         HDMI_INFOFRAME_AVI_DB5PR_9 = 8,
 330         HDMI_INFOFRAME_AVI_DB5PR_10 = 9,
 331         HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM = 0,
 332         HDMI_INFOFRAME_AUDIO_DB1CT_IEC60958 = 1,
 333         HDMI_INFOFRAME_AUDIO_DB1CT_AC3 = 2,
 334         HDMI_INFOFRAME_AUDIO_DB1CT_MPEG1 = 3,
 335         HDMI_INFOFRAME_AUDIO_DB1CT_MP3 = 4,
 336         HDMI_INFOFRAME_AUDIO_DB1CT_MPEG2_MULTICH = 5,
 337         HDMI_INFOFRAME_AUDIO_DB1CT_AAC = 6,
 338         HDMI_INFOFRAME_AUDIO_DB1CT_DTS = 7,
 339         HDMI_INFOFRAME_AUDIO_DB1CT_ATRAC = 8,
 340         HDMI_INFOFRAME_AUDIO_DB1CT_ONEBIT = 9,
 341         HDMI_INFOFRAME_AUDIO_DB1CT_DOLBY_DIGITAL_PLUS = 10,
 342         HDMI_INFOFRAME_AUDIO_DB1CT_DTS_HD = 11,
 343         HDMI_INFOFRAME_AUDIO_DB1CT_MAT = 12,
 344         HDMI_INFOFRAME_AUDIO_DB1CT_DST = 13,
 345         HDMI_INFOFRAME_AUDIO_DB1CT_WMA_PRO = 14,
 346         HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM = 0,
 347         HDMI_INFOFRAME_AUDIO_DB2SF_32000 = 1,
 348         HDMI_INFOFRAME_AUDIO_DB2SF_44100 = 2,
 349         HDMI_INFOFRAME_AUDIO_DB2SF_48000 = 3,
 350         HDMI_INFOFRAME_AUDIO_DB2SF_88200 = 4,
 351         HDMI_INFOFRAME_AUDIO_DB2SF_96000 = 5,
 352         HDMI_INFOFRAME_AUDIO_DB2SF_176400 = 6,
 353         HDMI_INFOFRAME_AUDIO_DB2SF_192000 = 7,
 354         HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM = 0,
 355         HDMI_INFOFRAME_AUDIO_DB2SS_16BIT = 1,
 356         HDMI_INFOFRAME_AUDIO_DB2SS_20BIT = 2,
 357         HDMI_INFOFRAME_AUDIO_DB2SS_24BIT = 3,
 358         HDMI_INFOFRAME_AUDIO_DB5_DM_INH_PERMITTED = 0,
 359         HDMI_INFOFRAME_AUDIO_DB5_DM_INH_PROHIBITED = 1
 360 };
 361
 362 enum hdmi_packing_mode {
 363         HDMI_PACK_10b_RGB_YUV444 = 0,
 364         HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
 365         HDMI_PACK_20b_YUV422 = 2,
 366         HDMI_PACK_ALREADYPACKED = 7
 367 };
 368
 369 enum hdmi_core_audio_sample_freq {
 370         HDMI_AUDIO_FS_32000 = 0x3,
 371         HDMI_AUDIO_FS_44100 = 0x0,
 372         HDMI_AUDIO_FS_48000 = 0x2,
 373         HDMI_AUDIO_FS_88200 = 0x8,
 374         HDMI_AUDIO_FS_96000 = 0xA,
 375         HDMI_AUDIO_FS_176400 = 0xC,
 376         HDMI_AUDIO_FS_192000 = 0xE,
 377         HDMI_AUDIO_FS_NOT_INDICATED = 0x1
 378 };
 379
 380 enum hdmi_core_audio_layout {
 381         HDMI_AUDIO_LAYOUT_2CH = 0,
 382         HDMI_AUDIO_LAYOUT_8CH = 1
 383 };
 384
 385 enum hdmi_core_cts_mode {
 386         HDMI_AUDIO_CTS_MODE_HW = 0,
 387         HDMI_AUDIO_CTS_MODE_SW = 1
 388 };
 389
 390 enum hdmi_stereo_channels {
 391         HDMI_AUDIO_STEREO_NOCHANNELS = 0,
 392         HDMI_AUDIO_STEREO_ONECHANNEL = 1,
 393         HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
 394         HDMI_AUDIO_STEREO_THREECHANNELS = 3,
 395         HDMI_AUDIO_STEREO_FOURCHANNELS = 4
 396 };
 397
 398 enum hdmi_audio_type {
 399         HDMI_AUDIO_TYPE_LPCM = 0,
 400         HDMI_AUDIO_TYPE_IEC = 1
 401 };
 402
 403 enum hdmi_audio_justify {
 404         HDMI_AUDIO_JUSTIFY_LEFT = 0,
 405         HDMI_AUDIO_JUSTIFY_RIGHT = 1
 406 };
 407
 408 enum hdmi_audio_sample_order {
 409         HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
 410         HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
 411 };
 412
 413 enum hdmi_audio_samples_perword {
 414         HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
 415         HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
 416 };
 417
 418 enum hdmi_audio_sample_size {
 419         HDMI_AUDIO_SAMPLE_16BITS = 0,
 420         HDMI_AUDIO_SAMPLE_24BITS = 1
 421 };
 422
 423 enum hdmi_audio_transf_mode {
 424         HDMI_AUDIO_TRANSF_DMA = 0,
 425         HDMI_AUDIO_TRANSF_IRQ = 1
 426 };
 427
 428 enum hdmi_audio_blk_strt_end_sig {
 429         HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
 430         HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
 431 };
 432
 433 enum hdmi_audio_i2s_config {
 434         HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT = 0,
 435         HDMI_AUDIO_I2S_WS_POLARIT_YLOW_IS_RIGHT = 1,
 436         HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST = 0,
 437         HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST = 1,
 438         HDMI_AUDIO_I2S_MAX_WORD_20BITS = 0,
 439         HDMI_AUDIO_I2S_MAX_WORD_24BITS = 1,
 440         HDMI_AUDIO_I2S_CHST_WORD_NOT_SPECIFIED = 0,
 441         HDMI_AUDIO_I2S_CHST_WORD_16_BITS = 1,
 442         HDMI_AUDIO_I2S_CHST_WORD_17_BITS = 6,
 443         HDMI_AUDIO_I2S_CHST_WORD_18_BITS = 2,
 444         HDMI_AUDIO_I2S_CHST_WORD_19_BITS = 4,
 445         HDMI_AUDIO_I2S_CHST_WORD_20_BITS_20MAX = 5,
 446         HDMI_AUDIO_I2S_CHST_WORD_20_BITS_24MAX = 1,
 447         HDMI_AUDIO_I2S_CHST_WORD_21_BITS = 6,
 448         HDMI_AUDIO_I2S_CHST_WORD_22_BITS = 2,
 449         HDMI_AUDIO_I2S_CHST_WORD_23_BITS = 4,
 450         HDMI_AUDIO_I2S_CHST_WORD_24_BITS = 5,
 451         HDMI_AUDIO_I2S_SCK_EDGE_FALLING = 0,
 452         HDMI_AUDIO_I2S_SCK_EDGE_RISING = 1,
 453         HDMI_AUDIO_I2S_VBIT_FOR_PCM = 0,
 454         HDMI_AUDIO_I2S_VBIT_FOR_COMPRESSED = 1,
 455         HDMI_AUDIO_I2S_INPUT_LENGTH_NA = 0,
 456         HDMI_AUDIO_I2S_INPUT_LENGTH_16 = 2,
 457         HDMI_AUDIO_I2S_INPUT_LENGTH_17 = 12,
 458         HDMI_AUDIO_I2S_INPUT_LENGTH_18 = 4,
 459         HDMI_AUDIO_I2S_INPUT_LENGTH_19 = 8,
 460         HDMI_AUDIO_I2S_INPUT_LENGTH_20 = 10,
 461         HDMI_AUDIO_I2S_INPUT_LENGTH_21 = 13,
 462         HDMI_AUDIO_I2S_INPUT_LENGTH_22 = 5,
 463         HDMI_AUDIO_I2S_INPUT_LENGTH_23 = 9,
 464         HDMI_AUDIO_I2S_INPUT_LENGTH_24 = 11,
 465         HDMI_AUDIO_I2S_FIRST_BIT_SHIFT = 0,
 466         HDMI_AUDIO_I2S_FIRST_BIT_NO_SHIFT = 1,
 467         HDMI_AUDIO_I2S_SD0_EN = 1,
 468         HDMI_AUDIO_I2S_SD1_EN = 1 << 1,
 469         HDMI_AUDIO_I2S_SD2_EN = 1 << 2,
 470         HDMI_AUDIO_I2S_SD3_EN = 1 << 3,
 471 };
 472
 473 enum hdmi_audio_mclk_mode {
 474         HDMI_AUDIO_MCLK_128FS = 0,
 475         HDMI_AUDIO_MCLK_256FS = 1,
 476         HDMI_AUDIO_MCLK_384FS = 2,
 477         HDMI_AUDIO_MCLK_512FS = 3,
 478         HDMI_AUDIO_MCLK_768FS = 4,
 479         HDMI_AUDIO_MCLK_1024FS = 5,
 480         HDMI_AUDIO_MCLK_1152FS = 6,
 481         HDMI_AUDIO_MCLK_192FS = 7
 482 };
 483
 484 struct hdmi_core_video_config {
 485         enum hdmi_core_inputbus_width   ip_bus_width;
 486         enum hdmi_core_dither_trunc     op_dither_truc;
 487         enum hdmi_core_deepcolor_ed     deep_color_pkt;
 488         enum hdmi_core_packet_mode      pkt_mode;
 489         enum hdmi_core_hdmi_dvi         hdmi_dvi;
 490         enum hdmi_core_tclkselclkmult   tclk_sel_clkmult;
 491 };
 492
 493 /*
 494  * Refer to section 8.2 in HDMI 1.3 specification for
 495  * details about infoframe databytes
 496  */
 497 struct hdmi_core_infoframe_avi {
 498         u8      db1_format;
 499                 /* Y0, Y1 rgb,yCbCr */
 500         u8      db1_active_info;
 501                 /* A0  Active information Present */
 502         u8      db1_bar_info_dv;
 503                 /* B0, B1 Bar info data valid */
 504         u8      db1_scan_info;
 505                 /* S0, S1 scan information */
 506         u8      db2_colorimetry;
 507                 /* C0, C1 colorimetry */
 508         u8      db2_aspect_ratio;
 509                 /* M0, M1 Aspect ratio (4:3, 16:9) */
 510         u8      db2_active_fmt_ar;
 511                 /* R0...R3 Active format aspect ratio */
 512         u8      db3_itc;
 513                 /* ITC IT content. */
 514         u8      db3_ec;
 515                 /* EC0, EC1, EC2 Extended colorimetry */
 516         u8      db3_q_range;
 517                 /* Q1, Q0 Quantization range */
 518         u8      db3_nup_scaling;
 519                 /* SC1, SC0 Non-uniform picture scaling */
 520         u8      db4_videocode;
 521                 /* VIC0..6 Video format identification */
 522         u8      db5_pixel_repeat;
 523                 /* PR0..PR3 Pixel repetition factor */
 524         u16     db6_7_line_eoftop;
 525                 /* Line number end of top bar */
 526         u16     db8_9_line_sofbottom;
 527                 /* Line number start of bottom bar */
 528         u16     db10_11_pixel_eofleft;
 529                 /* Pixel number end of left bar */
 530         u16     db12_13_pixel_sofright;
 531                 /* Pixel number start of right bar */
 532 };
 533 /*
 534  * Refer to section 8.2 in HDMI 1.3 specification for
 535  * details about infoframe databytes
 536  */
 537 struct hdmi_core_infoframe_audio {
 538         u8 db1_coding_type;
 539         u8 db1_channel_count;
 540         u8 db2_sample_freq;
 541         u8 db2_sample_size;
 542         u8 db4_channel_alloc;
 543         bool db5_downmix_inh;
 544         u8 db5_lsv;     /* Level shift values for downmix */
 545 };
 546
 547 struct hdmi_core_packet_enable_repeat {
 548         u32     audio_pkt;
 549         u32     audio_pkt_repeat;
 550         u32     avi_infoframe;
 551         u32     avi_infoframe_repeat;
 552         u32     gen_cntrl_pkt;
 553         u32     gen_cntrl_pkt_repeat;
 554         u32     generic_pkt;
 555         u32     generic_pkt_repeat;
 556 };
 557
 558 struct hdmi_video_format {
 559         enum hdmi_packing_mode  packing_mode;
 560         u32                     y_res;  /* Line per panel */
 561         u32                     x_res;  /* pixel per line */
 562 };
 563
 564 struct hdmi_video_interface {
 565         int     vsp;    /* Vsync polarity */
 566         int     hsp;    /* Hsync polarity */
 567         int     interlacing;
 568         int     tm;     /* Timing mode */
 569 };
 570
 571 struct hdmi_cm {
 572         int     code;
 573         int     mode;
 574 };
 575
 576 struct hdmi_config {
 577         struct hdmi_timings timings;
 578         u16     interlace;
 579         struct hdmi_cm cm;
 580 };
 581
 582 struct hdmi_audio_format {
 583         enum hdmi_stereo_channels               stereo_channels;
 584         u8                                      active_chnnls_msk;
 585         enum hdmi_audio_type                    type;
 586         enum hdmi_audio_justify                 justification;
 587         enum hdmi_audio_sample_order            sample_order;
 588         enum hdmi_audio_samples_perword         samples_per_word;
 589         enum hdmi_audio_sample_size             sample_size;
 590         enum hdmi_audio_blk_strt_end_sig        en_sig_blk_strt_end;
 591 };
 592
 593 struct hdmi_audio_dma {
 594         u8                              transfer_size;
 595         u8                              block_size;
 596         enum hdmi_audio_transf_mode     mode;
 597         u16                             fifo_threshold;
 598 };
 599
 600 struct hdmi_core_audio_i2s_config {
 601         u8 word_max_length;
 602         u8 word_length;
 603         u8 in_length_bits;
 604         u8 justification;
 605         u8 en_high_bitrate_aud;
 606         u8 sck_edge_mode;
 607         u8 cbit_order;
 608         u8 vbit;
 609         u8 ws_polarity;
 610         u8 direction;
 611         u8 shift;
 612         u8 active_sds;
 613 };
 614
 615 struct hdmi_core_audio_config {
 616         struct hdmi_core_audio_i2s_config       i2s_cfg;
 617         enum hdmi_core_audio_sample_freq        freq_sample;
 618         bool                                    fs_override;
 619         u32                                     n;
 620         u32                                     cts;
 621         u32                                     aud_par_busclk;
 622         enum hdmi_core_audio_layout             layout;
 623         enum hdmi_core_cts_mode                 cts_mode;
 624         bool                                    use_mclk;
 625         enum hdmi_audio_mclk_mode               mclk_mode;
 626         bool                                    en_acr_pkt;
 627         bool                                    en_dsd_audio;
 628         bool                                    en_parallel_aud_input;
 629         bool                                    en_spdif;
 630 };
 631 #endif