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Merge remote-tracking branch 'moduleh/module.h-split'
[linux-2.6/next.git] / sound / soc / codecs / wm8994.c
blobe5372675123d32ea070b3edc91a2a8fd0e626cfd
1 /*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
32
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
37
38 #include "wm8994.h"
39 #include "wm_hubs.h"
40
41 #define WM8994_NUM_DRC 3
42 #define WM8994_NUM_EQ 3
43
44 static int wm8994_drc_base[] = {
45 WM8994_AIF1_DRC1_1,
46 WM8994_AIF1_DRC2_1,
47 WM8994_AIF2_DRC_1,
48 };
49
50 static int wm8994_retune_mobile_base[] = {
51 WM8994_AIF1_DAC1_EQ_GAINS_1,
52 WM8994_AIF1_DAC2_EQ_GAINS_1,
53 WM8994_AIF2_EQ_GAINS_1,
54 };
55
56 static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
57 {
58 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
59 struct wm8994 *control = wm8994->control_data;
60
61 switch (reg) {
62 case WM8994_GPIO_1:
63 case WM8994_GPIO_2:
64 case WM8994_GPIO_3:
65 case WM8994_GPIO_4:
66 case WM8994_GPIO_5:
67 case WM8994_GPIO_6:
68 case WM8994_GPIO_7:
69 case WM8994_GPIO_8:
70 case WM8994_GPIO_9:
71 case WM8994_GPIO_10:
72 case WM8994_GPIO_11:
73 case WM8994_INTERRUPT_STATUS_1:
74 case WM8994_INTERRUPT_STATUS_2:
75 case WM8994_INTERRUPT_RAW_STATUS_2:
76 return 1;
77
78 case WM8958_DSP2_PROGRAM:
79 case WM8958_DSP2_CONFIG:
80 case WM8958_DSP2_EXECCONTROL:
81 if (control->type == WM8958)
82 return 1;
83 else
84 return 0;
85
86 default:
87 break;
88 }
89
90 if (reg >= WM8994_CACHE_SIZE)
91 return 0;
92 return wm8994_access_masks[reg].readable != 0;
93 }
94
95 static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
96 {
97 if (reg >= WM8994_CACHE_SIZE)
98 return 1;
99
100 switch (reg) {
101 case WM8994_SOFTWARE_RESET:
102 case WM8994_CHIP_REVISION:
103 case WM8994_DC_SERVO_1:
104 case WM8994_DC_SERVO_READBACK:
105 case WM8994_RATE_STATUS:
106 case WM8994_LDO_1:
107 case WM8994_LDO_2:
108 case WM8958_DSP2_EXECCONTROL:
109 case WM8958_MIC_DETECT_3:
110 case WM8994_DC_SERVO_4E:
111 return 1;
112 default:
113 return 0;
114 }
115 }
116
117 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
118 unsigned int value)
119 {
120 int ret;
121
122 BUG_ON(reg > WM8994_MAX_REGISTER);
123
124 if (!wm8994_volatile(codec, reg)) {
125 ret = snd_soc_cache_write(codec, reg, value);
126 if (ret != 0)
127 dev_err(codec->dev, "Cache write to %x failed: %d\n",
128 reg, ret);
129 }
130
131 return wm8994_reg_write(codec->control_data, reg, value);
132 }
133
134 static unsigned int wm8994_read(struct snd_soc_codec *codec,
135 unsigned int reg)
136 {
137 unsigned int val;
138 int ret;
139
140 BUG_ON(reg > WM8994_MAX_REGISTER);
141
142 if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
143 reg < codec->driver->reg_cache_size) {
144 ret = snd_soc_cache_read(codec, reg, &val);
145 if (ret >= 0)
146 return val;
147 else
148 dev_err(codec->dev, "Cache read from %x failed: %d\n",
149 reg, ret);
150 }
151
152 return wm8994_reg_read(codec->control_data, reg);
153 }
154
155 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
156 {
157 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
158 int rate;
159 int reg1 = 0;
160 int offset;
161
162 if (aif)
163 offset = 4;
164 else
165 offset = 0;
166
167 switch (wm8994->sysclk[aif]) {
168 case WM8994_SYSCLK_MCLK1:
169 rate = wm8994->mclk[0];
170 break;
171
172 case WM8994_SYSCLK_MCLK2:
173 reg1 |= 0x8;
174 rate = wm8994->mclk[1];
175 break;
176
177 case WM8994_SYSCLK_FLL1:
178 reg1 |= 0x10;
179 rate = wm8994->fll[0].out;
180 break;
181
182 case WM8994_SYSCLK_FLL2:
183 reg1 |= 0x18;
184 rate = wm8994->fll[1].out;
185 break;
186
187 default:
188 return -EINVAL;
189 }
190
191 if (rate >= 13500000) {
192 rate /= 2;
193 reg1 |= WM8994_AIF1CLK_DIV;
194
195 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
196 aif + 1, rate);
197 }
198
199 wm8994->aifclk[aif] = rate;
200
201 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
202 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
203 reg1);
204
205 return 0;
206 }
207
208 static int configure_clock(struct snd_soc_codec *codec)
209 {
210 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
211 int old, new;
212
213 /* Bring up the AIF clocks first */
214 configure_aif_clock(codec, 0);
215 configure_aif_clock(codec, 1);
216
217 /* Then switch CLK_SYS over to the higher of them; a change
218 * can only happen as a result of a clocking change which can
219 * only be made outside of DAPM so we can safely redo the
220 * clocking.
221 */
222
223 /* If they're equal it doesn't matter which is used */
224 if (wm8994->aifclk[0] == wm8994->aifclk[1])
225 return 0;
226
227 if (wm8994->aifclk[0] < wm8994->aifclk[1])
228 new = WM8994_SYSCLK_SRC;
229 else
230 new = 0;
231
232 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
233
234 /* If there's no change then we're done. */
235 if (old == new)
236 return 0;
237
238 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
239
240 snd_soc_dapm_sync(&codec->dapm);
241
242 return 0;
243 }
244
245 static int check_clk_sys(struct snd_soc_dapm_widget *source,
246 struct snd_soc_dapm_widget *sink)
247 {
248 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
249 const char *clk;
250
251 /* Check what we're currently using for CLK_SYS */
252 if (reg & WM8994_SYSCLK_SRC)
253 clk = "AIF2CLK";
254 else
255 clk = "AIF1CLK";
256
257 return strcmp(source->name, clk) == 0;
258 }
259
260 static const char *sidetone_hpf_text[] = {
261 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
262 };
263
264 static const struct soc_enum sidetone_hpf =
265 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
266
267 static const char *adc_hpf_text[] = {
268 "HiFi", "Voice 1", "Voice 2", "Voice 3"
269 };
270
271 static const struct soc_enum aif1adc1_hpf =
272 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
273
274 static const struct soc_enum aif1adc2_hpf =
275 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
276
277 static const struct soc_enum aif2adc_hpf =
278 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
279
280 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
281 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
282 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
283 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
284 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
285 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
286
287 #define WM8994_DRC_SWITCH(xname, reg, shift) \
288 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
289 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
290 .put = wm8994_put_drc_sw, \
291 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
292
293 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
294 struct snd_ctl_elem_value *ucontrol)
295 {
296 struct soc_mixer_control *mc =
297 (struct soc_mixer_control *)kcontrol->private_value;
298 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
299 int mask, ret;
300
301 /* Can't enable both ADC and DAC paths simultaneously */
302 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
303 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
304 WM8994_AIF1ADC1R_DRC_ENA_MASK;
305 else
306 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
307
308 ret = snd_soc_read(codec, mc->reg);
309 if (ret < 0)
310 return ret;
311 if (ret & mask)
312 return -EINVAL;
313
314 return snd_soc_put_volsw(kcontrol, ucontrol);
315 }
316
317 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
318 {
319 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
320 struct wm8994_pdata *pdata = wm8994->pdata;
321 int base = wm8994_drc_base[drc];
322 int cfg = wm8994->drc_cfg[drc];
323 int save, i;
324
325 /* Save any enables; the configuration should clear them. */
326 save = snd_soc_read(codec, base);
327 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
328 WM8994_AIF1ADC1R_DRC_ENA;
329
330 for (i = 0; i < WM8994_DRC_REGS; i++)
331 snd_soc_update_bits(codec, base + i, 0xffff,
332 pdata->drc_cfgs[cfg].regs[i]);
333
334 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
335 WM8994_AIF1ADC1L_DRC_ENA |
336 WM8994_AIF1ADC1R_DRC_ENA, save);
337 }
338
339 /* Icky as hell but saves code duplication */
340 static int wm8994_get_drc(const char *name)
341 {
342 if (strcmp(name, "AIF1DRC1 Mode") == 0)
343 return 0;
344 if (strcmp(name, "AIF1DRC2 Mode") == 0)
345 return 1;
346 if (strcmp(name, "AIF2DRC Mode") == 0)
347 return 2;
348 return -EINVAL;
349 }
350
351 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
352 struct snd_ctl_elem_value *ucontrol)
353 {
354 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
355 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
356 struct wm8994_pdata *pdata = wm8994->pdata;
357 int drc = wm8994_get_drc(kcontrol->id.name);
358 int value = ucontrol->value.integer.value[0];
359
360 if (drc < 0)
361 return drc;
362
363 if (value >= pdata->num_drc_cfgs)
364 return -EINVAL;
365
366 wm8994->drc_cfg[drc] = value;
367
368 wm8994_set_drc(codec, drc);
369
370 return 0;
371 }
372
373 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
374 struct snd_ctl_elem_value *ucontrol)
375 {
376 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
377 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
378 int drc = wm8994_get_drc(kcontrol->id.name);
379
380 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
381
382 return 0;
383 }
384
385 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
386 {
387 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
388 struct wm8994_pdata *pdata = wm8994->pdata;
389 int base = wm8994_retune_mobile_base[block];
390 int iface, best, best_val, save, i, cfg;
391
392 if (!pdata || !wm8994->num_retune_mobile_texts)
393 return;
394
395 switch (block) {
396 case 0:
397 case 1:
398 iface = 0;
399 break;
400 case 2:
401 iface = 1;
402 break;
403 default:
404 return;
405 }
406
407 /* Find the version of the currently selected configuration
408 * with the nearest sample rate. */
409 cfg = wm8994->retune_mobile_cfg[block];
410 best = 0;
411 best_val = INT_MAX;
412 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
413 if (strcmp(pdata->retune_mobile_cfgs[i].name,
414 wm8994->retune_mobile_texts[cfg]) == 0 &&
415 abs(pdata->retune_mobile_cfgs[i].rate
416 - wm8994->dac_rates[iface]) < best_val) {
417 best = i;
418 best_val = abs(pdata->retune_mobile_cfgs[i].rate
419 - wm8994->dac_rates[iface]);
420 }
421 }
422
423 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
424 block,
425 pdata->retune_mobile_cfgs[best].name,
426 pdata->retune_mobile_cfgs[best].rate,
427 wm8994->dac_rates[iface]);
428
429 /* The EQ will be disabled while reconfiguring it, remember the
430 * current configuration.
431 */
432 save = snd_soc_read(codec, base);
433 save &= WM8994_AIF1DAC1_EQ_ENA;
434
435 for (i = 0; i < WM8994_EQ_REGS; i++)
436 snd_soc_update_bits(codec, base + i, 0xffff,
437 pdata->retune_mobile_cfgs[best].regs[i]);
438
439 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
440 }
441
442 /* Icky as hell but saves code duplication */
443 static int wm8994_get_retune_mobile_block(const char *name)
444 {
445 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
446 return 0;
447 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
448 return 1;
449 if (strcmp(name, "AIF2 EQ Mode") == 0)
450 return 2;
451 return -EINVAL;
452 }
453
454 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
455 struct snd_ctl_elem_value *ucontrol)
456 {
457 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
458 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
459 struct wm8994_pdata *pdata = wm8994->pdata;
460 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
461 int value = ucontrol->value.integer.value[0];
462
463 if (block < 0)
464 return block;
465
466 if (value >= pdata->num_retune_mobile_cfgs)
467 return -EINVAL;
468
469 wm8994->retune_mobile_cfg[block] = value;
470
471 wm8994_set_retune_mobile(codec, block);
472
473 return 0;
474 }
475
476 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
477 struct snd_ctl_elem_value *ucontrol)
478 {
479 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
480 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
481 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
482
483 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
484
485 return 0;
486 }
487
488 static const char *aif_chan_src_text[] = {
489 "Left", "Right"
490 };
491
492 static const struct soc_enum aif1adcl_src =
493 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
494
495 static const struct soc_enum aif1adcr_src =
496 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
497
498 static const struct soc_enum aif2adcl_src =
499 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
500
501 static const struct soc_enum aif2adcr_src =
502 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
503
504 static const struct soc_enum aif1dacl_src =
505 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
506
507 static const struct soc_enum aif1dacr_src =
508 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
509
510 static const struct soc_enum aif2dacl_src =
511 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
512
513 static const struct soc_enum aif2dacr_src =
514 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
515
516 static const char *osr_text[] = {
517 "Low Power", "High Performance",
518 };
519
520 static const struct soc_enum dac_osr =
521 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
522
523 static const struct soc_enum adc_osr =
524 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
525
526 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
527 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
528 WM8994_AIF1_ADC1_RIGHT_VOLUME,
529 1, 119, 0, digital_tlv),
530 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
531 WM8994_AIF1_ADC2_RIGHT_VOLUME,
532 1, 119, 0, digital_tlv),
533 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
534 WM8994_AIF2_ADC_RIGHT_VOLUME,
535 1, 119, 0, digital_tlv),
536
537 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
538 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
539 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
540 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
541
542 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
543 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
544 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
545 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
546
547 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
548 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
549 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
550 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
551 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
552 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
553
554 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
555 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
556
557 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
558 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
559 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
560
561 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
562 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
563 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
564
565 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
566 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
567 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
568
569 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
570 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
571 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
572
573 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
574 5, 12, 0, st_tlv),
575 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
576 0, 12, 0, st_tlv),
577 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
578 5, 12, 0, st_tlv),
579 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
580 0, 12, 0, st_tlv),
581 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
582 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
583
584 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
585 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
586
587 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
588 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
589
590 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
591 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
592
593 SOC_ENUM("ADC OSR", adc_osr),
594 SOC_ENUM("DAC OSR", dac_osr),
595
596 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
597 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
598 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
599 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
600
601 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
602 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
603 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
604 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
605
606 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
607 6, 1, 1, wm_hubs_spkmix_tlv),
608 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
609 2, 1, 1, wm_hubs_spkmix_tlv),
610
611 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
612 6, 1, 1, wm_hubs_spkmix_tlv),
613 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
614 2, 1, 1, wm_hubs_spkmix_tlv),
615
616 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
617 10, 15, 0, wm8994_3d_tlv),
618 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
619 8, 1, 0),
620 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
621 10, 15, 0, wm8994_3d_tlv),
622 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
623 8, 1, 0),
624 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
625 10, 15, 0, wm8994_3d_tlv),
626 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
627 8, 1, 0),
628 };
629
630 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
631 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
632 eq_tlv),
633 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
634 eq_tlv),
635 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
636 eq_tlv),
637 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
638 eq_tlv),
639 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
640 eq_tlv),
641
642 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
643 eq_tlv),
644 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
645 eq_tlv),
646 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
647 eq_tlv),
648 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
649 eq_tlv),
650 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
651 eq_tlv),
652
653 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
654 eq_tlv),
655 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
656 eq_tlv),
657 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
658 eq_tlv),
659 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
660 eq_tlv),
661 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
662 eq_tlv),
663 };
664
665 static const char *wm8958_ng_text[] = {
666 "30ms", "125ms", "250ms", "500ms",
667 };
668
669 static const struct soc_enum wm8958_aif1dac1_ng_hold =
670 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
671 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
672
673 static const struct soc_enum wm8958_aif1dac2_ng_hold =
674 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
675 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
676
677 static const struct soc_enum wm8958_aif2dac_ng_hold =
678 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
679 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
680
681 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
682 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
683
684 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
685 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
686 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
687 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
688 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
689 7, 1, ng_tlv),
690
691 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
692 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
693 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
694 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
695 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
696 7, 1, ng_tlv),
697
698 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
699 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
700 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
701 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
702 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
703 7, 1, ng_tlv),
704 };
705
706 static int clk_sys_event(struct snd_soc_dapm_widget *w,
707 struct snd_kcontrol *kcontrol, int event)
708 {
709 struct snd_soc_codec *codec = w->codec;
710
711 switch (event) {
712 case SND_SOC_DAPM_PRE_PMU:
713 return configure_clock(codec);
714
715 case SND_SOC_DAPM_POST_PMD:
716 configure_clock(codec);
717 break;
718 }
719
720 return 0;
721 }
722
723 static void vmid_reference(struct snd_soc_codec *codec)
724 {
725 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
726
727 wm8994->vmid_refcount++;
728
729 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
730 wm8994->vmid_refcount);
731
732 if (wm8994->vmid_refcount == 1) {
733 /* Startup bias, VMID ramp & buffer */
734 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
735 WM8994_STARTUP_BIAS_ENA |
736 WM8994_VMID_BUF_ENA |
737 WM8994_VMID_RAMP_MASK,
738 WM8994_STARTUP_BIAS_ENA |
739 WM8994_VMID_BUF_ENA |
740 (0x11 << WM8994_VMID_RAMP_SHIFT));
741
742 /* Main bias enable, VMID=2x40k */
743 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
744 WM8994_BIAS_ENA |
745 WM8994_VMID_SEL_MASK,
746 WM8994_BIAS_ENA | 0x2);
747
748 msleep(20);
749 }
750 }
751
752 static void vmid_dereference(struct snd_soc_codec *codec)
753 {
754 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
755
756 wm8994->vmid_refcount--;
757
758 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
759 wm8994->vmid_refcount);
760
761 if (wm8994->vmid_refcount == 0) {
762 /* Switch over to startup biases */
763 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
764 WM8994_BIAS_SRC |
765 WM8994_STARTUP_BIAS_ENA |
766 WM8994_VMID_BUF_ENA |
767 WM8994_VMID_RAMP_MASK,
768 WM8994_BIAS_SRC |
769 WM8994_STARTUP_BIAS_ENA |
770 WM8994_VMID_BUF_ENA |
771 (1 << WM8994_VMID_RAMP_SHIFT));
772
773 /* Disable main biases */
774 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
775 WM8994_BIAS_ENA |
776 WM8994_VMID_SEL_MASK, 0);
777
778 /* Discharge line */
779 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
780 WM8994_LINEOUT1_DISCH |
781 WM8994_LINEOUT2_DISCH,
782 WM8994_LINEOUT1_DISCH |
783 WM8994_LINEOUT2_DISCH);
784
785 msleep(5);
786
787 /* Switch off startup biases */
788 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
789 WM8994_BIAS_SRC |
790 WM8994_STARTUP_BIAS_ENA |
791 WM8994_VMID_BUF_ENA |
792 WM8994_VMID_RAMP_MASK, 0);
793 }
794 }
795
796 static int vmid_event(struct snd_soc_dapm_widget *w,
797 struct snd_kcontrol *kcontrol, int event)
798 {
799 struct snd_soc_codec *codec = w->codec;
800
801 switch (event) {
802 case SND_SOC_DAPM_PRE_PMU:
803 vmid_reference(codec);
804 break;
805
806 case SND_SOC_DAPM_POST_PMD:
807 vmid_dereference(codec);
808 break;
809 }
810
811 return 0;
812 }
813
814 static void wm8994_update_class_w(struct snd_soc_codec *codec)
815 {
816 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
817 int enable = 1;
818 int source = 0; /* GCC flow analysis can't track enable */
819 int reg, reg_r;
820
821 /* Only support direct DAC->headphone paths */
822 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
823 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
824 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
825 enable = 0;
826 }
827
828 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
829 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
830 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
831 enable = 0;
832 }
833
834 /* We also need the same setting for L/R and only one path */
835 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
836 switch (reg) {
837 case WM8994_AIF2DACL_TO_DAC1L:
838 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
839 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
840 break;
841 case WM8994_AIF1DAC2L_TO_DAC1L:
842 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
843 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
844 break;
845 case WM8994_AIF1DAC1L_TO_DAC1L:
846 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
847 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
848 break;
849 default:
850 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
851 enable = 0;
852 break;
853 }
854
855 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
856 if (reg_r != reg) {
857 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
858 enable = 0;
859 }
860
861 if (enable) {
862 dev_dbg(codec->dev, "Class W enabled\n");
863 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
864 WM8994_CP_DYN_PWR |
865 WM8994_CP_DYN_SRC_SEL_MASK,
866 source | WM8994_CP_DYN_PWR);
867 wm8994->hubs.class_w = true;
868
869 } else {
870 dev_dbg(codec->dev, "Class W disabled\n");
871 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
872 WM8994_CP_DYN_PWR, 0);
873 wm8994->hubs.class_w = false;
874 }
875 }
876
877 static int late_enable_ev(struct snd_soc_dapm_widget *w,
878 struct snd_kcontrol *kcontrol, int event)
879 {
880 struct snd_soc_codec *codec = w->codec;
881 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
882
883 switch (event) {
884 case SND_SOC_DAPM_PRE_PMU:
885 if (wm8994->aif1clk_enable) {
886 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
887 WM8994_AIF1CLK_ENA_MASK,
888 WM8994_AIF1CLK_ENA);
889 wm8994->aif1clk_enable = 0;
890 }
891 if (wm8994->aif2clk_enable) {
892 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
893 WM8994_AIF2CLK_ENA_MASK,
894 WM8994_AIF2CLK_ENA);
895 wm8994->aif2clk_enable = 0;
896 }
897 break;
898 }
899
900 /* We may also have postponed startup of DSP, handle that. */
901 wm8958_aif_ev(w, kcontrol, event);
902
903 return 0;
904 }
905
906 static int late_disable_ev(struct snd_soc_dapm_widget *w,
907 struct snd_kcontrol *kcontrol, int event)
908 {
909 struct snd_soc_codec *codec = w->codec;
910 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
911
912 switch (event) {
913 case SND_SOC_DAPM_POST_PMD:
914 if (wm8994->aif1clk_disable) {
915 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
916 WM8994_AIF1CLK_ENA_MASK, 0);
917 wm8994->aif1clk_disable = 0;
918 }
919 if (wm8994->aif2clk_disable) {
920 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
921 WM8994_AIF2CLK_ENA_MASK, 0);
922 wm8994->aif2clk_disable = 0;
923 }
924 break;
925 }
926
927 return 0;
928 }
929
930 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
931 struct snd_kcontrol *kcontrol, int event)
932 {
933 struct snd_soc_codec *codec = w->codec;
934 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
935
936 switch (event) {
937 case SND_SOC_DAPM_PRE_PMU:
938 wm8994->aif1clk_enable = 1;
939 break;
940 case SND_SOC_DAPM_POST_PMD:
941 wm8994->aif1clk_disable = 1;
942 break;
943 }
944
945 return 0;
946 }
947
948 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
949 struct snd_kcontrol *kcontrol, int event)
950 {
951 struct snd_soc_codec *codec = w->codec;
952 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
953
954 switch (event) {
955 case SND_SOC_DAPM_PRE_PMU:
956 wm8994->aif2clk_enable = 1;
957 break;
958 case SND_SOC_DAPM_POST_PMD:
959 wm8994->aif2clk_disable = 1;
960 break;
961 }
962
963 return 0;
964 }
965
966 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
967 struct snd_kcontrol *kcontrol, int event)
968 {
969 late_enable_ev(w, kcontrol, event);
970 return 0;
971 }
972
973 static int micbias_ev(struct snd_soc_dapm_widget *w,
974 struct snd_kcontrol *kcontrol, int event)
975 {
976 late_enable_ev(w, kcontrol, event);
977 return 0;
978 }
979
980 static int dac_ev(struct snd_soc_dapm_widget *w,
981 struct snd_kcontrol *kcontrol, int event)
982 {
983 struct snd_soc_codec *codec = w->codec;
984 unsigned int mask = 1 << w->shift;
985
986 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
987 mask, mask);
988 return 0;
989 }
990
991 static const char *hp_mux_text[] = {
992 "Mixer",
993 "DAC",
994 };
995
996 #define WM8994_HP_ENUM(xname, xenum) \
997 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
998 .info = snd_soc_info_enum_double, \
999 .get = snd_soc_dapm_get_enum_double, \
1000 .put = wm8994_put_hp_enum, \
1001 .private_value = (unsigned long)&xenum }
1002
1003 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1004 struct snd_ctl_elem_value *ucontrol)
1005 {
1006 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1007 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1008 struct snd_soc_codec *codec = w->codec;
1009 int ret;
1010
1011 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1012
1013 wm8994_update_class_w(codec);
1014
1015 return ret;
1016 }
1017
1018 static const struct soc_enum hpl_enum =
1019 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1020
1021 static const struct snd_kcontrol_new hpl_mux =
1022 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1023
1024 static const struct soc_enum hpr_enum =
1025 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1026
1027 static const struct snd_kcontrol_new hpr_mux =
1028 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1029
1030 static const char *adc_mux_text[] = {
1031 "ADC",
1032 "DMIC",
1033 };
1034
1035 static const struct soc_enum adc_enum =
1036 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1037
1038 static const struct snd_kcontrol_new adcl_mux =
1039 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1040
1041 static const struct snd_kcontrol_new adcr_mux =
1042 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1043
1044 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1045 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1046 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1047 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1048 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1049 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1050 };
1051
1052 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1053 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1054 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1055 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1056 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1057 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1058 };
1059
1060 /* Debugging; dump chip status after DAPM transitions */
1061 static int post_ev(struct snd_soc_dapm_widget *w,
1062 struct snd_kcontrol *kcontrol, int event)
1063 {
1064 struct snd_soc_codec *codec = w->codec;
1065 dev_dbg(codec->dev, "SRC status: %x\n",
1066 snd_soc_read(codec,
1067 WM8994_RATE_STATUS));
1068 return 0;
1069 }
1070
1071 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1072 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1073 1, 1, 0),
1074 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1075 0, 1, 0),
1076 };
1077
1078 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1079 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1080 1, 1, 0),
1081 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1082 0, 1, 0),
1083 };
1084
1085 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1086 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1087 1, 1, 0),
1088 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1089 0, 1, 0),
1090 };
1091
1092 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1093 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1094 1, 1, 0),
1095 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1096 0, 1, 0),
1097 };
1098
1099 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1100 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1101 5, 1, 0),
1102 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1103 4, 1, 0),
1104 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1105 2, 1, 0),
1106 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1107 1, 1, 0),
1108 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1109 0, 1, 0),
1110 };
1111
1112 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1113 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1114 5, 1, 0),
1115 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1116 4, 1, 0),
1117 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1118 2, 1, 0),
1119 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1120 1, 1, 0),
1121 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1122 0, 1, 0),
1123 };
1124
1125 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1126 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1127 .info = snd_soc_info_volsw, \
1128 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1129 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1130
1131 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1132 struct snd_ctl_elem_value *ucontrol)
1133 {
1134 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1135 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1136 struct snd_soc_codec *codec = w->codec;
1137 int ret;
1138
1139 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1140
1141 wm8994_update_class_w(codec);
1142
1143 return ret;
1144 }
1145
1146 static const struct snd_kcontrol_new dac1l_mix[] = {
1147 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1148 5, 1, 0),
1149 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1150 4, 1, 0),
1151 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1152 2, 1, 0),
1153 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1154 1, 1, 0),
1155 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1156 0, 1, 0),
1157 };
1158
1159 static const struct snd_kcontrol_new dac1r_mix[] = {
1160 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1161 5, 1, 0),
1162 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1163 4, 1, 0),
1164 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1165 2, 1, 0),
1166 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1167 1, 1, 0),
1168 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1169 0, 1, 0),
1170 };
1171
1172 static const char *sidetone_text[] = {
1173 "ADC/DMIC1", "DMIC2",
1174 };
1175
1176 static const struct soc_enum sidetone1_enum =
1177 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1178
1179 static const struct snd_kcontrol_new sidetone1_mux =
1180 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1181
1182 static const struct soc_enum sidetone2_enum =
1183 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1184
1185 static const struct snd_kcontrol_new sidetone2_mux =
1186 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1187
1188 static const char *aif1dac_text[] = {
1189 "AIF1DACDAT", "AIF3DACDAT",
1190 };
1191
1192 static const struct soc_enum aif1dac_enum =
1193 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1194
1195 static const struct snd_kcontrol_new aif1dac_mux =
1196 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1197
1198 static const char *aif2dac_text[] = {
1199 "AIF2DACDAT", "AIF3DACDAT",
1200 };
1201
1202 static const struct soc_enum aif2dac_enum =
1203 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1204
1205 static const struct snd_kcontrol_new aif2dac_mux =
1206 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1207
1208 static const char *aif2adc_text[] = {
1209 "AIF2ADCDAT", "AIF3DACDAT",
1210 };
1211
1212 static const struct soc_enum aif2adc_enum =
1213 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1214
1215 static const struct snd_kcontrol_new aif2adc_mux =
1216 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1217
1218 static const char *aif3adc_text[] = {
1219 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1220 };
1221
1222 static const struct soc_enum wm8994_aif3adc_enum =
1223 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1224
1225 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1226 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1227
1228 static const struct soc_enum wm8958_aif3adc_enum =
1229 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1230
1231 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1232 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1233
1234 static const char *mono_pcm_out_text[] = {
1235 "None", "AIF2ADCL", "AIF2ADCR",
1236 };
1237
1238 static const struct soc_enum mono_pcm_out_enum =
1239 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1240
1241 static const struct snd_kcontrol_new mono_pcm_out_mux =
1242 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1243
1244 static const char *aif2dac_src_text[] = {
1245 "AIF2", "AIF3",
1246 };
1247
1248 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1249 static const struct soc_enum aif2dacl_src_enum =
1250 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1251
1252 static const struct snd_kcontrol_new aif2dacl_src_mux =
1253 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1254
1255 static const struct soc_enum aif2dacr_src_enum =
1256 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1257
1258 static const struct snd_kcontrol_new aif2dacr_src_mux =
1259 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1260
1261 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1262 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1263 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1264 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1265 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1266
1267 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1268 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1269 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1270 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1271 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1272 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1273 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1274 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1275 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1276 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1277
1278 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1279 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1280 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1281 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1282 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1283 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1284 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1285 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1286 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1287 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1288
1289 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1290 };
1291
1292 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1293 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1294 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1295 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1296 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1297 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1298 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1299 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1300 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1301 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1302 };
1303
1304 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1305 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1306 dac_ev, SND_SOC_DAPM_PRE_PMU),
1307 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1308 dac_ev, SND_SOC_DAPM_PRE_PMU),
1309 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1310 dac_ev, SND_SOC_DAPM_PRE_PMU),
1311 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1312 dac_ev, SND_SOC_DAPM_PRE_PMU),
1313 };
1314
1315 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1316 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1317 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1318 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1319 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1320 };
1321
1322 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1323 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1324 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1325 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1326 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1327 };
1328
1329 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1330 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1331 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1332 };
1333
1334 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1335 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1336 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1337 SND_SOC_DAPM_INPUT("Clock"),
1338
1339 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1340 SND_SOC_DAPM_PRE_PMU),
1341 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1342 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1343
1344 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1345 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1346
1347 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1348 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1349 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1350
1351 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1352 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1353 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1354 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1355 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1356 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1357 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1358 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1359 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1360 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1361
1362 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1363 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1364 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1365 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1366 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1367 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1368 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1369 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1370 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1371 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1372
1373 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1374 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1375 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1376 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1377
1378 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1379 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1380 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1381 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1382
1383 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1384 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1385 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1386 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1387
1388 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1389 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1390
1391 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1392 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1393 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1394 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1395
1396 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1397 WM8994_POWER_MANAGEMENT_4, 13, 0),
1398 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1399 WM8994_POWER_MANAGEMENT_4, 12, 0),
1400 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1401 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1402 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1403 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1404 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1405 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1406
1407 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1408 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1409 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1410 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1411
1412 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1413 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1414 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1415
1416 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1417 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1418
1419 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1420
1421 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1422 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1423 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1424 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1425
1426 /* Power is done with the muxes since the ADC power also controls the
1427 * downsampling chain, the chip will automatically manage the analogue
1428 * specific portions.
1429 */
1430 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1431 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1432
1433 SND_SOC_DAPM_POST("Debug log", post_ev),
1434 };
1435
1436 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1437 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1438 };
1439
1440 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1441 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1442 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1443 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1444 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1445 };
1446
1447 static const struct snd_soc_dapm_route intercon[] = {
1448 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1449 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1450
1451 { "DSP1CLK", NULL, "CLK_SYS" },
1452 { "DSP2CLK", NULL, "CLK_SYS" },
1453 { "DSPINTCLK", NULL, "CLK_SYS" },
1454
1455 { "AIF1ADC1L", NULL, "AIF1CLK" },
1456 { "AIF1ADC1L", NULL, "DSP1CLK" },
1457 { "AIF1ADC1R", NULL, "AIF1CLK" },
1458 { "AIF1ADC1R", NULL, "DSP1CLK" },
1459 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1460
1461 { "AIF1DAC1L", NULL, "AIF1CLK" },
1462 { "AIF1DAC1L", NULL, "DSP1CLK" },
1463 { "AIF1DAC1R", NULL, "AIF1CLK" },
1464 { "AIF1DAC1R", NULL, "DSP1CLK" },
1465 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1466
1467 { "AIF1ADC2L", NULL, "AIF1CLK" },
1468 { "AIF1ADC2L", NULL, "DSP1CLK" },
1469 { "AIF1ADC2R", NULL, "AIF1CLK" },
1470 { "AIF1ADC2R", NULL, "DSP1CLK" },
1471 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1472
1473 { "AIF1DAC2L", NULL, "AIF1CLK" },
1474 { "AIF1DAC2L", NULL, "DSP1CLK" },
1475 { "AIF1DAC2R", NULL, "AIF1CLK" },
1476 { "AIF1DAC2R", NULL, "DSP1CLK" },
1477 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1478
1479 { "AIF2ADCL", NULL, "AIF2CLK" },
1480 { "AIF2ADCL", NULL, "DSP2CLK" },
1481 { "AIF2ADCR", NULL, "AIF2CLK" },
1482 { "AIF2ADCR", NULL, "DSP2CLK" },
1483 { "AIF2ADCR", NULL, "DSPINTCLK" },
1484
1485 { "AIF2DACL", NULL, "AIF2CLK" },
1486 { "AIF2DACL", NULL, "DSP2CLK" },
1487 { "AIF2DACR", NULL, "AIF2CLK" },
1488 { "AIF2DACR", NULL, "DSP2CLK" },
1489 { "AIF2DACR", NULL, "DSPINTCLK" },
1490
1491 { "DMIC1L", NULL, "DMIC1DAT" },
1492 { "DMIC1L", NULL, "CLK_SYS" },
1493 { "DMIC1R", NULL, "DMIC1DAT" },
1494 { "DMIC1R", NULL, "CLK_SYS" },
1495 { "DMIC2L", NULL, "DMIC2DAT" },
1496 { "DMIC2L", NULL, "CLK_SYS" },
1497 { "DMIC2R", NULL, "DMIC2DAT" },
1498 { "DMIC2R", NULL, "CLK_SYS" },
1499
1500 { "ADCL", NULL, "AIF1CLK" },
1501 { "ADCL", NULL, "DSP1CLK" },
1502 { "ADCL", NULL, "DSPINTCLK" },
1503
1504 { "ADCR", NULL, "AIF1CLK" },
1505 { "ADCR", NULL, "DSP1CLK" },
1506 { "ADCR", NULL, "DSPINTCLK" },
1507
1508 { "ADCL Mux", "ADC", "ADCL" },
1509 { "ADCL Mux", "DMIC", "DMIC1L" },
1510 { "ADCR Mux", "ADC", "ADCR" },
1511 { "ADCR Mux", "DMIC", "DMIC1R" },
1512
1513 { "DAC1L", NULL, "AIF1CLK" },
1514 { "DAC1L", NULL, "DSP1CLK" },
1515 { "DAC1L", NULL, "DSPINTCLK" },
1516
1517 { "DAC1R", NULL, "AIF1CLK" },
1518 { "DAC1R", NULL, "DSP1CLK" },
1519 { "DAC1R", NULL, "DSPINTCLK" },
1520
1521 { "DAC2L", NULL, "AIF2CLK" },
1522 { "DAC2L", NULL, "DSP2CLK" },
1523 { "DAC2L", NULL, "DSPINTCLK" },
1524
1525 { "DAC2R", NULL, "AIF2DACR" },
1526 { "DAC2R", NULL, "AIF2CLK" },
1527 { "DAC2R", NULL, "DSP2CLK" },
1528 { "DAC2R", NULL, "DSPINTCLK" },
1529
1530 { "TOCLK", NULL, "CLK_SYS" },
1531
1532 /* AIF1 outputs */
1533 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1534 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1535 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1536
1537 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1538 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1539 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1540
1541 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1542 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1543 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1544
1545 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1546 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1547 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1548
1549 /* Pin level routing for AIF3 */
1550 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1551 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1552 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1553 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1554
1555 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1556 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1557 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1558 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1559 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1560 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1561 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1562
1563 /* DAC1 inputs */
1564 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1565 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1566 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1567 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1568 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1569
1570 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1571 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1572 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1573 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1574 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1575
1576 /* DAC2/AIF2 outputs */
1577 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1578 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1579 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1580 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1581 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1582 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1583
1584 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1585 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1586 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1587 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1588 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1589 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1590
1591 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1592 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1593 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1594 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1595
1596 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1597
1598 /* AIF3 output */
1599 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1600 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1601 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1602 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1603 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1604 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1605 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1606 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1607
1608 /* Sidetone */
1609 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1610 { "Left Sidetone", "DMIC2", "DMIC2L" },
1611 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1612 { "Right Sidetone", "DMIC2", "DMIC2R" },
1613
1614 /* Output stages */
1615 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1616 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1617
1618 { "SPKL", "DAC1 Switch", "DAC1L" },
1619 { "SPKL", "DAC2 Switch", "DAC2L" },
1620
1621 { "SPKR", "DAC1 Switch", "DAC1R" },
1622 { "SPKR", "DAC2 Switch", "DAC2R" },
1623
1624 { "Left Headphone Mux", "DAC", "DAC1L" },
1625 { "Right Headphone Mux", "DAC", "DAC1R" },
1626 };
1627
1628 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1629 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1630 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1631 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1632 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1633 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1634 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1635 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1636 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1637 };
1638
1639 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1640 { "DAC1L", NULL, "DAC1L Mixer" },
1641 { "DAC1R", NULL, "DAC1R Mixer" },
1642 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1643 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1644 };
1645
1646 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1647 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1648 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1649 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1650 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1651 { "MICBIAS1", NULL, "CLK_SYS" },
1652 { "MICBIAS1", NULL, "MICBIAS Supply" },
1653 { "MICBIAS2", NULL, "CLK_SYS" },
1654 { "MICBIAS2", NULL, "MICBIAS Supply" },
1655 };
1656
1657 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1658 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1659 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1660 { "MICBIAS1", NULL, "VMID" },
1661 { "MICBIAS2", NULL, "VMID" },
1662 };
1663
1664 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1665 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1666 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1667
1668 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1669 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1670 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1671 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1672
1673 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1674 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1675
1676 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1677 };
1678
1679 /* The size in bits of the FLL divide multiplied by 10
1680 * to allow rounding later */
1681 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1682
1683 struct fll_div {
1684 u16 outdiv;
1685 u16 n;
1686 u16 k;
1687 u16 clk_ref_div;
1688 u16 fll_fratio;
1689 };
1690
1691 static int wm8994_get_fll_config(struct fll_div *fll,
1692 int freq_in, int freq_out)
1693 {
1694 u64 Kpart;
1695 unsigned int K, Ndiv, Nmod;
1696
1697 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1698
1699 /* Scale the input frequency down to <= 13.5MHz */
1700 fll->clk_ref_div = 0;
1701 while (freq_in > 13500000) {
1702 fll->clk_ref_div++;
1703 freq_in /= 2;
1704
1705 if (fll->clk_ref_div > 3)
1706 return -EINVAL;
1707 }
1708 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1709
1710 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1711 fll->outdiv = 3;
1712 while (freq_out * (fll->outdiv + 1) < 90000000) {
1713 fll->outdiv++;
1714 if (fll->outdiv > 63)
1715 return -EINVAL;
1716 }
1717 freq_out *= fll->outdiv + 1;
1718 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1719
1720 if (freq_in > 1000000) {
1721 fll->fll_fratio = 0;
1722 } else if (freq_in > 256000) {
1723 fll->fll_fratio = 1;
1724 freq_in *= 2;
1725 } else if (freq_in > 128000) {
1726 fll->fll_fratio = 2;
1727 freq_in *= 4;
1728 } else if (freq_in > 64000) {
1729 fll->fll_fratio = 3;
1730 freq_in *= 8;
1731 } else {
1732 fll->fll_fratio = 4;
1733 freq_in *= 16;
1734 }
1735 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1736
1737 /* Now, calculate N.K */
1738 Ndiv = freq_out / freq_in;
1739
1740 fll->n = Ndiv;
1741 Nmod = freq_out % freq_in;
1742 pr_debug("Nmod=%d\n", Nmod);
1743
1744 /* Calculate fractional part - scale up so we can round. */
1745 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1746
1747 do_div(Kpart, freq_in);
1748
1749 K = Kpart & 0xFFFFFFFF;
1750
1751 if ((K % 10) >= 5)
1752 K += 5;
1753
1754 /* Move down to proper range now rounding is done */
1755 fll->k = K / 10;
1756
1757 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1758
1759 return 0;
1760 }
1761
1762 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1763 unsigned int freq_in, unsigned int freq_out)
1764 {
1765 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1766 struct wm8994 *control = codec->control_data;
1767 int reg_offset, ret;
1768 struct fll_div fll;
1769 u16 reg, aif1, aif2;
1770 unsigned long timeout;
1771 bool was_enabled;
1772
1773 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1774 & WM8994_AIF1CLK_ENA;
1775
1776 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1777 & WM8994_AIF2CLK_ENA;
1778
1779 switch (id) {
1780 case WM8994_FLL1:
1781 reg_offset = 0;
1782 id = 0;
1783 break;
1784 case WM8994_FLL2:
1785 reg_offset = 0x20;
1786 id = 1;
1787 break;
1788 default:
1789 return -EINVAL;
1790 }
1791
1792 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1793 was_enabled = reg & WM8994_FLL1_ENA;
1794
1795 switch (src) {
1796 case 0:
1797 /* Allow no source specification when stopping */
1798 if (freq_out)
1799 return -EINVAL;
1800 src = wm8994->fll[id].src;
1801 break;
1802 case WM8994_FLL_SRC_MCLK1:
1803 case WM8994_FLL_SRC_MCLK2:
1804 case WM8994_FLL_SRC_LRCLK:
1805 case WM8994_FLL_SRC_BCLK:
1806 break;
1807 default:
1808 return -EINVAL;
1809 }
1810
1811 /* Are we changing anything? */
1812 if (wm8994->fll[id].src == src &&
1813 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1814 return 0;
1815
1816 /* If we're stopping the FLL redo the old config - no
1817 * registers will actually be written but we avoid GCC flow
1818 * analysis bugs spewing warnings.
1819 */
1820 if (freq_out)
1821 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1822 else
1823 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1824 wm8994->fll[id].out);
1825 if (ret < 0)
1826 return ret;
1827
1828 /* Gate the AIF clocks while we reclock */
1829 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1830 WM8994_AIF1CLK_ENA, 0);
1831 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1832 WM8994_AIF2CLK_ENA, 0);
1833
1834 /* We always need to disable the FLL while reconfiguring */
1835 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1836 WM8994_FLL1_ENA, 0);
1837
1838 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1839 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1840 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1841 WM8994_FLL1_OUTDIV_MASK |
1842 WM8994_FLL1_FRATIO_MASK, reg);
1843
1844 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1845
1846 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1847 WM8994_FLL1_N_MASK,
1848 fll.n << WM8994_FLL1_N_SHIFT);
1849
1850 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1851 WM8994_FLL1_REFCLK_DIV_MASK |
1852 WM8994_FLL1_REFCLK_SRC_MASK,
1853 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1854 (src - 1));
1855
1856 /* Clear any pending completion from a previous failure */
1857 try_wait_for_completion(&wm8994->fll_locked[id]);
1858
1859 /* Enable (with fractional mode if required) */
1860 if (freq_out) {
1861 /* Enable VMID if we need it */
1862 if (!was_enabled) {
1863 switch (control->type) {
1864 case WM8994:
1865 vmid_reference(codec);
1866 break;
1867 case WM8958:
1868 if (wm8994->revision < 1)
1869 vmid_reference(codec);
1870 break;
1871 default:
1872 break;
1873 }
1874 }
1875
1876 if (fll.k)
1877 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1878 else
1879 reg = WM8994_FLL1_ENA;
1880 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1881 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1882 reg);
1883
1884 if (wm8994->fll_locked_irq) {
1885 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1886 msecs_to_jiffies(10));
1887 if (timeout == 0)
1888 dev_warn(codec->dev,
1889 "Timed out waiting for FLL lock\n");
1890 } else {
1891 msleep(5);
1892 }
1893 } else {
1894 if (was_enabled) {
1895 switch (control->type) {
1896 case WM8994:
1897 vmid_dereference(codec);
1898 break;
1899 case WM8958:
1900 if (wm8994->revision < 1)
1901 vmid_dereference(codec);
1902 break;
1903 default:
1904 break;
1905 }
1906 }
1907 }
1908
1909 wm8994->fll[id].in = freq_in;
1910 wm8994->fll[id].out = freq_out;
1911 wm8994->fll[id].src = src;
1912
1913 /* Enable any gated AIF clocks */
1914 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1915 WM8994_AIF1CLK_ENA, aif1);
1916 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1917 WM8994_AIF2CLK_ENA, aif2);
1918
1919 configure_clock(codec);
1920
1921 return 0;
1922 }
1923
1924 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
1925 {
1926 struct completion *completion = data;
1927
1928 complete(completion);
1929
1930 return IRQ_HANDLED;
1931 }
1932
1933 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1934
1935 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1936 unsigned int freq_in, unsigned int freq_out)
1937 {
1938 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1939 }
1940
1941 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1942 int clk_id, unsigned int freq, int dir)
1943 {
1944 struct snd_soc_codec *codec = dai->codec;
1945 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1946 int i;
1947
1948 switch (dai->id) {
1949 case 1:
1950 case 2:
1951 break;
1952
1953 default:
1954 /* AIF3 shares clocking with AIF1/2 */
1955 return -EINVAL;
1956 }
1957
1958 switch (clk_id) {
1959 case WM8994_SYSCLK_MCLK1:
1960 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1961 wm8994->mclk[0] = freq;
1962 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1963 dai->id, freq);
1964 break;
1965
1966 case WM8994_SYSCLK_MCLK2:
1967 /* TODO: Set GPIO AF */
1968 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1969 wm8994->mclk[1] = freq;
1970 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1971 dai->id, freq);
1972 break;
1973
1974 case WM8994_SYSCLK_FLL1:
1975 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1976 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1977 break;
1978
1979 case WM8994_SYSCLK_FLL2:
1980 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1981 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1982 break;
1983
1984 case WM8994_SYSCLK_OPCLK:
1985 /* Special case - a division (times 10) is given and
1986 * no effect on main clocking.
1987 */
1988 if (freq) {
1989 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1990 if (opclk_divs[i] == freq)
1991 break;
1992 if (i == ARRAY_SIZE(opclk_divs))
1993 return -EINVAL;
1994 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
1995 WM8994_OPCLK_DIV_MASK, i);
1996 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1997 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
1998 } else {
1999 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2000 WM8994_OPCLK_ENA, 0);
2001 }
2002
2003 default:
2004 return -EINVAL;
2005 }
2006
2007 configure_clock(codec);
2008
2009 return 0;
2010 }
2011
2012 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2013 enum snd_soc_bias_level level)
2014 {
2015 struct wm8994 *control = codec->control_data;
2016 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2017
2018 switch (level) {
2019 case SND_SOC_BIAS_ON:
2020 break;
2021
2022 case SND_SOC_BIAS_PREPARE:
2023 break;
2024
2025 case SND_SOC_BIAS_STANDBY:
2026 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2027 pm_runtime_get_sync(codec->dev);
2028
2029 switch (control->type) {
2030 case WM8994:
2031 if (wm8994->revision < 4) {
2032 /* Tweak DC servo and DSP
2033 * configuration for improved
2034 * performance. */
2035 snd_soc_write(codec, 0x102, 0x3);
2036 snd_soc_write(codec, 0x56, 0x3);
2037 snd_soc_write(codec, 0x817, 0);
2038 snd_soc_write(codec, 0x102, 0);
2039 }
2040 break;
2041
2042 case WM8958:
2043 if (wm8994->revision == 0) {
2044 /* Optimise performance for rev A */
2045 snd_soc_write(codec, 0x102, 0x3);
2046 snd_soc_write(codec, 0xcb, 0x81);
2047 snd_soc_write(codec, 0x817, 0);
2048 snd_soc_write(codec, 0x102, 0);
2049
2050 snd_soc_update_bits(codec,
2051 WM8958_CHARGE_PUMP_2,
2052 WM8958_CP_DISCH,
2053 WM8958_CP_DISCH);
2054 }
2055 break;
2056 }
2057
2058 /* Discharge LINEOUT1 & 2 */
2059 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2060 WM8994_LINEOUT1_DISCH |
2061 WM8994_LINEOUT2_DISCH,
2062 WM8994_LINEOUT1_DISCH |
2063 WM8994_LINEOUT2_DISCH);
2064 }
2065
2066
2067 break;
2068
2069 case SND_SOC_BIAS_OFF:
2070 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
2071 wm8994->cur_fw = NULL;
2072
2073 pm_runtime_put(codec->dev);
2074 }
2075 break;
2076 }
2077 codec->dapm.bias_level = level;
2078 return 0;
2079 }
2080
2081 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2082 {
2083 struct snd_soc_codec *codec = dai->codec;
2084 struct wm8994 *control = codec->control_data;
2085 int ms_reg;
2086 int aif1_reg;
2087 int ms = 0;
2088 int aif1 = 0;
2089
2090 switch (dai->id) {
2091 case 1:
2092 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2093 aif1_reg = WM8994_AIF1_CONTROL_1;
2094 break;
2095 case 2:
2096 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2097 aif1_reg = WM8994_AIF2_CONTROL_1;
2098 break;
2099 default:
2100 return -EINVAL;
2101 }
2102
2103 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2104 case SND_SOC_DAIFMT_CBS_CFS:
2105 break;
2106 case SND_SOC_DAIFMT_CBM_CFM:
2107 ms = WM8994_AIF1_MSTR;
2108 break;
2109 default:
2110 return -EINVAL;
2111 }
2112
2113 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2114 case SND_SOC_DAIFMT_DSP_B:
2115 aif1 |= WM8994_AIF1_LRCLK_INV;
2116 case SND_SOC_DAIFMT_DSP_A:
2117 aif1 |= 0x18;
2118 break;
2119 case SND_SOC_DAIFMT_I2S:
2120 aif1 |= 0x10;
2121 break;
2122 case SND_SOC_DAIFMT_RIGHT_J:
2123 break;
2124 case SND_SOC_DAIFMT_LEFT_J:
2125 aif1 |= 0x8;
2126 break;
2127 default:
2128 return -EINVAL;
2129 }
2130
2131 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2132 case SND_SOC_DAIFMT_DSP_A:
2133 case SND_SOC_DAIFMT_DSP_B:
2134 /* frame inversion not valid for DSP modes */
2135 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2136 case SND_SOC_DAIFMT_NB_NF:
2137 break;
2138 case SND_SOC_DAIFMT_IB_NF:
2139 aif1 |= WM8994_AIF1_BCLK_INV;
2140 break;
2141 default:
2142 return -EINVAL;
2143 }
2144 break;
2145
2146 case SND_SOC_DAIFMT_I2S:
2147 case SND_SOC_DAIFMT_RIGHT_J:
2148 case SND_SOC_DAIFMT_LEFT_J:
2149 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2150 case SND_SOC_DAIFMT_NB_NF:
2151 break;
2152 case SND_SOC_DAIFMT_IB_IF:
2153 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2154 break;
2155 case SND_SOC_DAIFMT_IB_NF:
2156 aif1 |= WM8994_AIF1_BCLK_INV;
2157 break;
2158 case SND_SOC_DAIFMT_NB_IF:
2159 aif1 |= WM8994_AIF1_LRCLK_INV;
2160 break;
2161 default:
2162 return -EINVAL;
2163 }
2164 break;
2165 default:
2166 return -EINVAL;
2167 }
2168
2169 /* The AIF2 format configuration needs to be mirrored to AIF3
2170 * on WM8958 if it's in use so just do it all the time. */
2171 if (control->type == WM8958 && dai->id == 2)
2172 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2173 WM8994_AIF1_LRCLK_INV |
2174 WM8958_AIF3_FMT_MASK, aif1);
2175
2176 snd_soc_update_bits(codec, aif1_reg,
2177 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2178 WM8994_AIF1_FMT_MASK,
2179 aif1);
2180 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2181 ms);
2182
2183 return 0;
2184 }
2185
2186 static struct {
2187 int val, rate;
2188 } srs[] = {
2189 { 0, 8000 },
2190 { 1, 11025 },
2191 { 2, 12000 },
2192 { 3, 16000 },
2193 { 4, 22050 },
2194 { 5, 24000 },
2195 { 6, 32000 },
2196 { 7, 44100 },
2197 { 8, 48000 },
2198 { 9, 88200 },
2199 { 10, 96000 },
2200 };
2201
2202 static int fs_ratios[] = {
2203 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2204 };
2205
2206 static int bclk_divs[] = {
2207 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2208 640, 880, 960, 1280, 1760, 1920
2209 };
2210
2211 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2212 struct snd_pcm_hw_params *params,
2213 struct snd_soc_dai *dai)
2214 {
2215 struct snd_soc_codec *codec = dai->codec;
2216 struct wm8994 *control = codec->control_data;
2217 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2218 int aif1_reg;
2219 int aif2_reg;
2220 int bclk_reg;
2221 int lrclk_reg;
2222 int rate_reg;
2223 int aif1 = 0;
2224 int aif2 = 0;
2225 int bclk = 0;
2226 int lrclk = 0;
2227 int rate_val = 0;
2228 int id = dai->id - 1;
2229
2230 int i, cur_val, best_val, bclk_rate, best;
2231
2232 switch (dai->id) {
2233 case 1:
2234 aif1_reg = WM8994_AIF1_CONTROL_1;
2235 aif2_reg = WM8994_AIF1_CONTROL_2;
2236 bclk_reg = WM8994_AIF1_BCLK;
2237 rate_reg = WM8994_AIF1_RATE;
2238 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2239 wm8994->lrclk_shared[0]) {
2240 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2241 } else {
2242 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2243 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2244 }
2245 break;
2246 case 2:
2247 aif1_reg = WM8994_AIF2_CONTROL_1;
2248 aif2_reg = WM8994_AIF2_CONTROL_2;
2249 bclk_reg = WM8994_AIF2_BCLK;
2250 rate_reg = WM8994_AIF2_RATE;
2251 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2252 wm8994->lrclk_shared[1]) {
2253 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2254 } else {
2255 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2256 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2257 }
2258 break;
2259 case 3:
2260 switch (control->type) {
2261 case WM8958:
2262 aif1_reg = WM8958_AIF3_CONTROL_1;
2263 break;
2264 default:
2265 return 0;
2266 }
2267 default:
2268 return -EINVAL;
2269 }
2270
2271 bclk_rate = params_rate(params) * 2;
2272 switch (params_format(params)) {
2273 case SNDRV_PCM_FORMAT_S16_LE:
2274 bclk_rate *= 16;
2275 break;
2276 case SNDRV_PCM_FORMAT_S20_3LE:
2277 bclk_rate *= 20;
2278 aif1 |= 0x20;
2279 break;
2280 case SNDRV_PCM_FORMAT_S24_LE:
2281 bclk_rate *= 24;
2282 aif1 |= 0x40;
2283 break;
2284 case SNDRV_PCM_FORMAT_S32_LE:
2285 bclk_rate *= 32;
2286 aif1 |= 0x60;
2287 break;
2288 default:
2289 return -EINVAL;
2290 }
2291
2292 /* Try to find an appropriate sample rate; look for an exact match. */
2293 for (i = 0; i < ARRAY_SIZE(srs); i++)
2294 if (srs[i].rate == params_rate(params))
2295 break;
2296 if (i == ARRAY_SIZE(srs))
2297 return -EINVAL;
2298 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2299
2300 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2301 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2302 dai->id, wm8994->aifclk[id], bclk_rate);
2303
2304 if (params_channels(params) == 1 &&
2305 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2306 aif2 |= WM8994_AIF1_MONO;
2307
2308 if (wm8994->aifclk[id] == 0) {
2309 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2310 return -EINVAL;
2311 }
2312
2313 /* AIFCLK/fs ratio; look for a close match in either direction */
2314 best = 0;
2315 best_val = abs((fs_ratios[0] * params_rate(params))
2316 - wm8994->aifclk[id]);
2317 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2318 cur_val = abs((fs_ratios[i] * params_rate(params))
2319 - wm8994->aifclk[id]);
2320 if (cur_val >= best_val)
2321 continue;
2322 best = i;
2323 best_val = cur_val;
2324 }
2325 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2326 dai->id, fs_ratios[best]);
2327 rate_val |= best;
2328
2329 /* We may not get quite the right frequency if using
2330 * approximate clocks so look for the closest match that is
2331 * higher than the target (we need to ensure that there enough
2332 * BCLKs to clock out the samples).
2333 */
2334 best = 0;
2335 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2336 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2337 if (cur_val < 0) /* BCLK table is sorted */
2338 break;
2339 best = i;
2340 }
2341 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2342 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2343 bclk_divs[best], bclk_rate);
2344 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2345
2346 lrclk = bclk_rate / params_rate(params);
2347 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2348 lrclk, bclk_rate / lrclk);
2349
2350 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2351 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2352 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2353 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2354 lrclk);
2355 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2356 WM8994_AIF1CLK_RATE_MASK, rate_val);
2357
2358 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2359 switch (dai->id) {
2360 case 1:
2361 wm8994->dac_rates[0] = params_rate(params);
2362 wm8994_set_retune_mobile(codec, 0);
2363 wm8994_set_retune_mobile(codec, 1);
2364 break;
2365 case 2:
2366 wm8994->dac_rates[1] = params_rate(params);
2367 wm8994_set_retune_mobile(codec, 2);
2368 break;
2369 }
2370 }
2371
2372 return 0;
2373 }
2374
2375 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2376 struct snd_pcm_hw_params *params,
2377 struct snd_soc_dai *dai)
2378 {
2379 struct snd_soc_codec *codec = dai->codec;
2380 struct wm8994 *control = codec->control_data;
2381 int aif1_reg;
2382 int aif1 = 0;
2383
2384 switch (dai->id) {
2385 case 3:
2386 switch (control->type) {
2387 case WM8958:
2388 aif1_reg = WM8958_AIF3_CONTROL_1;
2389 break;
2390 default:
2391 return 0;
2392 }
2393 default:
2394 return 0;
2395 }
2396
2397 switch (params_format(params)) {
2398 case SNDRV_PCM_FORMAT_S16_LE:
2399 break;
2400 case SNDRV_PCM_FORMAT_S20_3LE:
2401 aif1 |= 0x20;
2402 break;
2403 case SNDRV_PCM_FORMAT_S24_LE:
2404 aif1 |= 0x40;
2405 break;
2406 case SNDRV_PCM_FORMAT_S32_LE:
2407 aif1 |= 0x60;
2408 break;
2409 default:
2410 return -EINVAL;
2411 }
2412
2413 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2414 }
2415
2416 static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2417 struct snd_soc_dai *dai)
2418 {
2419 struct snd_soc_codec *codec = dai->codec;
2420 int rate_reg = 0;
2421
2422 switch (dai->id) {
2423 case 1:
2424 rate_reg = WM8994_AIF1_RATE;
2425 break;
2426 case 2:
2427 rate_reg = WM8994_AIF1_RATE;
2428 break;
2429 default:
2430 break;
2431 }
2432
2433 /* If the DAI is idle then configure the divider tree for the
2434 * lowest output rate to save a little power if the clock is
2435 * still active (eg, because it is system clock).
2436 */
2437 if (rate_reg && !dai->playback_active && !dai->capture_active)
2438 snd_soc_update_bits(codec, rate_reg,
2439 WM8994_AIF1_SR_MASK |
2440 WM8994_AIF1CLK_RATE_MASK, 0x9);
2441 }
2442
2443 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2444 {
2445 struct snd_soc_codec *codec = codec_dai->codec;
2446 int mute_reg;
2447 int reg;
2448
2449 switch (codec_dai->id) {
2450 case 1:
2451 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2452 break;
2453 case 2:
2454 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2455 break;
2456 default:
2457 return -EINVAL;
2458 }
2459
2460 if (mute)
2461 reg = WM8994_AIF1DAC1_MUTE;
2462 else
2463 reg = 0;
2464
2465 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2466
2467 return 0;
2468 }
2469
2470 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2471 {
2472 struct snd_soc_codec *codec = codec_dai->codec;
2473 int reg, val, mask;
2474
2475 switch (codec_dai->id) {
2476 case 1:
2477 reg = WM8994_AIF1_MASTER_SLAVE;
2478 mask = WM8994_AIF1_TRI;
2479 break;
2480 case 2:
2481 reg = WM8994_AIF2_MASTER_SLAVE;
2482 mask = WM8994_AIF2_TRI;
2483 break;
2484 case 3:
2485 reg = WM8994_POWER_MANAGEMENT_6;
2486 mask = WM8994_AIF3_TRI;
2487 break;
2488 default:
2489 return -EINVAL;
2490 }
2491
2492 if (tristate)
2493 val = mask;
2494 else
2495 val = 0;
2496
2497 return snd_soc_update_bits(codec, reg, mask, val);
2498 }
2499
2500 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2501 {
2502 struct snd_soc_codec *codec = dai->codec;
2503
2504 /* Disable the pulls on the AIF if we're using it to save power. */
2505 snd_soc_update_bits(codec, WM8994_GPIO_3,
2506 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2507 snd_soc_update_bits(codec, WM8994_GPIO_4,
2508 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2509 snd_soc_update_bits(codec, WM8994_GPIO_5,
2510 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2511
2512 return 0;
2513 }
2514
2515 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2516
2517 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2518 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2519
2520 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2521 .set_sysclk = wm8994_set_dai_sysclk,
2522 .set_fmt = wm8994_set_dai_fmt,
2523 .hw_params = wm8994_hw_params,
2524 .shutdown = wm8994_aif_shutdown,
2525 .digital_mute = wm8994_aif_mute,
2526 .set_pll = wm8994_set_fll,
2527 .set_tristate = wm8994_set_tristate,
2528 };
2529
2530 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2531 .set_sysclk = wm8994_set_dai_sysclk,
2532 .set_fmt = wm8994_set_dai_fmt,
2533 .hw_params = wm8994_hw_params,
2534 .shutdown = wm8994_aif_shutdown,
2535 .digital_mute = wm8994_aif_mute,
2536 .set_pll = wm8994_set_fll,
2537 .set_tristate = wm8994_set_tristate,
2538 };
2539
2540 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2541 .hw_params = wm8994_aif3_hw_params,
2542 .set_tristate = wm8994_set_tristate,
2543 };
2544
2545 static struct snd_soc_dai_driver wm8994_dai[] = {
2546 {
2547 .name = "wm8994-aif1",
2548 .id = 1,
2549 .playback = {
2550 .stream_name = "AIF1 Playback",
2551 .channels_min = 1,
2552 .channels_max = 2,
2553 .rates = WM8994_RATES,
2554 .formats = WM8994_FORMATS,
2555 },
2556 .capture = {
2557 .stream_name = "AIF1 Capture",
2558 .channels_min = 1,
2559 .channels_max = 2,
2560 .rates = WM8994_RATES,
2561 .formats = WM8994_FORMATS,
2562 },
2563 .ops = &wm8994_aif1_dai_ops,
2564 },
2565 {
2566 .name = "wm8994-aif2",
2567 .id = 2,
2568 .playback = {
2569 .stream_name = "AIF2 Playback",
2570 .channels_min = 1,
2571 .channels_max = 2,
2572 .rates = WM8994_RATES,
2573 .formats = WM8994_FORMATS,
2574 },
2575 .capture = {
2576 .stream_name = "AIF2 Capture",
2577 .channels_min = 1,
2578 .channels_max = 2,
2579 .rates = WM8994_RATES,
2580 .formats = WM8994_FORMATS,
2581 },
2582 .probe = wm8994_aif2_probe,
2583 .ops = &wm8994_aif2_dai_ops,
2584 },
2585 {
2586 .name = "wm8994-aif3",
2587 .id = 3,
2588 .playback = {
2589 .stream_name = "AIF3 Playback",
2590 .channels_min = 1,
2591 .channels_max = 2,
2592 .rates = WM8994_RATES,
2593 .formats = WM8994_FORMATS,
2594 },
2595 .capture = {
2596 .stream_name = "AIF3 Capture",
2597 .channels_min = 1,
2598 .channels_max = 2,
2599 .rates = WM8994_RATES,
2600 .formats = WM8994_FORMATS,
2601 },
2602 .ops = &wm8994_aif3_dai_ops,
2603 }
2604 };
2605
2606 #ifdef CONFIG_PM
2607 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2608 {
2609 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2610 struct wm8994 *control = codec->control_data;
2611 int i, ret;
2612
2613 switch (control->type) {
2614 case WM8994:
2615 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2616 break;
2617 case WM8958:
2618 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2619 WM8958_MICD_ENA, 0);
2620 break;
2621 }
2622
2623 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2624 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2625 sizeof(struct wm8994_fll_config));
2626 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2627 if (ret < 0)
2628 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2629 i + 1, ret);
2630 }
2631
2632 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2633
2634 return 0;
2635 }
2636
2637 static int wm8994_resume(struct snd_soc_codec *codec)
2638 {
2639 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2640 struct wm8994 *control = codec->control_data;
2641 int i, ret;
2642 unsigned int val, mask;
2643
2644 if (wm8994->revision < 4) {
2645 /* force a HW read */
2646 val = wm8994_reg_read(codec->control_data,
2647 WM8994_POWER_MANAGEMENT_5);
2648
2649 /* modify the cache only */
2650 codec->cache_only = 1;
2651 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2652 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2653 val &= mask;
2654 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2655 mask, val);
2656 codec->cache_only = 0;
2657 }
2658
2659 /* Restore the registers */
2660 ret = snd_soc_cache_sync(codec);
2661 if (ret != 0)
2662 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2663
2664 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2665
2666 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2667 if (!wm8994->fll_suspend[i].out)
2668 continue;
2669
2670 ret = _wm8994_set_fll(codec, i + 1,
2671 wm8994->fll_suspend[i].src,
2672 wm8994->fll_suspend[i].in,
2673 wm8994->fll_suspend[i].out);
2674 if (ret < 0)
2675 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2676 i + 1, ret);
2677 }
2678
2679 switch (control->type) {
2680 case WM8994:
2681 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2682 snd_soc_update_bits(codec, WM8994_MICBIAS,
2683 WM8994_MICD_ENA, WM8994_MICD_ENA);
2684 break;
2685 case WM8958:
2686 if (wm8994->jack_cb)
2687 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2688 WM8958_MICD_ENA, WM8958_MICD_ENA);
2689 break;
2690 }
2691
2692 return 0;
2693 }
2694 #else
2695 #define wm8994_suspend NULL
2696 #define wm8994_resume NULL
2697 #endif
2698
2699 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2700 {
2701 struct snd_soc_codec *codec = wm8994->codec;
2702 struct wm8994_pdata *pdata = wm8994->pdata;
2703 struct snd_kcontrol_new controls[] = {
2704 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2705 wm8994->retune_mobile_enum,
2706 wm8994_get_retune_mobile_enum,
2707 wm8994_put_retune_mobile_enum),
2708 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2709 wm8994->retune_mobile_enum,
2710 wm8994_get_retune_mobile_enum,
2711 wm8994_put_retune_mobile_enum),
2712 SOC_ENUM_EXT("AIF2 EQ Mode",
2713 wm8994->retune_mobile_enum,
2714 wm8994_get_retune_mobile_enum,
2715 wm8994_put_retune_mobile_enum),
2716 };
2717 int ret, i, j;
2718 const char **t;
2719
2720 /* We need an array of texts for the enum API but the number
2721 * of texts is likely to be less than the number of
2722 * configurations due to the sample rate dependency of the
2723 * configurations. */
2724 wm8994->num_retune_mobile_texts = 0;
2725 wm8994->retune_mobile_texts = NULL;
2726 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2727 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2728 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2729 wm8994->retune_mobile_texts[j]) == 0)
2730 break;
2731 }
2732
2733 if (j != wm8994->num_retune_mobile_texts)
2734 continue;
2735
2736 /* Expand the array... */
2737 t = krealloc(wm8994->retune_mobile_texts,
2738 sizeof(char *) *
2739 (wm8994->num_retune_mobile_texts + 1),
2740 GFP_KERNEL);
2741 if (t == NULL)
2742 continue;
2743
2744 /* ...store the new entry... */
2745 t[wm8994->num_retune_mobile_texts] =
2746 pdata->retune_mobile_cfgs[i].name;
2747
2748 /* ...and remember the new version. */
2749 wm8994->num_retune_mobile_texts++;
2750 wm8994->retune_mobile_texts = t;
2751 }
2752
2753 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2754 wm8994->num_retune_mobile_texts);
2755
2756 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2757 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2758
2759 ret = snd_soc_add_controls(wm8994->codec, controls,
2760 ARRAY_SIZE(controls));
2761 if (ret != 0)
2762 dev_err(wm8994->codec->dev,
2763 "Failed to add ReTune Mobile controls: %d\n", ret);
2764 }
2765
2766 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2767 {
2768 struct snd_soc_codec *codec = wm8994->codec;
2769 struct wm8994_pdata *pdata = wm8994->pdata;
2770 int ret, i;
2771
2772 if (!pdata)
2773 return;
2774
2775 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2776 pdata->lineout2_diff,
2777 pdata->lineout1fb,
2778 pdata->lineout2fb,
2779 pdata->jd_scthr,
2780 pdata->jd_thr,
2781 pdata->micbias1_lvl,
2782 pdata->micbias2_lvl);
2783
2784 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2785
2786 if (pdata->num_drc_cfgs) {
2787 struct snd_kcontrol_new controls[] = {
2788 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2789 wm8994_get_drc_enum, wm8994_put_drc_enum),
2790 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2791 wm8994_get_drc_enum, wm8994_put_drc_enum),
2792 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2793 wm8994_get_drc_enum, wm8994_put_drc_enum),
2794 };
2795
2796 /* We need an array of texts for the enum API */
2797 wm8994->drc_texts = kmalloc(sizeof(char *)
2798 * pdata->num_drc_cfgs, GFP_KERNEL);
2799 if (!wm8994->drc_texts) {
2800 dev_err(wm8994->codec->dev,
2801 "Failed to allocate %d DRC config texts\n",
2802 pdata->num_drc_cfgs);
2803 return;
2804 }
2805
2806 for (i = 0; i < pdata->num_drc_cfgs; i++)
2807 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2808
2809 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2810 wm8994->drc_enum.texts = wm8994->drc_texts;
2811
2812 ret = snd_soc_add_controls(wm8994->codec, controls,
2813 ARRAY_SIZE(controls));
2814 if (ret != 0)
2815 dev_err(wm8994->codec->dev,
2816 "Failed to add DRC mode controls: %d\n", ret);
2817
2818 for (i = 0; i < WM8994_NUM_DRC; i++)
2819 wm8994_set_drc(codec, i);
2820 }
2821
2822 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2823 pdata->num_retune_mobile_cfgs);
2824
2825 if (pdata->num_retune_mobile_cfgs)
2826 wm8994_handle_retune_mobile_pdata(wm8994);
2827 else
2828 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2829 ARRAY_SIZE(wm8994_eq_controls));
2830
2831 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2832 if (pdata->micbias[i]) {
2833 snd_soc_write(codec, WM8958_MICBIAS1 + i,
2834 pdata->micbias[i] & 0xffff);
2835 }
2836 }
2837 }
2838
2839 /**
2840 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2841 *
2842 * @codec: WM8994 codec
2843 * @jack: jack to report detection events on
2844 * @micbias: microphone bias to detect on
2845 * @det: value to report for presence detection
2846 * @shrt: value to report for short detection
2847 *
2848 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2849 * being used to bring out signals to the processor then only platform
2850 * data configuration is needed for WM8994 and processor GPIOs should
2851 * be configured using snd_soc_jack_add_gpios() instead.
2852 *
2853 * Configuration of detection levels is available via the micbias1_lvl
2854 * and micbias2_lvl platform data members.
2855 */
2856 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2857 int micbias, int det, int shrt)
2858 {
2859 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2860 struct wm8994_micdet *micdet;
2861 struct wm8994 *control = codec->control_data;
2862 int reg;
2863
2864 if (control->type != WM8994)
2865 return -EINVAL;
2866
2867 switch (micbias) {
2868 case 1:
2869 micdet = &wm8994->micdet[0];
2870 break;
2871 case 2:
2872 micdet = &wm8994->micdet[1];
2873 break;
2874 default:
2875 return -EINVAL;
2876 }
2877
2878 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2879 micbias, det, shrt);
2880
2881 /* Store the configuration */
2882 micdet->jack = jack;
2883 micdet->det = det;
2884 micdet->shrt = shrt;
2885
2886 /* If either of the jacks is set up then enable detection */
2887 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2888 reg = WM8994_MICD_ENA;
2889 else
2890 reg = 0;
2891
2892 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2893
2894 return 0;
2895 }
2896 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2897
2898 static irqreturn_t wm8994_mic_irq(int irq, void *data)
2899 {
2900 struct wm8994_priv *priv = data;
2901 struct snd_soc_codec *codec = priv->codec;
2902 int reg;
2903 int report;
2904
2905 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2906 trace_snd_soc_jack_irq(dev_name(codec->dev));
2907 #endif
2908
2909 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2910 if (reg < 0) {
2911 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2912 reg);
2913 return IRQ_HANDLED;
2914 }
2915
2916 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2917
2918 report = 0;
2919 if (reg & WM8994_MIC1_DET_STS)
2920 report |= priv->micdet[0].det;
2921 if (reg & WM8994_MIC1_SHRT_STS)
2922 report |= priv->micdet[0].shrt;
2923 snd_soc_jack_report(priv->micdet[0].jack, report,
2924 priv->micdet[0].det | priv->micdet[0].shrt);
2925
2926 report = 0;
2927 if (reg & WM8994_MIC2_DET_STS)
2928 report |= priv->micdet[1].det;
2929 if (reg & WM8994_MIC2_SHRT_STS)
2930 report |= priv->micdet[1].shrt;
2931 snd_soc_jack_report(priv->micdet[1].jack, report,
2932 priv->micdet[1].det | priv->micdet[1].shrt);
2933
2934 return IRQ_HANDLED;
2935 }
2936
2937 /* Default microphone detection handler for WM8958 - the user can
2938 * override this if they wish.
2939 */
2940 static void wm8958_default_micdet(u16 status, void *data)
2941 {
2942 struct snd_soc_codec *codec = data;
2943 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2944 int report = 0;
2945
2946 /* If nothing present then clear our statuses */
2947 if (!(status & WM8958_MICD_STS))
2948 goto done;
2949
2950 report = SND_JACK_MICROPHONE;
2951
2952 /* Everything else is buttons; just assign slots */
2953 if (status & 0x1c)
2954 report |= SND_JACK_BTN_0;
2955
2956 done:
2957 snd_soc_jack_report(wm8994->micdet[0].jack, report,
2958 SND_JACK_BTN_0 | SND_JACK_MICROPHONE);
2959 }
2960
2961 /**
2962 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2963 *
2964 * @codec: WM8958 codec
2965 * @jack: jack to report detection events on
2966 *
2967 * Enable microphone detection functionality for the WM8958. By
2968 * default simple detection which supports the detection of up to 6
2969 * buttons plus video and microphone functionality is supported.
2970 *
2971 * The WM8958 has an advanced jack detection facility which is able to
2972 * support complex accessory detection, especially when used in
2973 * conjunction with external circuitry. In order to provide maximum
2974 * flexiblity a callback is provided which allows a completely custom
2975 * detection algorithm.
2976 */
2977 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2978 wm8958_micdet_cb cb, void *cb_data)
2979 {
2980 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2981 struct wm8994 *control = codec->control_data;
2982
2983 if (control->type != WM8958)
2984 return -EINVAL;
2985
2986 if (jack) {
2987 if (!cb) {
2988 dev_dbg(codec->dev, "Using default micdet callback\n");
2989 cb = wm8958_default_micdet;
2990 cb_data = codec;
2991 }
2992
2993 wm8994->micdet[0].jack = jack;
2994 wm8994->jack_cb = cb;
2995 wm8994->jack_cb_data = cb_data;
2996
2997 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2998 WM8958_MICD_ENA, WM8958_MICD_ENA);
2999 } else {
3000 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3001 WM8958_MICD_ENA, 0);
3002 }
3003
3004 return 0;
3005 }
3006 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3007
3008 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3009 {
3010 struct wm8994_priv *wm8994 = data;
3011 struct snd_soc_codec *codec = wm8994->codec;
3012 int reg;
3013
3014 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3015 if (reg < 0) {
3016 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
3017 reg);
3018 return IRQ_NONE;
3019 }
3020
3021 if (!(reg & WM8958_MICD_VALID)) {
3022 dev_dbg(codec->dev, "Mic detect data not valid\n");
3023 goto out;
3024 }
3025
3026 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3027 trace_snd_soc_jack_irq(dev_name(codec->dev));
3028 #endif
3029
3030 if (wm8994->jack_cb)
3031 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3032 else
3033 dev_warn(codec->dev, "Accessory detection with no callback\n");
3034
3035 out:
3036 return IRQ_HANDLED;
3037 }
3038
3039 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3040 {
3041 struct snd_soc_codec *codec = data;
3042
3043 dev_err(codec->dev, "FIFO error\n");
3044
3045 return IRQ_HANDLED;
3046 }
3047
3048 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3049 {
3050 struct snd_soc_codec *codec = data;
3051
3052 dev_err(codec->dev, "Thermal warning\n");
3053
3054 return IRQ_HANDLED;
3055 }
3056
3057 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3058 {
3059 struct snd_soc_codec *codec = data;
3060
3061 dev_crit(codec->dev, "Thermal shutdown\n");
3062
3063 return IRQ_HANDLED;
3064 }
3065
3066 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3067 {
3068 struct wm8994 *control;
3069 struct wm8994_priv *wm8994;
3070 struct snd_soc_dapm_context *dapm = &codec->dapm;
3071 int ret, i;
3072
3073 codec->control_data = dev_get_drvdata(codec->dev->parent);
3074 control = codec->control_data;
3075
3076 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
3077 if (wm8994 == NULL)
3078 return -ENOMEM;
3079 snd_soc_codec_set_drvdata(codec, wm8994);
3080
3081 wm8994->pdata = dev_get_platdata(codec->dev->parent);
3082 wm8994->codec = codec;
3083
3084 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3085 init_completion(&wm8994->fll_locked[i]);
3086
3087 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3088 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3089 else if (wm8994->pdata && wm8994->pdata->irq_base)
3090 wm8994->micdet_irq = wm8994->pdata->irq_base +
3091 WM8994_IRQ_MIC1_DET;
3092
3093 pm_runtime_enable(codec->dev);
3094 pm_runtime_resume(codec->dev);
3095
3096 /* Read our current status back from the chip - we don't want to
3097 * reset as this may interfere with the GPIO or LDO operation. */
3098 for (i = 0; i < WM8994_CACHE_SIZE; i++) {
3099 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
3100 continue;
3101
3102 ret = wm8994_reg_read(codec->control_data, i);
3103 if (ret <= 0)
3104 continue;
3105
3106 ret = snd_soc_cache_write(codec, i, ret);
3107 if (ret != 0) {
3108 dev_err(codec->dev,
3109 "Failed to initialise cache for 0x%x: %d\n",
3110 i, ret);
3111 goto err;
3112 }
3113 }
3114
3115 /* Set revision-specific configuration */
3116 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3117 switch (control->type) {
3118 case WM8994:
3119 switch (wm8994->revision) {
3120 case 2:
3121 case 3:
3122 wm8994->hubs.dcs_codes_l = -5;
3123 wm8994->hubs.dcs_codes_r = -5;
3124 wm8994->hubs.hp_startup_mode = 1;
3125 wm8994->hubs.dcs_readback_mode = 1;
3126 wm8994->hubs.series_startup = 1;
3127 break;
3128 default:
3129 wm8994->hubs.dcs_readback_mode = 2;
3130 break;
3131 }
3132 break;
3133
3134 case WM8958:
3135 wm8994->hubs.dcs_readback_mode = 1;
3136 break;
3137
3138 default:
3139 break;
3140 }
3141
3142 wm8994_request_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR,
3143 wm8994_fifo_error, "FIFO error", codec);
3144 wm8994_request_irq(wm8994->control_data, WM8994_IRQ_TEMP_WARN,
3145 wm8994_temp_warn, "Thermal warning", codec);
3146 wm8994_request_irq(wm8994->control_data, WM8994_IRQ_TEMP_SHUT,
3147 wm8994_temp_shut, "Thermal shutdown", codec);
3148
3149 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3150 wm_hubs_dcs_done, "DC servo done",
3151 &wm8994->hubs);
3152 if (ret == 0)
3153 wm8994->hubs.dcs_done_irq = true;
3154
3155 switch (control->type) {
3156 case WM8994:
3157 if (wm8994->micdet_irq) {
3158 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3159 wm8994_mic_irq,
3160 IRQF_TRIGGER_RISING,
3161 "Mic1 detect",
3162 wm8994);
3163 if (ret != 0)
3164 dev_warn(codec->dev,
3165 "Failed to request Mic1 detect IRQ: %d\n",
3166 ret);
3167 }
3168
3169 ret = wm8994_request_irq(codec->control_data,
3170 WM8994_IRQ_MIC1_SHRT,
3171 wm8994_mic_irq, "Mic 1 short",
3172 wm8994);
3173 if (ret != 0)
3174 dev_warn(codec->dev,
3175 "Failed to request Mic1 short IRQ: %d\n",
3176 ret);
3177
3178 ret = wm8994_request_irq(codec->control_data,
3179 WM8994_IRQ_MIC2_DET,
3180 wm8994_mic_irq, "Mic 2 detect",
3181 wm8994);
3182 if (ret != 0)
3183 dev_warn(codec->dev,
3184 "Failed to request Mic2 detect IRQ: %d\n",
3185 ret);
3186
3187 ret = wm8994_request_irq(codec->control_data,
3188 WM8994_IRQ_MIC2_SHRT,
3189 wm8994_mic_irq, "Mic 2 short",
3190 wm8994);
3191 if (ret != 0)
3192 dev_warn(codec->dev,
3193 "Failed to request Mic2 short IRQ: %d\n",
3194 ret);
3195 break;
3196
3197 case WM8958:
3198 if (wm8994->micdet_irq) {
3199 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3200 wm8958_mic_irq,
3201 IRQF_TRIGGER_RISING,
3202 "Mic detect",
3203 wm8994);
3204 if (ret != 0)
3205 dev_warn(codec->dev,
3206 "Failed to request Mic detect IRQ: %d\n",
3207 ret);
3208 }
3209 }
3210
3211 wm8994->fll_locked_irq = true;
3212 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3213 ret = wm8994_request_irq(codec->control_data,
3214 WM8994_IRQ_FLL1_LOCK + i,
3215 wm8994_fll_locked_irq, "FLL lock",
3216 &wm8994->fll_locked[i]);
3217 if (ret != 0)
3218 wm8994->fll_locked_irq = false;
3219 }
3220
3221 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3222 * configured on init - if a system wants to do this dynamically
3223 * at runtime we can deal with that then.
3224 */
3225 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3226 if (ret < 0) {
3227 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3228 goto err_irq;
3229 }
3230 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3231 wm8994->lrclk_shared[0] = 1;
3232 wm8994_dai[0].symmetric_rates = 1;
3233 } else {
3234 wm8994->lrclk_shared[0] = 0;
3235 }
3236
3237 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3238 if (ret < 0) {
3239 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3240 goto err_irq;
3241 }
3242 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3243 wm8994->lrclk_shared[1] = 1;
3244 wm8994_dai[1].symmetric_rates = 1;
3245 } else {
3246 wm8994->lrclk_shared[1] = 0;
3247 }
3248
3249 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3250
3251 /* Latch volume updates (right only; we always do left then right). */
3252 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3253 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3254 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3255 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3256 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3257 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3258 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3259 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3260 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3261 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3262 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3263 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3264 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3265 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3266 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3267 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3268 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3269 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3270 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3271 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3272 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3273 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3274 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3275 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3276 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3277 WM8994_DAC1_VU, WM8994_DAC1_VU);
3278 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3279 WM8994_DAC1_VU, WM8994_DAC1_VU);
3280 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3281 WM8994_DAC2_VU, WM8994_DAC2_VU);
3282 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3283 WM8994_DAC2_VU, WM8994_DAC2_VU);
3284
3285 /* Set the low bit of the 3D stereo depth so TLV matches */
3286 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3287 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3288 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3289 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3290 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3291 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3292 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3293 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3294 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3295
3296 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3297 * use this; it only affects behaviour on idle TDM clock
3298 * cycles. */
3299 switch (control->type) {
3300 case WM8994:
3301 case WM8958:
3302 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3303 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3304 break;
3305 default:
3306 break;
3307 }
3308
3309 wm8994_update_class_w(codec);
3310
3311 wm8994_handle_pdata(wm8994);
3312
3313 wm_hubs_add_analogue_controls(codec);
3314 snd_soc_add_controls(codec, wm8994_snd_controls,
3315 ARRAY_SIZE(wm8994_snd_controls));
3316 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3317 ARRAY_SIZE(wm8994_dapm_widgets));
3318
3319 switch (control->type) {
3320 case WM8994:
3321 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3322 ARRAY_SIZE(wm8994_specific_dapm_widgets));
3323 if (wm8994->revision < 4) {
3324 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3325 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3326 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3327 ARRAY_SIZE(wm8994_adc_revd_widgets));
3328 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3329 ARRAY_SIZE(wm8994_dac_revd_widgets));
3330 } else {
3331 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3332 ARRAY_SIZE(wm8994_lateclk_widgets));
3333 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3334 ARRAY_SIZE(wm8994_adc_widgets));
3335 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3336 ARRAY_SIZE(wm8994_dac_widgets));
3337 }
3338 break;
3339 case WM8958:
3340 snd_soc_add_controls(codec, wm8958_snd_controls,
3341 ARRAY_SIZE(wm8958_snd_controls));
3342 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3343 ARRAY_SIZE(wm8958_dapm_widgets));
3344 if (wm8994->revision < 1) {
3345 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3346 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3347 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3348 ARRAY_SIZE(wm8994_adc_revd_widgets));
3349 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3350 ARRAY_SIZE(wm8994_dac_revd_widgets));
3351 } else {
3352 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3353 ARRAY_SIZE(wm8994_lateclk_widgets));
3354 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3355 ARRAY_SIZE(wm8994_adc_widgets));
3356 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3357 ARRAY_SIZE(wm8994_dac_widgets));
3358 }
3359 break;
3360 }
3361
3362
3363 wm_hubs_add_analogue_routes(codec, 0, 0);
3364 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3365
3366 switch (control->type) {
3367 case WM8994:
3368 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3369 ARRAY_SIZE(wm8994_intercon));
3370
3371 if (wm8994->revision < 4) {
3372 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3373 ARRAY_SIZE(wm8994_revd_intercon));
3374 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3375 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3376 } else {
3377 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3378 ARRAY_SIZE(wm8994_lateclk_intercon));
3379 }
3380 break;
3381 case WM8958:
3382 if (wm8994->revision < 1) {
3383 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3384 ARRAY_SIZE(wm8994_revd_intercon));
3385 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3386 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3387 } else {
3388 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3389 ARRAY_SIZE(wm8994_lateclk_intercon));
3390 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3391 ARRAY_SIZE(wm8958_intercon));
3392 }
3393
3394 wm8958_dsp2_init(codec);
3395 break;
3396 }
3397
3398 return 0;
3399
3400 err_irq:
3401 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3402 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3403 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
3404 if (wm8994->micdet_irq)
3405 free_irq(wm8994->micdet_irq, wm8994);
3406 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3407 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3408 &wm8994->fll_locked[i]);
3409 wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3410 &wm8994->hubs);
3411 wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
3412 wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_SHUT, codec);
3413 wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_WARN, codec);
3414 err:
3415 kfree(wm8994);
3416 return ret;
3417 }
3418
3419 static int wm8994_codec_remove(struct snd_soc_codec *codec)
3420 {
3421 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3422 struct wm8994 *control = codec->control_data;
3423 int i;
3424
3425 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3426
3427 pm_runtime_disable(codec->dev);
3428
3429 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3430 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3431 &wm8994->fll_locked[i]);
3432
3433 wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3434 &wm8994->hubs);
3435 wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
3436 wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_SHUT, codec);
3437 wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_WARN, codec);
3438
3439 switch (control->type) {
3440 case WM8994:
3441 if (wm8994->micdet_irq)
3442 free_irq(wm8994->micdet_irq, wm8994);
3443 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3444 wm8994);
3445 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3446 wm8994);
3447 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3448 wm8994);
3449 break;
3450
3451 case WM8958:
3452 if (wm8994->micdet_irq)
3453 free_irq(wm8994->micdet_irq, wm8994);
3454 break;
3455 }
3456 if (wm8994->mbc)
3457 release_firmware(wm8994->mbc);
3458 if (wm8994->mbc_vss)
3459 release_firmware(wm8994->mbc_vss);
3460 if (wm8994->enh_eq)
3461 release_firmware(wm8994->enh_eq);
3462 kfree(wm8994->retune_mobile_texts);
3463 kfree(wm8994->drc_texts);
3464 kfree(wm8994);
3465
3466 return 0;
3467 }
3468
3469 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3470 .probe = wm8994_codec_probe,
3471 .remove = wm8994_codec_remove,
3472 .suspend = wm8994_suspend,
3473 .resume = wm8994_resume,
3474 .read = wm8994_read,
3475 .write = wm8994_write,
3476 .readable_register = wm8994_readable,
3477 .volatile_register = wm8994_volatile,
3478 .set_bias_level = wm8994_set_bias_level,
3479
3480 .reg_cache_size = WM8994_CACHE_SIZE,
3481 .reg_cache_default = wm8994_reg_defaults,
3482 .reg_word_size = 2,
3483 .compress_type = SND_SOC_RBTREE_COMPRESSION,
3484 };
3485
3486 static int __devinit wm8994_probe(struct platform_device *pdev)
3487 {
3488 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3489 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3490 }
3491
3492 static int __devexit wm8994_remove(struct platform_device *pdev)
3493 {
3494 snd_soc_unregister_codec(&pdev->dev);
3495 return 0;
3496 }
3497
3498 static struct platform_driver wm8994_codec_driver = {
3499 .driver = {
3500 .name = "wm8994-codec",
3501 .owner = THIS_MODULE,
3502 },
3503 .probe = wm8994_probe,
3504 .remove = __devexit_p(wm8994_remove),
3505 };
3506
3507 static __init int wm8994_init(void)
3508 {
3509 return platform_driver_register(&wm8994_codec_driver);
3510 }
3511 module_init(wm8994_init);
3512
3513 static __exit void wm8994_exit(void)
3514 {
3515 platform_driver_unregister(&wm8994_codec_driver);
3516 }
3517 module_exit(wm8994_exit);
3518
3519
3520 MODULE_DESCRIPTION("ASoC WM8994 driver");
3521 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3522 MODULE_LICENSE("GPL");
3523 MODULE_ALIAS("platform:wm8994-codec");
linux-next