sound/soc/mxs/mxs-saif.c

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/slab.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/clk.h>
  25 #include <linux/delay.h>
  26 #include <sound/core.h>
  27 #include <sound/pcm.h>
  28 #include <sound/pcm_params.h>
  29 #include <sound/soc.h>
  30 #include <mach/dma.h>
  31 #include <asm/mach-types.h>
  32 #include <mach/hardware.h>
  33 #include <mach/mxs.h>
  34
  35 #include "mxs-saif.h"
  36
  37 static struct mxs_saif *mxs_saif[2];
  38
  39 static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
  40                         int clk_id, unsigned int freq, int dir)
  41 {
  42         struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
  43
  44         switch (clk_id) {
  45         case MXS_SAIF_MCLK:
  46                 saif->mclk = freq;
  47                 break;
  48         default:
  49                 return -EINVAL;
  50         }
  51         return 0;
  52 }
  53
  54 /*
  55  * Set SAIF clock and MCLK
  56  */
  57 static int mxs_saif_set_clk(struct mxs_saif *saif,
  58                                   unsigned int mclk,
  59                                   unsigned int rate)
  60 {
  61         u32 scr;
  62         int ret;
  63
  64         scr = __raw_readl(saif->base + SAIF_CTRL);
  65         scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE;
  66         scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
  67
  68         /*
  69          * Set SAIF clock
  70          *
  71          * The SAIF clock should be either 384*fs or 512*fs.
  72          * If MCLK is used, the SAIF clk ratio need to match mclk ratio.
  73          *  For 32x mclk, set saif clk as 512*fs.
  74          *  For 48x mclk, set saif clk as 384*fs.
  75          *
  76          * If MCLK is not used, we just set saif clk to 512*fs.
  77          */
  78         if (saif->mclk_in_use) {
  79                 if (mclk % 32 == 0) {
  80                         scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
  81                         ret = clk_set_rate(saif->clk, 512 * rate);
  82                 } else if (mclk % 48 == 0) {
  83                         scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE;
  84                         ret = clk_set_rate(saif->clk, 384 * rate);
  85                 } else {
  86                         /* SAIF MCLK should be either 32x or 48x */
  87                         return -EINVAL;
  88                 }
  89         } else {
  90                 ret = clk_set_rate(saif->clk, 512 * rate);
  91                 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
  92         }
  93
  94         if (ret)
  95                 return ret;
  96
  97         if (!saif->mclk_in_use) {
  98                 __raw_writel(scr, saif->base + SAIF_CTRL);
  99                 return 0;
 100         }
 101
 102         /*
 103          * Program the over-sample rate for MCLK output
 104          *
 105          * The available MCLK range is 32x, 48x... 512x. The rate
 106          * could be from 8kHz to 192kH.
 107          */
 108         switch (mclk / rate) {
 109         case 32:
 110                 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4);
 111                 break;
 112         case 64:
 113                 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
 114                 break;
 115         case 128:
 116                 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
 117                 break;
 118         case 256:
 119                 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
 120                 break;
 121         case 512:
 122                 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
 123                 break;
 124         case 48:
 125                 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
 126                 break;
 127         case 96:
 128                 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
 129                 break;
 130         case 192:
 131                 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
 132                 break;
 133         case 384:
 134                 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
 135                 break;
 136         default:
 137                 return -EINVAL;
 138         }
 139
 140         __raw_writel(scr, saif->base + SAIF_CTRL);
 141
 142         return 0;
 143 }
 144
 145 /*
 146  * Put and disable MCLK.
 147  */
 148 int mxs_saif_put_mclk(unsigned int saif_id)
 149 {
 150         struct mxs_saif *saif = mxs_saif[saif_id];
 151         u32 stat;
 152
 153         if (!saif)
 154                 return -EINVAL;
 155
 156         stat = __raw_readl(saif->base + SAIF_STAT);
 157         if (stat & BM_SAIF_STAT_BUSY) {
 158                 dev_err(saif->dev, "error: busy\n");
 159                 return -EBUSY;
 160         }
 161
 162         clk_disable(saif->clk);
 163
 164         /* disable MCLK output */
 165         __raw_writel(BM_SAIF_CTRL_CLKGATE,
 166                 saif->base + SAIF_CTRL + MXS_SET_ADDR);
 167         __raw_writel(BM_SAIF_CTRL_RUN,
 168                 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
 169
 170         saif->mclk_in_use = 0;
 171         return 0;
 172 }
 173
 174 /*
 175  * Get MCLK and set clock rate, then enable it
 176  *
 177  * This interface is used for codecs who are using MCLK provided
 178  * by saif.
 179  */
 180 int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
 181                                         unsigned int rate)
 182 {
 183         struct mxs_saif *saif = mxs_saif[saif_id];
 184         u32 stat;
 185         int ret;
 186
 187         if (!saif)
 188                 return -EINVAL;
 189
 190         /* Clear Reset */
 191         __raw_writel(BM_SAIF_CTRL_SFTRST,
 192                 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
 193
 194         /* FIXME: need clear clk gate for register r/w */
 195         __raw_writel(BM_SAIF_CTRL_CLKGATE,
 196                 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
 197
 198         stat = __raw_readl(saif->base + SAIF_STAT);
 199         if (stat & BM_SAIF_STAT_BUSY) {
 200                 dev_err(saif->dev, "error: busy\n");
 201                 return -EBUSY;
 202         }
 203
 204         saif->mclk_in_use = 1;
 205         ret = mxs_saif_set_clk(saif, mclk, rate);
 206         if (ret)
 207                 return ret;
 208
 209         ret = clk_enable(saif->clk);
 210         if (ret)
 211                 return ret;
 212
 213         /* enable MCLK output */
 214         __raw_writel(BM_SAIF_CTRL_RUN,
 215                 saif->base + SAIF_CTRL + MXS_SET_ADDR);
 216
 217         return 0;
 218 }
 219
 220 /*
 221  * SAIF DAI format configuration.
 222  * Should only be called when port is inactive.
 223  */
 224 static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 225 {
 226         u32 scr, stat;
 227         u32 scr0;
 228         struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
 229
 230         stat = __raw_readl(saif->base + SAIF_STAT);
 231         if (stat & BM_SAIF_STAT_BUSY) {
 232                 dev_err(cpu_dai->dev, "error: busy\n");
 233                 return -EBUSY;
 234         }
 235
 236         scr0 = __raw_readl(saif->base + SAIF_CTRL);
 237         scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
 238                 & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;
 239         scr = 0;
 240
 241         /* DAI mode */
 242         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 243         case SND_SOC_DAIFMT_I2S:
 244                 /* data frame low 1clk before data */
 245                 scr |= BM_SAIF_CTRL_DELAY;
 246                 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
 247                 break;
 248         case SND_SOC_DAIFMT_LEFT_J:
 249                 /* data frame high with data */
 250                 scr &= ~BM_SAIF_CTRL_DELAY;
 251                 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
 252                 scr &= ~BM_SAIF_CTRL_JUSTIFY;
 253                 break;
 254         default:
 255                 return -EINVAL;
 256         }
 257
 258         /* DAI clock inversion */
 259         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 260         case SND_SOC_DAIFMT_IB_IF:
 261                 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
 262                 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
 263                 break;
 264         case SND_SOC_DAIFMT_IB_NF:
 265                 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
 266                 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
 267                 break;
 268         case SND_SOC_DAIFMT_NB_IF:
 269                 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
 270                 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
 271                 break;
 272         case SND_SOC_DAIFMT_NB_NF:
 273                 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
 274                 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
 275                 break;
 276         }
 277
 278         /*
 279          * Note: We simply just support master mode since SAIF TX can only
 280          * work as master.
 281          */
 282         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 283         case SND_SOC_DAIFMT_CBS_CFS:
 284                 scr &= ~BM_SAIF_CTRL_SLAVE_MODE;
 285                 __raw_writel(scr | scr0, saif->base + SAIF_CTRL);
 286                 break;
 287         default:
 288                 return -EINVAL;
 289         }
 290
 291         return 0;
 292 }
 293
 294 static int mxs_saif_startup(struct snd_pcm_substream *substream,
 295                            struct snd_soc_dai *cpu_dai)
 296 {
 297         struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
 298         snd_soc_dai_set_dma_data(cpu_dai, substream, &saif->dma_param);
 299
 300         /* clear error status to 0 for each re-open */
 301         saif->fifo_underrun = 0;
 302         saif->fifo_overrun = 0;
 303
 304         /* Clear Reset for normal operations */
 305         __raw_writel(BM_SAIF_CTRL_SFTRST,
 306                 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
 307
 308         /* clear clock gate */
 309         __raw_writel(BM_SAIF_CTRL_CLKGATE,
 310                 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
 311
 312         return 0;
 313 }
 314
 315 /*
 316  * Should only be called when port is inactive.
 317  * although can be called multiple times by upper layers.
 318  */
 319 static int mxs_saif_hw_params(struct snd_pcm_substream *substream,
 320                              struct snd_pcm_hw_params *params,
 321                              struct snd_soc_dai *cpu_dai)
 322 {
 323         struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
 324         u32 scr, stat;
 325         int ret;
 326
 327         /* mclk should already be set */
 328         if (!saif->mclk && saif->mclk_in_use) {
 329                 dev_err(cpu_dai->dev, "set mclk first\n");
 330                 return -EINVAL;
 331         }
 332
 333         stat = __raw_readl(saif->base + SAIF_STAT);
 334         if (stat & BM_SAIF_STAT_BUSY) {
 335                 dev_err(cpu_dai->dev, "error: busy\n");
 336                 return -EBUSY;
 337         }
 338
 339         /*
 340          * Set saif clk based on sample rate.
 341          * If mclk is used, we also set mclk, if not, saif->mclk is
 342          * default 0, means not used.
 343          */
 344         ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params));
 345         if (ret) {
 346                 dev_err(cpu_dai->dev, "unable to get proper clk\n");
 347                 return ret;
 348         }
 349
 350         scr = __raw_readl(saif->base + SAIF_CTRL);
 351
 352         scr &= ~BM_SAIF_CTRL_WORD_LENGTH;
 353         scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
 354         switch (params_format(params)) {
 355         case SNDRV_PCM_FORMAT_S16_LE:
 356                 scr |= BF_SAIF_CTRL_WORD_LENGTH(0);
 357                 break;
 358         case SNDRV_PCM_FORMAT_S20_3LE:
 359                 scr |= BF_SAIF_CTRL_WORD_LENGTH(4);
 360                 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
 361                 break;
 362         case SNDRV_PCM_FORMAT_S24_LE:
 363                 scr |= BF_SAIF_CTRL_WORD_LENGTH(8);
 364                 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
 365                 break;
 366         default:
 367                 return -EINVAL;
 368         }
 369
 370         /* Tx/Rx config */
 371         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 372                 /* enable TX mode */
 373                 scr &= ~BM_SAIF_CTRL_READ_MODE;
 374         } else {
 375                 /* enable RX mode */
 376                 scr |= BM_SAIF_CTRL_READ_MODE;
 377         }
 378
 379         __raw_writel(scr, saif->base + SAIF_CTRL);
 380         return 0;
 381 }
 382
 383 static int mxs_saif_prepare(struct snd_pcm_substream *substream,
 384                            struct snd_soc_dai *cpu_dai)
 385 {
 386         struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
 387
 388         /* enable FIFO error irqs */
 389         __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN,
 390                 saif->base + SAIF_CTRL + MXS_SET_ADDR);
 391
 392         return 0;
 393 }
 394
 395 static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd,
 396                                 struct snd_soc_dai *cpu_dai)
 397 {
 398         struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
 399
 400         switch (cmd) {
 401         case SNDRV_PCM_TRIGGER_START:
 402         case SNDRV_PCM_TRIGGER_RESUME:
 403         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 404                 dev_dbg(cpu_dai->dev, "start\n");
 405
 406                 clk_enable(saif->clk);
 407                 if (!saif->mclk_in_use)
 408                         __raw_writel(BM_SAIF_CTRL_RUN,
 409                                 saif->base + SAIF_CTRL + MXS_SET_ADDR);
 410
 411                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 412                         /*
 413                          * write a data to saif data register to trigger
 414                          * the transfer
 415                          */
 416                         __raw_writel(0, saif->base + SAIF_DATA);
 417                 } else {
 418                         /*
 419                          * read a data from saif data register to trigger
 420                          * the receive
 421                          */
 422                         __raw_readl(saif->base + SAIF_DATA);
 423                 }
 424
 425                 dev_dbg(cpu_dai->dev, "CTRL 0x%x STAT 0x%x\n",
 426                         __raw_readl(saif->base + SAIF_CTRL),
 427                         __raw_readl(saif->base + SAIF_STAT));
 428
 429                 break;
 430         case SNDRV_PCM_TRIGGER_SUSPEND:
 431         case SNDRV_PCM_TRIGGER_STOP:
 432         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 433                 dev_dbg(cpu_dai->dev, "stop\n");
 434
 435                 clk_disable(saif->clk);
 436                 if (!saif->mclk_in_use)
 437                         __raw_writel(BM_SAIF_CTRL_RUN,
 438                                 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
 439
 440                 break;
 441         default:
 442                 return -EINVAL;
 443         }
 444
 445         return 0;
 446 }
 447
 448 #define MXS_SAIF_RATES          SNDRV_PCM_RATE_8000_192000
 449 #define MXS_SAIF_FORMATS \
 450         (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
 451         SNDRV_PCM_FMTBIT_S24_LE)
 452
 453 static struct snd_soc_dai_ops mxs_saif_dai_ops = {
 454         .startup = mxs_saif_startup,
 455         .trigger = mxs_saif_trigger,
 456         .prepare = mxs_saif_prepare,
 457         .hw_params = mxs_saif_hw_params,
 458         .set_sysclk = mxs_saif_set_dai_sysclk,
 459         .set_fmt = mxs_saif_set_dai_fmt,
 460 };
 461
 462 static int mxs_saif_dai_probe(struct snd_soc_dai *dai)
 463 {
 464         struct mxs_saif *saif = dev_get_drvdata(dai->dev);
 465
 466         snd_soc_dai_set_drvdata(dai, saif);
 467
 468         return 0;
 469 }
 470
 471 static struct snd_soc_dai_driver mxs_saif_dai = {
 472         .name = "mxs-saif",
 473         .probe = mxs_saif_dai_probe,
 474         .playback = {
 475                 .channels_min = 2,
 476                 .channels_max = 2,
 477                 .rates = MXS_SAIF_RATES,
 478                 .formats = MXS_SAIF_FORMATS,
 479         },
 480         .capture = {
 481                 .channels_min = 2,
 482                 .channels_max = 2,
 483                 .rates = MXS_SAIF_RATES,
 484                 .formats = MXS_SAIF_FORMATS,
 485         },
 486         .ops = &mxs_saif_dai_ops,
 487 };
 488
 489 static irqreturn_t mxs_saif_irq(int irq, void *dev_id)
 490 {
 491         struct mxs_saif *saif = dev_id;
 492         unsigned int stat;
 493
 494         stat = __raw_readl(saif->base + SAIF_STAT);
 495         if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ |
 496                         BM_SAIF_STAT_FIFO_OVERFLOW_IRQ)))
 497                 return IRQ_NONE;
 498
 499         if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) {
 500                 dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun);
 501                 __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ,
 502                                 saif->base + SAIF_STAT + MXS_CLR_ADDR);
 503         }
 504
 505         if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) {
 506                 dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun);
 507                 __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ,
 508                                 saif->base + SAIF_STAT + MXS_CLR_ADDR);
 509         }
 510
 511         dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n",
 512                __raw_readl(saif->base + SAIF_CTRL),
 513                __raw_readl(saif->base + SAIF_STAT));
 514
 515         return IRQ_HANDLED;
 516 }
 517
 518 static int mxs_saif_probe(struct platform_device *pdev)
 519 {
 520         struct resource *res;
 521         struct mxs_saif *saif;
 522         int ret = 0;
 523
 524         if (pdev->id >= ARRAY_SIZE(mxs_saif))
 525                 return -EINVAL;
 526
 527         saif = kzalloc(sizeof(*saif), GFP_KERNEL);
 528         if (!saif)
 529                 return -ENOMEM;
 530
 531         mxs_saif[pdev->id] = saif;
 532
 533         saif->clk = clk_get(&pdev->dev, NULL);
 534         if (IS_ERR(saif->clk)) {
 535                 ret = PTR_ERR(saif->clk);
 536                 dev_err(&pdev->dev, "Cannot get the clock: %d\n",
 537                         ret);
 538                 goto failed_clk;
 539         }
 540
 541         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 542         if (!res) {
 543                 ret = -ENODEV;
 544                 dev_err(&pdev->dev, "failed to get io resource: %d\n",
 545                         ret);
 546                 goto failed_get_resource;
 547         }
 548
 549         if (!request_mem_region(res->start, resource_size(res), "mxs-saif")) {
 550                 dev_err(&pdev->dev, "request_mem_region failed\n");
 551                 ret = -EBUSY;
 552                 goto failed_get_resource;
 553         }
 554
 555         saif->base = ioremap(res->start, resource_size(res));
 556         if (!saif->base) {
 557                 dev_err(&pdev->dev, "ioremap failed\n");
 558                 ret = -ENODEV;
 559                 goto failed_ioremap;
 560         }
 561
 562         res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
 563         if (!res) {
 564                 ret = -ENODEV;
 565                 dev_err(&pdev->dev, "failed to get dma resource: %d\n",
 566                         ret);
 567                 goto failed_ioremap;
 568         }
 569         saif->dma_param.chan_num = res->start;
 570
 571         saif->irq = platform_get_irq(pdev, 0);
 572         if (saif->irq < 0) {
 573                 ret = saif->irq;
 574                 dev_err(&pdev->dev, "failed to get irq resource: %d\n",
 575                         ret);
 576                 goto failed_get_irq1;
 577         }
 578
 579         saif->dev = &pdev->dev;
 580         ret = request_irq(saif->irq, mxs_saif_irq, 0, "mxs-saif", saif);
 581         if (ret) {
 582                 dev_err(&pdev->dev, "failed to request irq\n");
 583                 goto failed_get_irq1;
 584         }
 585
 586         saif->dma_param.chan_irq = platform_get_irq(pdev, 1);
 587         if (saif->dma_param.chan_irq < 0) {
 588                 ret = saif->dma_param.chan_irq;
 589                 dev_err(&pdev->dev, "failed to get dma irq resource: %d\n",
 590                         ret);
 591                 goto failed_get_irq2;
 592         }
 593
 594         platform_set_drvdata(pdev, saif);
 595
 596         ret = snd_soc_register_dai(&pdev->dev, &mxs_saif_dai);
 597         if (ret) {
 598                 dev_err(&pdev->dev, "register DAI failed\n");
 599                 goto failed_register;
 600         }
 601
 602         saif->soc_platform_pdev = platform_device_alloc(
 603                                         "mxs-pcm-audio", pdev->id);
 604         if (!saif->soc_platform_pdev) {
 605                 ret = -ENOMEM;
 606                 goto failed_pdev_alloc;
 607         }
 608
 609         platform_set_drvdata(saif->soc_platform_pdev, saif);
 610         ret = platform_device_add(saif->soc_platform_pdev);
 611         if (ret) {
 612                 dev_err(&pdev->dev, "failed to add soc platform device\n");
 613                 goto failed_pdev_add;
 614         }
 615
 616         return 0;
 617
 618 failed_pdev_add:
 619         platform_device_put(saif->soc_platform_pdev);
 620 failed_pdev_alloc:
 621         snd_soc_unregister_dai(&pdev->dev);
 622 failed_register:
 623 failed_get_irq2:
 624         free_irq(saif->irq, saif);
 625 failed_get_irq1:
 626         iounmap(saif->base);
 627 failed_ioremap:
 628         release_mem_region(res->start, resource_size(res));
 629 failed_get_resource:
 630         clk_put(saif->clk);
 631 failed_clk:
 632         kfree(saif);
 633
 634         return ret;
 635 }
 636
 637 static int __devexit mxs_saif_remove(struct platform_device *pdev)
 638 {
 639         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 640         struct mxs_saif *saif = platform_get_drvdata(pdev);
 641
 642         platform_device_unregister(saif->soc_platform_pdev);
 643
 644         snd_soc_unregister_dai(&pdev->dev);
 645
 646         iounmap(saif->base);
 647         release_mem_region(res->start, resource_size(res));
 648         free_irq(saif->irq, saif);
 649
 650         clk_put(saif->clk);
 651         kfree(saif);
 652
 653         return 0;
 654 }
 655
 656 static struct platform_driver mxs_saif_driver = {
 657         .probe = mxs_saif_probe,
 658         .remove = __devexit_p(mxs_saif_remove),
 659
 660         .driver = {
 661                 .name = "mxs-saif",
 662                 .owner = THIS_MODULE,
 663         },
 664 };
 665
 666 static int __init mxs_saif_init(void)
 667 {
 668         return platform_driver_register(&mxs_saif_driver);
 669 }
 670
 671 static void __exit mxs_saif_exit(void)
 672 {
 673         platform_driver_unregister(&mxs_saif_driver);
 674 }
 675
 676 module_init(mxs_saif_init);
 677 module_exit(mxs_saif_exit);
 678 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
 679 MODULE_DESCRIPTION("MXS ASoC SAIF driver");
 680 MODULE_LICENSE("GPL");