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staging:iio: one more fix for IIO_RING_BUFFER not enabled.
[linux-2.6/next.git] / drivers / staging / dt3155v4l / dt3155v4l.c
blobfe02d22274b4d21b3f5cf69943fd49fe4a9dc8b0
1 /***************************************************************************
2 * Copyright (C) 2006-2010 by Marin Mitov *
3 * mitov@issp.bas.bg *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20
21 #include <linux/version.h>
22 #include <linux/stringify.h>
23 #include <linux/delay.h>
24 #include <linux/kthread.h>
25 #include <media/v4l2-dev.h>
26 #include <media/v4l2-ioctl.h>
27 #include <media/videobuf2-dma-contig.h>
28
29 #include "dt3155v4l.h"
30
31 #define DT3155_VENDOR_ID 0x8086
32 #define DT3155_DEVICE_ID 0x1223
33
34 /* DT3155_CHUNK_SIZE is 4M (2^22) 8 full size buffers */
35 #define DT3155_CHUNK_SIZE (1U << 22)
36
37 #define DT3155_COH_FLAGS (GFP_KERNEL | GFP_DMA32 | __GFP_COLD | __GFP_NOWARN)
38
39 #define DT3155_BUF_SIZE (768 * 576)
40
41 #ifdef CONFIG_DT3155_STREAMING
42 #define DT3155_CAPTURE_METHOD V4L2_CAP_STREAMING
43 #else
44 #define DT3155_CAPTURE_METHOD V4L2_CAP_READWRITE
45 #endif
46
47 /* global initializers (for all boards) */
48 #ifdef CONFIG_DT3155_CCIR
49 static const u8 csr2_init = VT_50HZ;
50 #define DT3155_CURRENT_NORM V4L2_STD_625_50
51 static const unsigned int img_width = 768;
52 static const unsigned int img_height = 576;
53 static const unsigned int frames_per_sec = 25;
54 static const struct v4l2_fmtdesc frame_std[] = {
55 {
56 .index = 0,
57 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
58 .flags = 0,
59 .description = "CCIR/50Hz 8 bits gray",
60 .pixelformat = V4L2_PIX_FMT_GREY,
61 },
62 };
63 #else
64 static const u8 csr2_init = VT_60HZ;
65 #define DT3155_CURRENT_NORM V4L2_STD_525_60
66 static const unsigned int img_width = 640;
67 static const unsigned int img_height = 480;
68 static const unsigned int frames_per_sec = 30;
69 static const struct v4l2_fmtdesc frame_std[] = {
70 {
71 .index = 0,
72 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
73 .flags = 0,
74 .description = "RS-170/60Hz 8 bits gray",
75 .pixelformat = V4L2_PIX_FMT_GREY,
76 },
77 };
78 #endif
79
80 #define NUM_OF_FORMATS ARRAY_SIZE(frame_std)
81
82 static u8 config_init = ACQ_MODE_EVEN;
83
84 /**
85 * read_i2c_reg - reads an internal i2c register
86 *
87 * @addr: dt3155 mmio base address
88 * @index: index (internal address) of register to read
89 * @data: pointer to byte the read data will be placed in
90 *
91 * returns: zero on success or error code
92 *
93 * This function starts reading the specified (by index) register
94 * and busy waits for the process to finish. The result is placed
95 * in a byte pointed by data.
96 */
97 static int
98 read_i2c_reg(void __iomem *addr, u8 index, u8 *data)
99 {
100 u32 tmp = index;
101
102 iowrite32((tmp<<17) | IIC_READ, addr + IIC_CSR2);
103 mmiowb();
104 udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */
105 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) {
106 /* error: NEW_CYCLE not cleared */
107 printk(KERN_ERR "dt3155: NEW_CYCLE not cleared\n");
108 return -EIO;
109 }
110 tmp = ioread32(addr + IIC_CSR1);
111 if (tmp & DIRECT_ABORT) {
112 /* error: DIRECT_ABORT set */
113 printk(KERN_ERR "dt3155: DIRECT_ABORT set\n");
114 /* reset DIRECT_ABORT bit */
115 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
116 return -EIO;
117 }
118 *data = tmp>>24;
119 return 0;
120 }
121
122 /**
123 * write_i2c_reg - writes to an internal i2c register
124 *
125 * @addr: dt3155 mmio base address
126 * @index: index (internal address) of register to read
127 * @data: data to be written
128 *
129 * returns: zero on success or error code
130 *
131 * This function starts writting the specified (by index) register
132 * and busy waits for the process to finish.
133 */
134 static int
135 write_i2c_reg(void __iomem *addr, u8 index, u8 data)
136 {
137 u32 tmp = index;
138
139 iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2);
140 mmiowb();
141 udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
142 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) {
143 /* error: NEW_CYCLE not cleared */
144 printk(KERN_ERR "dt3155: NEW_CYCLE not cleared\n");
145 return -EIO;
146 }
147 if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
148 /* error: DIRECT_ABORT set */
149 printk(KERN_ERR "dt3155: DIRECT_ABORT set\n");
150 /* reset DIRECT_ABORT bit */
151 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
152 return -EIO;
153 }
154 return 0;
155 }
156
157 /**
158 * write_i2c_reg_nowait - writes to an internal i2c register
159 *
160 * @addr: dt3155 mmio base address
161 * @index: index (internal address) of register to read
162 * @data: data to be written
163 *
164 * This function starts writting the specified (by index) register
165 * and then returns.
166 */
167 static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data)
168 {
169 u32 tmp = index;
170
171 iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2);
172 mmiowb();
173 }
174
175 /**
176 * wait_i2c_reg - waits the read/write to finish
177 *
178 * @addr: dt3155 mmio base address
179 *
180 * returns: zero on success or error code
181 *
182 * This function waits reading/writting to finish.
183 */
184 static int wait_i2c_reg(void __iomem *addr)
185 {
186 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
187 udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
188 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) {
189 /* error: NEW_CYCLE not cleared */
190 printk(KERN_ERR "dt3155: NEW_CYCLE not cleared\n");
191 return -EIO;
192 }
193 if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
194 /* error: DIRECT_ABORT set */
195 printk(KERN_ERR "dt3155: DIRECT_ABORT set\n");
196 /* reset DIRECT_ABORT bit */
197 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
198 return -EIO;
199 }
200 return 0;
201 }
202
203 static int
204 dt3155_start_acq(struct dt3155_priv *pd)
205 {
206 struct vb2_buffer *vb = pd->curr_buf;
207 dma_addr_t dma_addr;
208
209 dma_addr = vb2_dma_contig_plane_paddr(vb, 0);
210 iowrite32(dma_addr, pd->regs + EVEN_DMA_START);
211 iowrite32(dma_addr + img_width, pd->regs + ODD_DMA_START);
212 iowrite32(img_width, pd->regs + EVEN_DMA_STRIDE);
213 iowrite32(img_width, pd->regs + ODD_DMA_STRIDE);
214 /* enable interrupts, clear all irq flags */
215 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
216 FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
217 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
218 FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD,
219 pd->regs + CSR1);
220 wait_i2c_reg(pd->regs);
221 write_i2c_reg(pd->regs, CONFIG, pd->config);
222 write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);
223 write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);
224
225 /* start the board */
226 write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD);
227 return 0; /* success */
228 }
229
230 /*
231 * driver-specific callbacks (vb2_ops)
232 */
233 static int
234 dt3155_queue_setup(struct vb2_queue *q, unsigned int *num_buffers,
235 unsigned int *num_planes, unsigned long sizes[],
236 void *alloc_ctxs[])
237 {
238 struct dt3155_priv *pd = vb2_get_drv_priv(q);
239 void *ret;
240
241 if (*num_buffers == 0)
242 *num_buffers = 1;
243 *num_planes = 1;
244 sizes[0] = img_width * img_height;
245 if (pd->q->alloc_ctx[0])
246 return 0;
247 ret = vb2_dma_contig_init_ctx(&pd->pdev->dev);
248 if (IS_ERR(ret))
249 return PTR_ERR(ret);
250 pd->q->alloc_ctx[0] = ret;
251 return 0;
252 }
253
254 static void
255 dt3155_wait_prepare(struct vb2_queue *q)
256 {
257 struct dt3155_priv *pd = vb2_get_drv_priv(q);
258
259 mutex_unlock(pd->vdev->lock);
260 }
261
262 static void
263 dt3155_wait_finish(struct vb2_queue *q)
264 {
265 struct dt3155_priv *pd = vb2_get_drv_priv(q);
266
267 mutex_lock(pd->vdev->lock);
268 }
269
270 static int
271 dt3155_buf_prepare(struct vb2_buffer *vb)
272 {
273 vb2_set_plane_payload(vb, 0, img_width * img_height);
274 return 0;
275 }
276
277 static int
278 dt3155_start_streaming(struct vb2_queue *q)
279 {
280 return 0;
281 }
282
283 static int
284 dt3155_stop_streaming(struct vb2_queue *q)
285 {
286 struct dt3155_priv *pd = vb2_get_drv_priv(q);
287 struct vb2_buffer *vb;
288
289 spin_lock_irq(&pd->lock);
290 while (!list_empty(&pd->dmaq)) {
291 vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry);
292 list_del(&vb->done_entry);
293 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
294 }
295 spin_unlock_irq(&pd->lock);
296 msleep(45); /* irq hendler will stop the hardware */
297 return 0;
298 }
299
300 static void
301 dt3155_buf_queue(struct vb2_buffer *vb)
302 {
303 struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
304
305 /* pd->q->streaming = 1 when dt3155_buf_queue() is invoked */
306 spin_lock_irq(&pd->lock);
307 if (pd->curr_buf)
308 list_add_tail(&vb->done_entry, &pd->dmaq);
309 else {
310 pd->curr_buf = vb;
311 dt3155_start_acq(pd);
312 }
313 spin_unlock_irq(&pd->lock);
314 }
315 /*
316 * end driver-specific callbacks
317 */
318
319 const struct vb2_ops q_ops = {
320 .queue_setup = dt3155_queue_setup,
321 .wait_prepare = dt3155_wait_prepare,
322 .wait_finish = dt3155_wait_finish,
323 .buf_prepare = dt3155_buf_prepare,
324 .start_streaming = dt3155_start_streaming,
325 .stop_streaming = dt3155_stop_streaming,
326 .buf_queue = dt3155_buf_queue,
327 };
328
329 static irqreturn_t
330 dt3155_irq_handler_even(int irq, void *dev_id)
331 {
332 struct dt3155_priv *ipd = dev_id;
333 struct vb2_buffer *ivb;
334 dma_addr_t dma_addr;
335 u32 tmp;
336
337 tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD);
338 if (!tmp)
339 return IRQ_NONE; /* not our irq */
340 if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) {
341 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START,
342 ipd->regs + INT_CSR);
343 ipd->field_count++;
344 return IRQ_HANDLED; /* start of field irq */
345 }
346 if ((tmp & FLD_START) && (tmp & FLD_END_ODD)) {
347 if (!ipd->stats.start_before_end++)
348 printk(KERN_ERR "dt3155: irq: START before END\n");
349 }
350 /* check for corrupted fields */
351 /* write_i2c_reg(ipd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE); */
352 /* write_i2c_reg(ipd->regs, ODD_CSR, CSR_ERROR | CSR_DONE); */
353 tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD);
354 if (tmp) {
355 if (!ipd->stats.corrupted_fields++)
356 printk(KERN_ERR "dt3155: corrupted field %u\n", tmp);
357 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
358 FLD_DN_ODD | FLD_DN_EVEN |
359 CAP_CONT_EVEN | CAP_CONT_ODD,
360 ipd->regs + CSR1);
361 mmiowb();
362 }
363
364 spin_lock(&ipd->lock);
365 if (ipd->curr_buf) {
366 do_gettimeofday(&ipd->curr_buf->v4l2_buf.timestamp);
367 ipd->curr_buf->v4l2_buf.sequence = (ipd->field_count) >> 1;
368 vb2_buffer_done(ipd->curr_buf, VB2_BUF_STATE_DONE);
369 }
370
371 if (!ipd->q->streaming || list_empty(&ipd->dmaq))
372 goto stop_dma;
373 ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry);
374 list_del(&ivb->done_entry);
375 ipd->curr_buf = ivb;
376 dma_addr = vb2_dma_contig_plane_paddr(ivb, 0);
377 iowrite32(dma_addr, ipd->regs + EVEN_DMA_START);
378 iowrite32(dma_addr + img_width, ipd->regs + ODD_DMA_START);
379 iowrite32(img_width, ipd->regs + EVEN_DMA_STRIDE);
380 iowrite32(img_width, ipd->regs + ODD_DMA_STRIDE);
381 mmiowb();
382 /* enable interrupts, clear all irq flags */
383 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
384 FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
385 spin_unlock(&ipd->lock);
386 return IRQ_HANDLED;
387
388 stop_dma:
389 ipd->curr_buf = NULL;
390 /* stop the board */
391 write_i2c_reg_nowait(ipd->regs, CSR2, ipd->csr2);
392 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
393 FLD_DN_ODD | FLD_DN_EVEN, ipd->regs + CSR1);
394 /* disable interrupts, clear all irq flags */
395 iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
396 spin_unlock(&ipd->lock);
397 return IRQ_HANDLED;
398 }
399
400 static int
401 dt3155_open(struct file *filp)
402 {
403 int ret = 0;
404 struct dt3155_priv *pd = video_drvdata(filp);
405
406 printk(KERN_INFO "dt3155: open(): minor: %i, users: %i\n",
407 pd->vdev->minor, pd->users);
408
409 if (!pd->users) {
410 pd->q = kzalloc(sizeof(*pd->q), GFP_KERNEL);
411 if (!pd->q) {
412 printk(KERN_ERR "dt3155: error: alloc queue\n");
413 ret = -ENOMEM;
414 goto err_alloc_queue;
415 }
416 pd->q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
417 pd->q->io_modes = VB2_READ | VB2_MMAP;
418 pd->q->ops = &q_ops;
419 pd->q->mem_ops = &vb2_dma_contig_memops;
420 pd->q->drv_priv = pd;
421 pd->curr_buf = NULL;
422 pd->field_count = 0;
423 vb2_queue_init(pd->q); /* cannot fail */
424 INIT_LIST_HEAD(&pd->dmaq);
425 spin_lock_init(&pd->lock);
426 /* disable all irqs, clear all irq flags */
427 iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD,
428 pd->regs + INT_CSR);
429 pd->irq_handler = dt3155_irq_handler_even;
430 ret = request_irq(pd->pdev->irq, pd->irq_handler,
431 IRQF_SHARED, DT3155_NAME, pd);
432 if (ret) {
433 printk(KERN_ERR "dt3155: error: request_irq\n");
434 goto err_request_irq;
435 }
436 }
437 pd->users++;
438 return 0; /* success */
439 err_request_irq:
440 kfree(pd->q);
441 pd->q = NULL;
442 err_alloc_queue:
443 return ret;
444 }
445
446 static int
447 dt3155_release(struct file *filp)
448 {
449 struct dt3155_priv *pd = video_drvdata(filp);
450
451 printk(KERN_INFO "dt3155: release(): minor: %i, users: %i\n",
452 pd->vdev->minor, pd->users - 1);
453
454 pd->users--;
455 BUG_ON(pd->users < 0);
456 if (!pd->users) {
457 vb2_queue_release(pd->q);
458 free_irq(pd->pdev->irq, pd);
459 if (pd->q->alloc_ctx[0])
460 vb2_dma_contig_cleanup_ctx(pd->q->alloc_ctx[0]);
461 kfree(pd->q);
462 pd->q = NULL;
463 }
464 return 0;
465 }
466
467 static ssize_t
468 dt3155_read(struct file *filp, char __user *user, size_t size, loff_t *loff)
469 {
470 struct dt3155_priv *pd = video_drvdata(filp);
471
472 return vb2_read(pd->q, user, size, loff, filp->f_flags & O_NONBLOCK);
473 }
474
475 static unsigned int
476 dt3155_poll(struct file *filp, struct poll_table_struct *polltbl)
477 {
478 struct dt3155_priv *pd = video_drvdata(filp);
479
480 return vb2_poll(pd->q, filp, polltbl);
481 }
482
483 static int
484 dt3155_mmap(struct file *filp, struct vm_area_struct *vma)
485 {
486 struct dt3155_priv *pd = video_drvdata(filp);
487
488 return vb2_mmap(pd->q, vma);
489 }
490
491 static const struct v4l2_file_operations dt3155_fops = {
492 .owner = THIS_MODULE,
493 .open = dt3155_open,
494 .release = dt3155_release,
495 .read = dt3155_read,
496 .poll = dt3155_poll,
497 .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */
498 .mmap = dt3155_mmap,
499 };
500
501 static int
502 dt3155_ioc_streamon(struct file *filp, void *p, enum v4l2_buf_type type)
503 {
504 struct dt3155_priv *pd = video_drvdata(filp);
505
506 return vb2_streamon(pd->q, type);
507 }
508
509 static int
510 dt3155_ioc_streamoff(struct file *filp, void *p, enum v4l2_buf_type type)
511 {
512 struct dt3155_priv *pd = video_drvdata(filp);
513
514 return vb2_streamoff(pd->q, type);
515 }
516
517 static int
518 dt3155_ioc_querycap(struct file *filp, void *p, struct v4l2_capability *cap)
519 {
520 struct dt3155_priv *pd = video_drvdata(filp);
521
522 strcpy(cap->driver, DT3155_NAME);
523 strcpy(cap->card, DT3155_NAME " frame grabber");
524 sprintf(cap->bus_info, "PCI:%s", pci_name(pd->pdev));
525 cap->version =
526 KERNEL_VERSION(DT3155_VER_MAJ, DT3155_VER_MIN, DT3155_VER_EXT);
527 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE |
528 DT3155_CAPTURE_METHOD;
529 return 0;
530 }
531
532 static int
533 dt3155_ioc_enum_fmt_vid_cap(struct file *filp, void *p, struct v4l2_fmtdesc *f)
534 {
535 if (f->index >= NUM_OF_FORMATS)
536 return -EINVAL;
537 *f = frame_std[f->index];
538 return 0;
539 }
540
541 static int
542 dt3155_ioc_g_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
543 {
544 if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
545 return -EINVAL;
546 f->fmt.pix.width = img_width;
547 f->fmt.pix.height = img_height;
548 f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY;
549 f->fmt.pix.field = V4L2_FIELD_NONE;
550 f->fmt.pix.bytesperline = f->fmt.pix.width;
551 f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height;
552 f->fmt.pix.colorspace = 0;
553 f->fmt.pix.priv = 0;
554 return 0;
555 }
556
557 static int
558 dt3155_ioc_try_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
559 {
560 if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
561 return -EINVAL;
562 if (f->fmt.pix.width == img_width &&
563 f->fmt.pix.height == img_height &&
564 f->fmt.pix.pixelformat == V4L2_PIX_FMT_GREY &&
565 f->fmt.pix.field == V4L2_FIELD_NONE &&
566 f->fmt.pix.bytesperline == f->fmt.pix.width &&
567 f->fmt.pix.sizeimage == f->fmt.pix.width * f->fmt.pix.height)
568 return 0;
569 else
570 return -EINVAL;
571 }
572
573 static int
574 dt3155_ioc_s_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
575 {
576 return dt3155_ioc_g_fmt_vid_cap(filp, p, f);
577 }
578
579 static int
580 dt3155_ioc_reqbufs(struct file *filp, void *p, struct v4l2_requestbuffers *b)
581 {
582 struct dt3155_priv *pd = video_drvdata(filp);
583
584 return vb2_reqbufs(pd->q, b);
585 }
586
587 static int
588 dt3155_ioc_querybuf(struct file *filp, void *p, struct v4l2_buffer *b)
589 {
590 struct dt3155_priv *pd = video_drvdata(filp);
591
592 return vb2_querybuf(pd->q, b);
593 }
594
595 static int
596 dt3155_ioc_qbuf(struct file *filp, void *p, struct v4l2_buffer *b)
597 {
598 struct dt3155_priv *pd = video_drvdata(filp);
599
600 return vb2_qbuf(pd->q, b);
601 }
602
603 static int
604 dt3155_ioc_dqbuf(struct file *filp, void *p, struct v4l2_buffer *b)
605 {
606 struct dt3155_priv *pd = video_drvdata(filp);
607
608 return vb2_dqbuf(pd->q, b, filp->f_flags & O_NONBLOCK);
609 }
610
611 static int
612 dt3155_ioc_querystd(struct file *filp, void *p, v4l2_std_id *norm)
613 {
614 *norm = DT3155_CURRENT_NORM;
615 return 0;
616 }
617
618 static int
619 dt3155_ioc_g_std(struct file *filp, void *p, v4l2_std_id *norm)
620 {
621 *norm = DT3155_CURRENT_NORM;
622 return 0;
623 }
624
625 static int
626 dt3155_ioc_s_std(struct file *filp, void *p, v4l2_std_id *norm)
627 {
628 if (*norm & DT3155_CURRENT_NORM)
629 return 0;
630 return -EINVAL;
631 }
632
633 static int
634 dt3155_ioc_enum_input(struct file *filp, void *p, struct v4l2_input *input)
635 {
636 if (input->index)
637 return -EINVAL;
638 strcpy(input->name, "Coax in");
639 input->type = V4L2_INPUT_TYPE_CAMERA;
640 /*
641 * FIXME: input->std = 0 according to v4l2 API
642 * VIDIOC_G_STD, VIDIOC_S_STD, VIDIOC_QUERYSTD and VIDIOC_ENUMSTD
643 * should return -EINVAL
644 */
645 input->std = DT3155_CURRENT_NORM;
646 input->status = 0;/* FIXME: add sync detection & V4L2_IN_ST_NO_H_LOCK */
647 return 0;
648 }
649
650 static int
651 dt3155_ioc_g_input(struct file *filp, void *p, unsigned int *i)
652 {
653 *i = 0;
654 return 0;
655 }
656
657 static int
658 dt3155_ioc_s_input(struct file *filp, void *p, unsigned int i)
659 {
660 if (i)
661 return -EINVAL;
662 return 0;
663 }
664
665 static int
666 dt3155_ioc_g_parm(struct file *filp, void *p, struct v4l2_streamparm *parms)
667 {
668 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
669 return -EINVAL;
670 parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
671 parms->parm.capture.capturemode = 0;
672 parms->parm.capture.timeperframe.numerator = 1001;
673 parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000;
674 parms->parm.capture.extendedmode = 0;
675 parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */
676 return 0;
677 }
678
679 static int
680 dt3155_ioc_s_parm(struct file *filp, void *p, struct v4l2_streamparm *parms)
681 {
682 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
683 return -EINVAL;
684 parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
685 parms->parm.capture.capturemode = 0;
686 parms->parm.capture.timeperframe.numerator = 1001;
687 parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000;
688 parms->parm.capture.extendedmode = 0;
689 parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */
690 return 0;
691 }
692
693 static const struct v4l2_ioctl_ops dt3155_ioctl_ops = {
694 .vidioc_streamon = dt3155_ioc_streamon,
695 .vidioc_streamoff = dt3155_ioc_streamoff,
696 .vidioc_querycap = dt3155_ioc_querycap,
697 /*
698 .vidioc_g_priority = dt3155_ioc_g_priority,
699 .vidioc_s_priority = dt3155_ioc_s_priority,
700 */
701 .vidioc_enum_fmt_vid_cap = dt3155_ioc_enum_fmt_vid_cap,
702 .vidioc_try_fmt_vid_cap = dt3155_ioc_try_fmt_vid_cap,
703 .vidioc_g_fmt_vid_cap = dt3155_ioc_g_fmt_vid_cap,
704 .vidioc_s_fmt_vid_cap = dt3155_ioc_s_fmt_vid_cap,
705 .vidioc_reqbufs = dt3155_ioc_reqbufs,
706 .vidioc_querybuf = dt3155_ioc_querybuf,
707 .vidioc_qbuf = dt3155_ioc_qbuf,
708 .vidioc_dqbuf = dt3155_ioc_dqbuf,
709 .vidioc_querystd = dt3155_ioc_querystd,
710 .vidioc_g_std = dt3155_ioc_g_std,
711 .vidioc_s_std = dt3155_ioc_s_std,
712 .vidioc_enum_input = dt3155_ioc_enum_input,
713 .vidioc_g_input = dt3155_ioc_g_input,
714 .vidioc_s_input = dt3155_ioc_s_input,
715 /*
716 .vidioc_queryctrl = dt3155_ioc_queryctrl,
717 .vidioc_g_ctrl = dt3155_ioc_g_ctrl,
718 .vidioc_s_ctrl = dt3155_ioc_s_ctrl,
719 .vidioc_querymenu = dt3155_ioc_querymenu,
720 .vidioc_g_ext_ctrls = dt3155_ioc_g_ext_ctrls,
721 .vidioc_s_ext_ctrls = dt3155_ioc_s_ext_ctrls,
722 */
723 .vidioc_g_parm = dt3155_ioc_g_parm,
724 .vidioc_s_parm = dt3155_ioc_s_parm,
725 /*
726 .vidioc_cropcap = dt3155_ioc_cropcap,
727 .vidioc_g_crop = dt3155_ioc_g_crop,
728 .vidioc_s_crop = dt3155_ioc_s_crop,
729 .vidioc_enum_framesizes = dt3155_ioc_enum_framesizes,
730 .vidioc_enum_frameintervals = dt3155_ioc_enum_frameintervals,
731 */
732 };
733
734 static int __devinit
735 dt3155_init_board(struct pci_dev *pdev)
736 {
737 struct dt3155_priv *pd = pci_get_drvdata(pdev);
738 void *buf_cpu;
739 dma_addr_t buf_dma;
740 int i;
741 u8 tmp;
742
743 pci_set_master(pdev); /* dt3155 needs it */
744
745 /* resetting the adapter */
746 iowrite32(FLD_CRPT_ODD | FLD_CRPT_EVEN | FLD_DN_ODD | FLD_DN_EVEN,
747 pd->regs + CSR1);
748 mmiowb();
749 msleep(20);
750
751 /* initializing adaper registers */
752 iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
753 mmiowb();
754 iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT);
755 iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT);
756 iowrite32(0x00000020, pd->regs + FIFO_TRIGER);
757 iowrite32(0x00000103, pd->regs + XFER_MODE);
758 iowrite32(0, pd->regs + RETRY_WAIT_CNT);
759 iowrite32(0, pd->regs + INT_CSR);
760 iowrite32(1, pd->regs + EVEN_FLD_MASK);
761 iowrite32(1, pd->regs + ODD_FLD_MASK);
762 iowrite32(0, pd->regs + MASK_LENGTH);
763 iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT);
764 iowrite32(0x01010101, pd->regs + IIC_CLK_DUR);
765 mmiowb();
766
767 /* verifying that we have a DT3155 board (not just a SAA7116 chip) */
768 read_i2c_reg(pd->regs, DT_ID, &tmp);
769 if (tmp != DT3155_ID)
770 return -ENODEV;
771
772 /* initialize AD LUT */
773 write_i2c_reg(pd->regs, AD_ADDR, 0);
774 for (i = 0; i < 256; i++)
775 write_i2c_reg(pd->regs, AD_LUT, i);
776
777 /* initialize ADC references */
778 /* FIXME: pos_ref & neg_ref depend on VT_50HZ */
779 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
780 write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
781 write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF);
782 write_i2c_reg(pd->regs, AD_CMD, 34);
783 write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF);
784 write_i2c_reg(pd->regs, AD_CMD, 0);
785
786 /* initialize PM LUT */
787 write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM);
788 for (i = 0; i < 256; i++) {
789 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
790 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
791 }
792 write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL);
793 for (i = 0; i < 256; i++) {
794 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
795 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
796 }
797 write_i2c_reg(pd->regs, CONFIG, pd->config); /* ACQ_MODE_EVEN */
798
799 /* select chanel 1 for input and set sync level */
800 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
801 write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
802
803 /* allocate memory, and initialize the DMA machine */
804 buf_cpu = dma_alloc_coherent(&pdev->dev, DT3155_BUF_SIZE, &buf_dma,
805 GFP_KERNEL);
806 if (!buf_cpu) {
807 printk(KERN_ERR "dt3155: dma_alloc_coherent "
808 "(in dt3155_init_board) failed\n");
809 return -ENOMEM;
810 }
811 iowrite32(buf_dma, pd->regs + EVEN_DMA_START);
812 iowrite32(buf_dma, pd->regs + ODD_DMA_START);
813 iowrite32(0, pd->regs + EVEN_DMA_STRIDE);
814 iowrite32(0, pd->regs + ODD_DMA_STRIDE);
815
816 /* Perform a pseudo even field acquire */
817 iowrite32(FIFO_EN | SRST | CAP_CONT_ODD, pd->regs + CSR1);
818 write_i2c_reg(pd->regs, CSR2, pd->csr2 | SYNC_SNTL);
819 write_i2c_reg(pd->regs, CONFIG, pd->config);
820 write_i2c_reg(pd->regs, EVEN_CSR, CSR_SNGL);
821 write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | SYNC_SNTL);
822 msleep(100);
823 read_i2c_reg(pd->regs, CSR2, &tmp);
824 write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE);
825 write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE);
826 write_i2c_reg(pd->regs, CSR2, pd->csr2);
827 iowrite32(FIFO_EN | SRST | FLD_DN_EVEN | FLD_DN_ODD, pd->regs + CSR1);
828
829 /* deallocate memory */
830 dma_free_coherent(&pdev->dev, DT3155_BUF_SIZE, buf_cpu, buf_dma);
831 if (tmp & BUSY_EVEN) {
832 printk(KERN_ERR "dt3155: BUSY_EVEN not cleared\n");
833 return -EIO;
834 }
835 return 0;
836 }
837
838 static struct video_device dt3155_vdev = {
839 .name = DT3155_NAME,
840 .fops = &dt3155_fops,
841 .ioctl_ops = &dt3155_ioctl_ops,
842 .minor = -1,
843 .release = video_device_release,
844 .tvnorms = DT3155_CURRENT_NORM,
845 .current_norm = DT3155_CURRENT_NORM,
846 };
847
848 /* same as in drivers/base/dma-coherent.c */
849 struct dma_coherent_mem {
850 void *virt_base;
851 dma_addr_t device_base;
852 int size;
853 int flags;
854 unsigned long *bitmap;
855 };
856
857 static int __devinit
858 dt3155_alloc_coherent(struct device *dev, size_t size, int flags)
859 {
860 struct dma_coherent_mem *mem;
861 dma_addr_t dev_base;
862 int pages = size >> PAGE_SHIFT;
863 int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
864
865 if ((flags & DMA_MEMORY_MAP) == 0)
866 goto out;
867 if (!size)
868 goto out;
869 if (dev->dma_mem)
870 goto out;
871
872 mem = kzalloc(sizeof(*mem), GFP_KERNEL);
873 if (!mem)
874 goto out;
875 mem->virt_base = dma_alloc_coherent(dev, size, &dev_base,
876 DT3155_COH_FLAGS);
877 if (!mem->virt_base)
878 goto err_alloc_coherent;
879 mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
880 if (!mem->bitmap)
881 goto err_bitmap;
882
883 /* coherent_dma_mask is already set to 32 bits */
884 mem->device_base = dev_base;
885 mem->size = pages;
886 mem->flags = flags;
887 dev->dma_mem = mem;
888 return DMA_MEMORY_MAP;
889
890 err_bitmap:
891 dma_free_coherent(dev, size, mem->virt_base, dev_base);
892 err_alloc_coherent:
893 kfree(mem);
894 out:
895 return 0;
896 }
897
898 static void __devexit
899 dt3155_free_coherent(struct device *dev)
900 {
901 struct dma_coherent_mem *mem = dev->dma_mem;
902
903 if (!mem)
904 return;
905 dev->dma_mem = NULL;
906 dma_free_coherent(dev, mem->size << PAGE_SHIFT,
907 mem->virt_base, mem->device_base);
908 kfree(mem->bitmap);
909 kfree(mem);
910 }
911
912 static int __devinit
913 dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id)
914 {
915 int err;
916 struct dt3155_priv *pd;
917
918 printk(KERN_INFO "dt3155: probe()\n");
919 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
920 if (err) {
921 printk(KERN_ERR "dt3155: cannot set dma_mask\n");
922 return -ENODEV;
923 }
924 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
925 if (err) {
926 printk(KERN_ERR "dt3155: cannot set dma_coherent_mask\n");
927 return -ENODEV;
928 }
929 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
930 if (!pd) {
931 printk(KERN_ERR "dt3155: cannot allocate dt3155_priv\n");
932 return -ENOMEM;
933 }
934 pd->vdev = video_device_alloc();
935 if (!pd->vdev) {
936 printk(KERN_ERR "dt3155: cannot allocate vdev structure\n");
937 goto err_video_device_alloc;
938 }
939 *pd->vdev = dt3155_vdev;
940 pci_set_drvdata(pdev, pd); /* for use in dt3155_remove() */
941 video_set_drvdata(pd->vdev, pd); /* for use in video_fops */
942 pd->users = 0;
943 pd->pdev = pdev;
944 INIT_LIST_HEAD(&pd->dmaq);
945 mutex_init(&pd->mux);
946 pd->vdev->lock = &pd->mux; /* for locking v4l2_file_operations */
947 spin_lock_init(&pd->lock);
948 pd->csr2 = csr2_init;
949 pd->config = config_init;
950 err = pci_enable_device(pdev);
951 if (err) {
952 printk(KERN_ERR "dt3155: pci_dev not enabled\n");
953 goto err_enable_dev;
954 }
955 err = pci_request_region(pdev, 0, pci_name(pdev));
956 if (err)
957 goto err_req_region;
958 pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0));
959 if (!pd->regs) {
960 err = -ENOMEM;
961 printk(KERN_ERR "dt3155: pci_iomap failed\n");
962 goto err_pci_iomap;
963 }
964 err = dt3155_init_board(pdev);
965 if (err) {
966 printk(KERN_ERR "dt3155: dt3155_init_board failed\n");
967 goto err_init_board;
968 }
969 err = video_register_device(pd->vdev, VFL_TYPE_GRABBER, -1);
970 if (err) {
971 printk(KERN_ERR "dt3155: Cannot register video device\n");
972 goto err_init_board;
973 }
974 err = dt3155_alloc_coherent(&pdev->dev, DT3155_CHUNK_SIZE,
975 DMA_MEMORY_MAP);
976 if (err)
977 printk(KERN_INFO "dt3155: preallocated 8 buffers\n");
978 printk(KERN_INFO "dt3155: /dev/video%i is ready\n", pd->vdev->minor);
979 return 0; /* success */
980
981 err_init_board:
982 pci_iounmap(pdev, pd->regs);
983 err_pci_iomap:
984 pci_release_region(pdev, 0);
985 err_req_region:
986 pci_disable_device(pdev);
987 err_enable_dev:
988 video_device_release(pd->vdev);
989 err_video_device_alloc:
990 kfree(pd);
991 return err;
992 }
993
994 static void __devexit
995 dt3155_remove(struct pci_dev *pdev)
996 {
997 struct dt3155_priv *pd = pci_get_drvdata(pdev);
998
999 printk(KERN_INFO "dt3155: remove()\n");
1000 dt3155_free_coherent(&pdev->dev);
1001 video_unregister_device(pd->vdev);
1002 pci_iounmap(pdev, pd->regs);
1003 pci_release_region(pdev, 0);
1004 pci_disable_device(pdev);
1005 /*
1006 * video_device_release() is invoked automatically
1007 * see: struct video_device dt3155_vdev
1008 */
1009 kfree(pd);
1010 }
1011
1012 static DEFINE_PCI_DEVICE_TABLE(pci_ids) = {
1013 { PCI_DEVICE(DT3155_VENDOR_ID, DT3155_DEVICE_ID) },
1014 { 0, /* zero marks the end */ },
1015 };
1016 MODULE_DEVICE_TABLE(pci, pci_ids);
1017
1018 static struct pci_driver pci_driver = {
1019 .name = DT3155_NAME,
1020 .id_table = pci_ids,
1021 .probe = dt3155_probe,
1022 .remove = __devexit_p(dt3155_remove),
1023 };
1024
1025 static int __init
1026 dt3155_init_module(void)
1027 {
1028 int err;
1029
1030 printk(KERN_INFO "dt3155: ==================\n");
1031 printk(KERN_INFO "dt3155: init()\n");
1032 err = pci_register_driver(&pci_driver);
1033 if (err) {
1034 printk(KERN_ERR "dt3155: cannot register pci_driver\n");
1035 return err;
1036 }
1037 return 0; /* succes */
1038 }
1039
1040 static void __exit
1041 dt3155_exit_module(void)
1042 {
1043 pci_unregister_driver(&pci_driver);
1044 printk(KERN_INFO "dt3155: exit()\n");
1045 printk(KERN_INFO "dt3155: ==================\n");
1046 }
1047
1048 module_init(dt3155_init_module);
1049 module_exit(dt3155_exit_module);
1050
1051 MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber");
1052 MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>");
1053 MODULE_VERSION(DT3155_VERSION);
1054 MODULE_LICENSE("GPL");
linux-next