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sched: task_tick_rt: Remove the obsolete ->signal != NULL check
[linux-2.6/next.git] / drivers / spi / spi_mpc8xxx.c
blobffa111a7e9d443f23cda4287eeeb17d53d323a46
1 /*
2 * MPC8xxx SPI controller driver.
3 *
4 * Maintainer: Kumar Gala
5 *
6 * Copyright (C) 2006 Polycom, Inc.
7 *
8 * CPM SPI and QE buffer descriptors mode support:
9 * Copyright (c) 2009 MontaVista Software, Inc.
10 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/bug.h>
22 #include <linux/errno.h>
23 #include <linux/err.h>
24 #include <linux/io.h>
25 #include <linux/completion.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28 #include <linux/irq.h>
29 #include <linux/device.h>
30 #include <linux/spi/spi.h>
31 #include <linux/spi/spi_bitbang.h>
32 #include <linux/platform_device.h>
33 #include <linux/fsl_devices.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/mm.h>
36 #include <linux/mutex.h>
37 #include <linux/of.h>
38 #include <linux/of_platform.h>
39 #include <linux/gpio.h>
40 #include <linux/of_gpio.h>
41 #include <linux/of_spi.h>
42 #include <linux/slab.h>
43
44 #include <sysdev/fsl_soc.h>
45 #include <asm/cpm.h>
46 #include <asm/qe.h>
47 #include <asm/irq.h>
48
49 /* CPM1 and CPM2 are mutually exclusive. */
50 #ifdef CONFIG_CPM1
51 #include <asm/cpm1.h>
52 #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_CH_SPI, 0)
53 #else
54 #include <asm/cpm2.h>
55 #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, 0, 0)
56 #endif
57
58 /* SPI Controller registers */
59 struct mpc8xxx_spi_reg {
60 u8 res1[0x20];
61 __be32 mode;
62 __be32 event;
63 __be32 mask;
64 __be32 command;
65 __be32 transmit;
66 __be32 receive;
67 };
68
69 /* SPI Parameter RAM */
70 struct spi_pram {
71 __be16 rbase; /* Rx Buffer descriptor base address */
72 __be16 tbase; /* Tx Buffer descriptor base address */
73 u8 rfcr; /* Rx function code */
74 u8 tfcr; /* Tx function code */
75 __be16 mrblr; /* Max receive buffer length */
76 __be32 rstate; /* Internal */
77 __be32 rdp; /* Internal */
78 __be16 rbptr; /* Internal */
79 __be16 rbc; /* Internal */
80 __be32 rxtmp; /* Internal */
81 __be32 tstate; /* Internal */
82 __be32 tdp; /* Internal */
83 __be16 tbptr; /* Internal */
84 __be16 tbc; /* Internal */
85 __be32 txtmp; /* Internal */
86 __be32 res; /* Tx temp. */
87 __be16 rpbase; /* Relocation pointer (CPM1 only) */
88 __be16 res1; /* Reserved */
89 };
90
91 /* SPI Controller mode register definitions */
92 #define SPMODE_LOOP (1 << 30)
93 #define SPMODE_CI_INACTIVEHIGH (1 << 29)
94 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
95 #define SPMODE_DIV16 (1 << 27)
96 #define SPMODE_REV (1 << 26)
97 #define SPMODE_MS (1 << 25)
98 #define SPMODE_ENABLE (1 << 24)
99 #define SPMODE_LEN(x) ((x) << 20)
100 #define SPMODE_PM(x) ((x) << 16)
101 #define SPMODE_OP (1 << 14)
102 #define SPMODE_CG(x) ((x) << 7)
103
104 /*
105 * Default for SPI Mode:
106 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
107 */
108 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
109 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
110
111 /* SPIE register values */
112 #define SPIE_NE 0x00000200 /* Not empty */
113 #define SPIE_NF 0x00000100 /* Not full */
114
115 /* SPIM register values */
116 #define SPIM_NE 0x00000200 /* Not empty */
117 #define SPIM_NF 0x00000100 /* Not full */
118
119 #define SPIE_TXB 0x00000200 /* Last char is written to tx fifo */
120 #define SPIE_RXB 0x00000100 /* Last char is written to rx buf */
121
122 /* SPCOM register values */
123 #define SPCOM_STR (1 << 23) /* Start transmit */
124
125 #define SPI_PRAM_SIZE 0x100
126 #define SPI_MRBLR ((unsigned int)PAGE_SIZE)
127
128 /* SPI Controller driver's private data. */
129 struct mpc8xxx_spi {
130 struct device *dev;
131 struct mpc8xxx_spi_reg __iomem *base;
132
133 /* rx & tx bufs from the spi_transfer */
134 const void *tx;
135 void *rx;
136
137 int subblock;
138 struct spi_pram __iomem *pram;
139 struct cpm_buf_desc __iomem *tx_bd;
140 struct cpm_buf_desc __iomem *rx_bd;
141
142 struct spi_transfer *xfer_in_progress;
143
144 /* dma addresses for CPM transfers */
145 dma_addr_t tx_dma;
146 dma_addr_t rx_dma;
147 bool map_tx_dma;
148 bool map_rx_dma;
149
150 dma_addr_t dma_dummy_tx;
151 dma_addr_t dma_dummy_rx;
152
153 /* functions to deal with different sized buffers */
154 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
155 u32(*get_tx) (struct mpc8xxx_spi *);
156
157 unsigned int count;
158 unsigned int irq;
159
160 unsigned nsecs; /* (clock cycle time)/2 */
161
162 u32 spibrg; /* SPIBRG input clock */
163 u32 rx_shift; /* RX data reg shift when in qe mode */
164 u32 tx_shift; /* TX data reg shift when in qe mode */
165
166 unsigned int flags;
167
168 struct workqueue_struct *workqueue;
169 struct work_struct work;
170
171 struct list_head queue;
172 spinlock_t lock;
173
174 struct completion done;
175 };
176
177 static void *mpc8xxx_dummy_rx;
178 static DEFINE_MUTEX(mpc8xxx_dummy_rx_lock);
179 static int mpc8xxx_dummy_rx_refcnt;
180
181 struct spi_mpc8xxx_cs {
182 /* functions to deal with different sized buffers */
183 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
184 u32 (*get_tx) (struct mpc8xxx_spi *);
185 u32 rx_shift; /* RX data reg shift when in qe mode */
186 u32 tx_shift; /* TX data reg shift when in qe mode */
187 u32 hw_mode; /* Holds HW mode register settings */
188 };
189
190 static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
191 {
192 out_be32(reg, val);
193 }
194
195 static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
196 {
197 return in_be32(reg);
198 }
199
200 #define MPC83XX_SPI_RX_BUF(type) \
201 static \
202 void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
203 { \
204 type *rx = mpc8xxx_spi->rx; \
205 *rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \
206 mpc8xxx_spi->rx = rx; \
207 }
208
209 #define MPC83XX_SPI_TX_BUF(type) \
210 static \
211 u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
212 { \
213 u32 data; \
214 const type *tx = mpc8xxx_spi->tx; \
215 if (!tx) \
216 return 0; \
217 data = *tx++ << mpc8xxx_spi->tx_shift; \
218 mpc8xxx_spi->tx = tx; \
219 return data; \
220 }
221
222 MPC83XX_SPI_RX_BUF(u8)
223 MPC83XX_SPI_RX_BUF(u16)
224 MPC83XX_SPI_RX_BUF(u32)
225 MPC83XX_SPI_TX_BUF(u8)
226 MPC83XX_SPI_TX_BUF(u16)
227 MPC83XX_SPI_TX_BUF(u32)
228
229 static void mpc8xxx_spi_change_mode(struct spi_device *spi)
230 {
231 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
232 struct spi_mpc8xxx_cs *cs = spi->controller_state;
233 __be32 __iomem *mode = &mspi->base->mode;
234 unsigned long flags;
235
236 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
237 return;
238
239 /* Turn off IRQs locally to minimize time that SPI is disabled. */
240 local_irq_save(flags);
241
242 /* Turn off SPI unit prior changing mode */
243 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
244
245 /* When in CPM mode, we need to reinit tx and rx. */
246 if (mspi->flags & SPI_CPM_MODE) {
247 if (mspi->flags & SPI_QE) {
248 qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock,
249 QE_CR_PROTOCOL_UNSPECIFIED, 0);
250 } else {
251 cpm_command(CPM_SPI_CMD, CPM_CR_INIT_TRX);
252 if (mspi->flags & SPI_CPM1) {
253 out_be16(&mspi->pram->rbptr,
254 in_be16(&mspi->pram->rbase));
255 out_be16(&mspi->pram->tbptr,
256 in_be16(&mspi->pram->tbase));
257 }
258 }
259 }
260 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
261 local_irq_restore(flags);
262 }
263
264 static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value)
265 {
266 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
267 struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data;
268 bool pol = spi->mode & SPI_CS_HIGH;
269 struct spi_mpc8xxx_cs *cs = spi->controller_state;
270
271 if (value == BITBANG_CS_INACTIVE) {
272 if (pdata->cs_control)
273 pdata->cs_control(spi, !pol);
274 }
275
276 if (value == BITBANG_CS_ACTIVE) {
277 mpc8xxx_spi->rx_shift = cs->rx_shift;
278 mpc8xxx_spi->tx_shift = cs->tx_shift;
279 mpc8xxx_spi->get_rx = cs->get_rx;
280 mpc8xxx_spi->get_tx = cs->get_tx;
281
282 mpc8xxx_spi_change_mode(spi);
283
284 if (pdata->cs_control)
285 pdata->cs_control(spi, pol);
286 }
287 }
288
289 static int
290 mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
291 struct spi_device *spi,
292 struct mpc8xxx_spi *mpc8xxx_spi,
293 int bits_per_word)
294 {
295 cs->rx_shift = 0;
296 cs->tx_shift = 0;
297 if (bits_per_word <= 8) {
298 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
299 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
300 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
301 cs->rx_shift = 16;
302 cs->tx_shift = 24;
303 }
304 } else if (bits_per_word <= 16) {
305 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
306 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
307 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
308 cs->rx_shift = 16;
309 cs->tx_shift = 16;
310 }
311 } else if (bits_per_word <= 32) {
312 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
313 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
314 } else
315 return -EINVAL;
316
317 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE &&
318 spi->mode & SPI_LSB_FIRST) {
319 cs->tx_shift = 0;
320 if (bits_per_word <= 8)
321 cs->rx_shift = 8;
322 else
323 cs->rx_shift = 0;
324 }
325 mpc8xxx_spi->rx_shift = cs->rx_shift;
326 mpc8xxx_spi->tx_shift = cs->tx_shift;
327 mpc8xxx_spi->get_rx = cs->get_rx;
328 mpc8xxx_spi->get_tx = cs->get_tx;
329
330 return bits_per_word;
331 }
332
333 static int
334 mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
335 struct spi_device *spi,
336 int bits_per_word)
337 {
338 /* QE uses Little Endian for words > 8
339 * so transform all words > 8 into 8 bits
340 * Unfortnatly that doesn't work for LSB so
341 * reject these for now */
342 /* Note: 32 bits word, LSB works iff
343 * tfcr/rfcr is set to CPMFCR_GBL */
344 if (spi->mode & SPI_LSB_FIRST &&
345 bits_per_word > 8)
346 return -EINVAL;
347 if (bits_per_word > 8)
348 return 8; /* pretend its 8 bits */
349 return bits_per_word;
350 }
351
352 static
353 int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
354 {
355 struct mpc8xxx_spi *mpc8xxx_spi;
356 int bits_per_word;
357 u8 pm;
358 u32 hz;
359 struct spi_mpc8xxx_cs *cs = spi->controller_state;
360
361 mpc8xxx_spi = spi_master_get_devdata(spi->master);
362
363 if (t) {
364 bits_per_word = t->bits_per_word;
365 hz = t->speed_hz;
366 } else {
367 bits_per_word = 0;
368 hz = 0;
369 }
370
371 /* spi_transfer level calls that work per-word */
372 if (!bits_per_word)
373 bits_per_word = spi->bits_per_word;
374
375 /* Make sure its a bit width we support [4..16, 32] */
376 if ((bits_per_word < 4)
377 || ((bits_per_word > 16) && (bits_per_word != 32)))
378 return -EINVAL;
379
380 if (!hz)
381 hz = spi->max_speed_hz;
382
383 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
384 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
385 mpc8xxx_spi,
386 bits_per_word);
387 else if (mpc8xxx_spi->flags & SPI_QE)
388 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
389 bits_per_word);
390
391 if (bits_per_word < 0)
392 return bits_per_word;
393
394 if (bits_per_word == 32)
395 bits_per_word = 0;
396 else
397 bits_per_word = bits_per_word - 1;
398
399 /* mask out bits we are going to set */
400 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
401 | SPMODE_PM(0xF));
402
403 cs->hw_mode |= SPMODE_LEN(bits_per_word);
404
405 if ((mpc8xxx_spi->spibrg / hz) > 64) {
406 cs->hw_mode |= SPMODE_DIV16;
407 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
408
409 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
410 "Will use %d Hz instead.\n", dev_name(&spi->dev),
411 hz, mpc8xxx_spi->spibrg / 1024);
412 if (pm > 16)
413 pm = 16;
414 } else
415 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
416 if (pm)
417 pm--;
418
419 cs->hw_mode |= SPMODE_PM(pm);
420
421 mpc8xxx_spi_change_mode(spi);
422 return 0;
423 }
424
425 static void mpc8xxx_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi)
426 {
427 struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd;
428 struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd;
429 unsigned int xfer_len = min(mspi->count, SPI_MRBLR);
430 unsigned int xfer_ofs;
431
432 xfer_ofs = mspi->xfer_in_progress->len - mspi->count;
433
434 out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma + xfer_ofs);
435 out_be16(&rx_bd->cbd_datlen, 0);
436 out_be16(&rx_bd->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT | BD_SC_WRAP);
437
438 out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma + xfer_ofs);
439 out_be16(&tx_bd->cbd_datlen, xfer_len);
440 out_be16(&tx_bd->cbd_sc, BD_SC_READY | BD_SC_INTRPT | BD_SC_WRAP |
441 BD_SC_LAST);
442
443 /* start transfer */
444 mpc8xxx_spi_write_reg(&mspi->base->command, SPCOM_STR);
445 }
446
447 static int mpc8xxx_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
448 struct spi_transfer *t, bool is_dma_mapped)
449 {
450 struct device *dev = mspi->dev;
451
452 if (is_dma_mapped) {
453 mspi->map_tx_dma = 0;
454 mspi->map_rx_dma = 0;
455 } else {
456 mspi->map_tx_dma = 1;
457 mspi->map_rx_dma = 1;
458 }
459
460 if (!t->tx_buf) {
461 mspi->tx_dma = mspi->dma_dummy_tx;
462 mspi->map_tx_dma = 0;
463 }
464
465 if (!t->rx_buf) {
466 mspi->rx_dma = mspi->dma_dummy_rx;
467 mspi->map_rx_dma = 0;
468 }
469
470 if (mspi->map_tx_dma) {
471 void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */
472
473 mspi->tx_dma = dma_map_single(dev, nonconst_tx, t->len,
474 DMA_TO_DEVICE);
475 if (dma_mapping_error(dev, mspi->tx_dma)) {
476 dev_err(dev, "unable to map tx dma\n");
477 return -ENOMEM;
478 }
479 } else if (t->tx_buf) {
480 mspi->tx_dma = t->tx_dma;
481 }
482
483 if (mspi->map_rx_dma) {
484 mspi->rx_dma = dma_map_single(dev, mspi->rx, t->len,
485 DMA_FROM_DEVICE);
486 if (dma_mapping_error(dev, mspi->rx_dma)) {
487 dev_err(dev, "unable to map rx dma\n");
488 goto err_rx_dma;
489 }
490 } else if (t->rx_buf) {
491 mspi->rx_dma = t->rx_dma;
492 }
493
494 /* enable rx ints */
495 mpc8xxx_spi_write_reg(&mspi->base->mask, SPIE_RXB);
496
497 mspi->xfer_in_progress = t;
498 mspi->count = t->len;
499
500 /* start CPM transfers */
501 mpc8xxx_spi_cpm_bufs_start(mspi);
502
503 return 0;
504
505 err_rx_dma:
506 if (mspi->map_tx_dma)
507 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
508 return -ENOMEM;
509 }
510
511 static void mpc8xxx_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
512 {
513 struct device *dev = mspi->dev;
514 struct spi_transfer *t = mspi->xfer_in_progress;
515
516 if (mspi->map_tx_dma)
517 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
518 if (mspi->map_rx_dma)
519 dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE);
520 mspi->xfer_in_progress = NULL;
521 }
522
523 static int mpc8xxx_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
524 struct spi_transfer *t, unsigned int len)
525 {
526 u32 word;
527
528 mspi->count = len;
529
530 /* enable rx ints */
531 mpc8xxx_spi_write_reg(&mspi->base->mask, SPIM_NE);
532
533 /* transmit word */
534 word = mspi->get_tx(mspi);
535 mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
536
537 return 0;
538 }
539
540 static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
541 bool is_dma_mapped)
542 {
543 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
544 unsigned int len = t->len;
545 u8 bits_per_word;
546 int ret;
547
548 bits_per_word = spi->bits_per_word;
549 if (t->bits_per_word)
550 bits_per_word = t->bits_per_word;
551
552 if (bits_per_word > 8) {
553 /* invalid length? */
554 if (len & 1)
555 return -EINVAL;
556 len /= 2;
557 }
558 if (bits_per_word > 16) {
559 /* invalid length? */
560 if (len & 1)
561 return -EINVAL;
562 len /= 2;
563 }
564
565 mpc8xxx_spi->tx = t->tx_buf;
566 mpc8xxx_spi->rx = t->rx_buf;
567
568 INIT_COMPLETION(mpc8xxx_spi->done);
569
570 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
571 ret = mpc8xxx_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
572 else
573 ret = mpc8xxx_spi_cpu_bufs(mpc8xxx_spi, t, len);
574 if (ret)
575 return ret;
576
577 wait_for_completion(&mpc8xxx_spi->done);
578
579 /* disable rx ints */
580 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
581
582 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
583 mpc8xxx_spi_cpm_bufs_complete(mpc8xxx_spi);
584
585 return mpc8xxx_spi->count;
586 }
587
588 static void mpc8xxx_spi_do_one_msg(struct spi_message *m)
589 {
590 struct spi_device *spi = m->spi;
591 struct spi_transfer *t;
592 unsigned int cs_change;
593 const int nsecs = 50;
594 int status;
595
596 cs_change = 1;
597 status = 0;
598 list_for_each_entry(t, &m->transfers, transfer_list) {
599 if (t->bits_per_word || t->speed_hz) {
600 /* Don't allow changes if CS is active */
601 status = -EINVAL;
602
603 if (cs_change)
604 status = mpc8xxx_spi_setup_transfer(spi, t);
605 if (status < 0)
606 break;
607 }
608
609 if (cs_change) {
610 mpc8xxx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
611 ndelay(nsecs);
612 }
613 cs_change = t->cs_change;
614 if (t->len)
615 status = mpc8xxx_spi_bufs(spi, t, m->is_dma_mapped);
616 if (status) {
617 status = -EMSGSIZE;
618 break;
619 }
620 m->actual_length += t->len;
621
622 if (t->delay_usecs)
623 udelay(t->delay_usecs);
624
625 if (cs_change) {
626 ndelay(nsecs);
627 mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
628 ndelay(nsecs);
629 }
630 }
631
632 m->status = status;
633 m->complete(m->context);
634
635 if (status || !cs_change) {
636 ndelay(nsecs);
637 mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
638 }
639
640 mpc8xxx_spi_setup_transfer(spi, NULL);
641 }
642
643 static void mpc8xxx_spi_work(struct work_struct *work)
644 {
645 struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
646 work);
647
648 spin_lock_irq(&mpc8xxx_spi->lock);
649 while (!list_empty(&mpc8xxx_spi->queue)) {
650 struct spi_message *m = container_of(mpc8xxx_spi->queue.next,
651 struct spi_message, queue);
652
653 list_del_init(&m->queue);
654 spin_unlock_irq(&mpc8xxx_spi->lock);
655
656 mpc8xxx_spi_do_one_msg(m);
657
658 spin_lock_irq(&mpc8xxx_spi->lock);
659 }
660 spin_unlock_irq(&mpc8xxx_spi->lock);
661 }
662
663 static int mpc8xxx_spi_setup(struct spi_device *spi)
664 {
665 struct mpc8xxx_spi *mpc8xxx_spi;
666 int retval;
667 u32 hw_mode;
668 struct spi_mpc8xxx_cs *cs = spi->controller_state;
669
670 if (!spi->max_speed_hz)
671 return -EINVAL;
672
673 if (!cs) {
674 cs = kzalloc(sizeof *cs, GFP_KERNEL);
675 if (!cs)
676 return -ENOMEM;
677 spi->controller_state = cs;
678 }
679 mpc8xxx_spi = spi_master_get_devdata(spi->master);
680
681 hw_mode = cs->hw_mode; /* Save original settings */
682 cs->hw_mode = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode);
683 /* mask out bits we are going to set */
684 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
685 | SPMODE_REV | SPMODE_LOOP);
686
687 if (spi->mode & SPI_CPHA)
688 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
689 if (spi->mode & SPI_CPOL)
690 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
691 if (!(spi->mode & SPI_LSB_FIRST))
692 cs->hw_mode |= SPMODE_REV;
693 if (spi->mode & SPI_LOOP)
694 cs->hw_mode |= SPMODE_LOOP;
695
696 retval = mpc8xxx_spi_setup_transfer(spi, NULL);
697 if (retval < 0) {
698 cs->hw_mode = hw_mode; /* Restore settings */
699 return retval;
700 }
701 return 0;
702 }
703
704 static void mpc8xxx_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
705 {
706 u16 len;
707
708 dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__,
709 in_be16(&mspi->rx_bd->cbd_datlen), mspi->count);
710
711 len = in_be16(&mspi->rx_bd->cbd_datlen);
712 if (len > mspi->count) {
713 WARN_ON(1);
714 len = mspi->count;
715 }
716
717 /* Clear the events */
718 mpc8xxx_spi_write_reg(&mspi->base->event, events);
719
720 mspi->count -= len;
721 if (mspi->count)
722 mpc8xxx_spi_cpm_bufs_start(mspi);
723 else
724 complete(&mspi->done);
725 }
726
727 static void mpc8xxx_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
728 {
729 /* We need handle RX first */
730 if (events & SPIE_NE) {
731 u32 rx_data = mpc8xxx_spi_read_reg(&mspi->base->receive);
732
733 if (mspi->rx)
734 mspi->get_rx(rx_data, mspi);
735 }
736
737 if ((events & SPIE_NF) == 0)
738 /* spin until TX is done */
739 while (((events =
740 mpc8xxx_spi_read_reg(&mspi->base->event)) &
741 SPIE_NF) == 0)
742 cpu_relax();
743
744 /* Clear the events */
745 mpc8xxx_spi_write_reg(&mspi->base->event, events);
746
747 mspi->count -= 1;
748 if (mspi->count) {
749 u32 word = mspi->get_tx(mspi);
750
751 mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
752 } else {
753 complete(&mspi->done);
754 }
755 }
756
757 static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data)
758 {
759 struct mpc8xxx_spi *mspi = context_data;
760 irqreturn_t ret = IRQ_NONE;
761 u32 events;
762
763 /* Get interrupt events(tx/rx) */
764 events = mpc8xxx_spi_read_reg(&mspi->base->event);
765 if (events)
766 ret = IRQ_HANDLED;
767
768 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
769
770 if (mspi->flags & SPI_CPM_MODE)
771 mpc8xxx_spi_cpm_irq(mspi, events);
772 else
773 mpc8xxx_spi_cpu_irq(mspi, events);
774
775 return ret;
776 }
777
778 static int mpc8xxx_spi_transfer(struct spi_device *spi,
779 struct spi_message *m)
780 {
781 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
782 unsigned long flags;
783
784 m->actual_length = 0;
785 m->status = -EINPROGRESS;
786
787 spin_lock_irqsave(&mpc8xxx_spi->lock, flags);
788 list_add_tail(&m->queue, &mpc8xxx_spi->queue);
789 queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work);
790 spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags);
791
792 return 0;
793 }
794
795
796 static void mpc8xxx_spi_cleanup(struct spi_device *spi)
797 {
798 kfree(spi->controller_state);
799 }
800
801 static void *mpc8xxx_spi_alloc_dummy_rx(void)
802 {
803 mutex_lock(&mpc8xxx_dummy_rx_lock);
804
805 if (!mpc8xxx_dummy_rx)
806 mpc8xxx_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL);
807 if (mpc8xxx_dummy_rx)
808 mpc8xxx_dummy_rx_refcnt++;
809
810 mutex_unlock(&mpc8xxx_dummy_rx_lock);
811
812 return mpc8xxx_dummy_rx;
813 }
814
815 static void mpc8xxx_spi_free_dummy_rx(void)
816 {
817 mutex_lock(&mpc8xxx_dummy_rx_lock);
818
819 switch (mpc8xxx_dummy_rx_refcnt) {
820 case 0:
821 WARN_ON(1);
822 break;
823 case 1:
824 kfree(mpc8xxx_dummy_rx);
825 mpc8xxx_dummy_rx = NULL;
826 /* fall through */
827 default:
828 mpc8xxx_dummy_rx_refcnt--;
829 break;
830 }
831
832 mutex_unlock(&mpc8xxx_dummy_rx_lock);
833 }
834
835 static unsigned long mpc8xxx_spi_cpm_get_pram(struct mpc8xxx_spi *mspi)
836 {
837 struct device *dev = mspi->dev;
838 struct device_node *np = dev->of_node;
839 const u32 *iprop;
840 int size;
841 unsigned long spi_base_ofs;
842 unsigned long pram_ofs = -ENOMEM;
843
844 /* Can't use of_address_to_resource(), QE muram isn't at 0. */
845 iprop = of_get_property(np, "reg", &size);
846
847 /* QE with a fixed pram location? */
848 if (mspi->flags & SPI_QE && iprop && size == sizeof(*iprop) * 4)
849 return cpm_muram_alloc_fixed(iprop[2], SPI_PRAM_SIZE);
850
851 /* QE but with a dynamic pram location? */
852 if (mspi->flags & SPI_QE) {
853 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
854 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, mspi->subblock,
855 QE_CR_PROTOCOL_UNSPECIFIED, pram_ofs);
856 return pram_ofs;
857 }
858
859 /* CPM1 and CPM2 pram must be at a fixed addr. */
860 if (!iprop || size != sizeof(*iprop) * 4)
861 return -ENOMEM;
862
863 spi_base_ofs = cpm_muram_alloc_fixed(iprop[2], 2);
864 if (IS_ERR_VALUE(spi_base_ofs))
865 return -ENOMEM;
866
867 if (mspi->flags & SPI_CPM2) {
868 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
869 if (!IS_ERR_VALUE(pram_ofs)) {
870 u16 __iomem *spi_base = cpm_muram_addr(spi_base_ofs);
871
872 out_be16(spi_base, pram_ofs);
873 }
874 } else {
875 struct spi_pram __iomem *pram = cpm_muram_addr(spi_base_ofs);
876 u16 rpbase = in_be16(&pram->rpbase);
877
878 /* Microcode relocation patch applied? */
879 if (rpbase)
880 pram_ofs = rpbase;
881 else
882 return spi_base_ofs;
883 }
884
885 cpm_muram_free(spi_base_ofs);
886 return pram_ofs;
887 }
888
889 static int mpc8xxx_spi_cpm_init(struct mpc8xxx_spi *mspi)
890 {
891 struct device *dev = mspi->dev;
892 struct device_node *np = dev->of_node;
893 const u32 *iprop;
894 int size;
895 unsigned long pram_ofs;
896 unsigned long bds_ofs;
897
898 if (!(mspi->flags & SPI_CPM_MODE))
899 return 0;
900
901 if (!mpc8xxx_spi_alloc_dummy_rx())
902 return -ENOMEM;
903
904 if (mspi->flags & SPI_QE) {
905 iprop = of_get_property(np, "cell-index", &size);
906 if (iprop && size == sizeof(*iprop))
907 mspi->subblock = *iprop;
908
909 switch (mspi->subblock) {
910 default:
911 dev_warn(dev, "cell-index unspecified, assuming SPI1");
912 /* fall through */
913 case 0:
914 mspi->subblock = QE_CR_SUBBLOCK_SPI1;
915 break;
916 case 1:
917 mspi->subblock = QE_CR_SUBBLOCK_SPI2;
918 break;
919 }
920 }
921
922 pram_ofs = mpc8xxx_spi_cpm_get_pram(mspi);
923 if (IS_ERR_VALUE(pram_ofs)) {
924 dev_err(dev, "can't allocate spi parameter ram\n");
925 goto err_pram;
926 }
927
928 bds_ofs = cpm_muram_alloc(sizeof(*mspi->tx_bd) +
929 sizeof(*mspi->rx_bd), 8);
930 if (IS_ERR_VALUE(bds_ofs)) {
931 dev_err(dev, "can't allocate bds\n");
932 goto err_bds;
933 }
934
935 mspi->dma_dummy_tx = dma_map_single(dev, empty_zero_page, PAGE_SIZE,
936 DMA_TO_DEVICE);
937 if (dma_mapping_error(dev, mspi->dma_dummy_tx)) {
938 dev_err(dev, "unable to map dummy tx buffer\n");
939 goto err_dummy_tx;
940 }
941
942 mspi->dma_dummy_rx = dma_map_single(dev, mpc8xxx_dummy_rx, SPI_MRBLR,
943 DMA_FROM_DEVICE);
944 if (dma_mapping_error(dev, mspi->dma_dummy_rx)) {
945 dev_err(dev, "unable to map dummy rx buffer\n");
946 goto err_dummy_rx;
947 }
948
949 mspi->pram = cpm_muram_addr(pram_ofs);
950
951 mspi->tx_bd = cpm_muram_addr(bds_ofs);
952 mspi->rx_bd = cpm_muram_addr(bds_ofs + sizeof(*mspi->tx_bd));
953
954 /* Initialize parameter ram. */
955 out_be16(&mspi->pram->tbase, cpm_muram_offset(mspi->tx_bd));
956 out_be16(&mspi->pram->rbase, cpm_muram_offset(mspi->rx_bd));
957 out_8(&mspi->pram->tfcr, CPMFCR_EB | CPMFCR_GBL);
958 out_8(&mspi->pram->rfcr, CPMFCR_EB | CPMFCR_GBL);
959 out_be16(&mspi->pram->mrblr, SPI_MRBLR);
960 out_be32(&mspi->pram->rstate, 0);
961 out_be32(&mspi->pram->rdp, 0);
962 out_be16(&mspi->pram->rbptr, 0);
963 out_be16(&mspi->pram->rbc, 0);
964 out_be32(&mspi->pram->rxtmp, 0);
965 out_be32(&mspi->pram->tstate, 0);
966 out_be32(&mspi->pram->tdp, 0);
967 out_be16(&mspi->pram->tbptr, 0);
968 out_be16(&mspi->pram->tbc, 0);
969 out_be32(&mspi->pram->txtmp, 0);
970
971 return 0;
972
973 err_dummy_rx:
974 dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
975 err_dummy_tx:
976 cpm_muram_free(bds_ofs);
977 err_bds:
978 cpm_muram_free(pram_ofs);
979 err_pram:
980 mpc8xxx_spi_free_dummy_rx();
981 return -ENOMEM;
982 }
983
984 static void mpc8xxx_spi_cpm_free(struct mpc8xxx_spi *mspi)
985 {
986 struct device *dev = mspi->dev;
987
988 dma_unmap_single(dev, mspi->dma_dummy_rx, SPI_MRBLR, DMA_FROM_DEVICE);
989 dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
990 cpm_muram_free(cpm_muram_offset(mspi->tx_bd));
991 cpm_muram_free(cpm_muram_offset(mspi->pram));
992 mpc8xxx_spi_free_dummy_rx();
993 }
994
995 static const char *mpc8xxx_spi_strmode(unsigned int flags)
996 {
997 if (flags & SPI_QE_CPU_MODE) {
998 return "QE CPU";
999 } else if (flags & SPI_CPM_MODE) {
1000 if (flags & SPI_QE)
1001 return "QE";
1002 else if (flags & SPI_CPM2)
1003 return "CPM2";
1004 else
1005 return "CPM1";
1006 }
1007 return "CPU";
1008 }
1009
1010 static struct spi_master * __devinit
1011 mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
1012 {
1013 struct fsl_spi_platform_data *pdata = dev->platform_data;
1014 struct spi_master *master;
1015 struct mpc8xxx_spi *mpc8xxx_spi;
1016 u32 regval;
1017 int ret = 0;
1018
1019 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
1020 if (master == NULL) {
1021 ret = -ENOMEM;
1022 goto err;
1023 }
1024
1025 dev_set_drvdata(dev, master);
1026
1027 /* the spi->mode bits understood by this driver: */
1028 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
1029 | SPI_LSB_FIRST | SPI_LOOP;
1030
1031 master->setup = mpc8xxx_spi_setup;
1032 master->transfer = mpc8xxx_spi_transfer;
1033 master->cleanup = mpc8xxx_spi_cleanup;
1034
1035 mpc8xxx_spi = spi_master_get_devdata(master);
1036 mpc8xxx_spi->dev = dev;
1037 mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
1038 mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
1039 mpc8xxx_spi->flags = pdata->flags;
1040 mpc8xxx_spi->spibrg = pdata->sysclk;
1041
1042 ret = mpc8xxx_spi_cpm_init(mpc8xxx_spi);
1043 if (ret)
1044 goto err_cpm_init;
1045
1046 mpc8xxx_spi->rx_shift = 0;
1047 mpc8xxx_spi->tx_shift = 0;
1048 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
1049 mpc8xxx_spi->rx_shift = 16;
1050 mpc8xxx_spi->tx_shift = 24;
1051 }
1052
1053 init_completion(&mpc8xxx_spi->done);
1054
1055 mpc8xxx_spi->base = ioremap(mem->start, resource_size(mem));
1056 if (mpc8xxx_spi->base == NULL) {
1057 ret = -ENOMEM;
1058 goto err_ioremap;
1059 }
1060
1061 mpc8xxx_spi->irq = irq;
1062
1063 /* Register for SPI Interrupt */
1064 ret = request_irq(mpc8xxx_spi->irq, mpc8xxx_spi_irq,
1065 0, "mpc8xxx_spi", mpc8xxx_spi);
1066
1067 if (ret != 0)
1068 goto unmap_io;
1069
1070 master->bus_num = pdata->bus_num;
1071 master->num_chipselect = pdata->max_chipselect;
1072
1073 /* SPI controller initializations */
1074 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, 0);
1075 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
1076 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->command, 0);
1077 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, 0xffffffff);
1078
1079 /* Enable SPI interface */
1080 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
1081 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
1082 regval |= SPMODE_OP;
1083
1084 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, regval);
1085 spin_lock_init(&mpc8xxx_spi->lock);
1086 init_completion(&mpc8xxx_spi->done);
1087 INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work);
1088 INIT_LIST_HEAD(&mpc8xxx_spi->queue);
1089
1090 mpc8xxx_spi->workqueue = create_singlethread_workqueue(
1091 dev_name(master->dev.parent));
1092 if (mpc8xxx_spi->workqueue == NULL) {
1093 ret = -EBUSY;
1094 goto free_irq;
1095 }
1096
1097 ret = spi_register_master(master);
1098 if (ret < 0)
1099 goto unreg_master;
1100
1101 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", mpc8xxx_spi->base,
1102 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
1103
1104 return master;
1105
1106 unreg_master:
1107 destroy_workqueue(mpc8xxx_spi->workqueue);
1108 free_irq:
1109 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
1110 unmap_io:
1111 iounmap(mpc8xxx_spi->base);
1112 err_ioremap:
1113 mpc8xxx_spi_cpm_free(mpc8xxx_spi);
1114 err_cpm_init:
1115 spi_master_put(master);
1116 err:
1117 return ERR_PTR(ret);
1118 }
1119
1120 static int __devexit mpc8xxx_spi_remove(struct device *dev)
1121 {
1122 struct mpc8xxx_spi *mpc8xxx_spi;
1123 struct spi_master *master;
1124
1125 master = dev_get_drvdata(dev);
1126 mpc8xxx_spi = spi_master_get_devdata(master);
1127
1128 flush_workqueue(mpc8xxx_spi->workqueue);
1129 destroy_workqueue(mpc8xxx_spi->workqueue);
1130 spi_unregister_master(master);
1131
1132 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
1133 iounmap(mpc8xxx_spi->base);
1134 mpc8xxx_spi_cpm_free(mpc8xxx_spi);
1135
1136 return 0;
1137 }
1138
1139 struct mpc8xxx_spi_probe_info {
1140 struct fsl_spi_platform_data pdata;
1141 int *gpios;
1142 bool *alow_flags;
1143 };
1144
1145 static struct mpc8xxx_spi_probe_info *
1146 to_of_pinfo(struct fsl_spi_platform_data *pdata)
1147 {
1148 return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
1149 }
1150
1151 static void mpc8xxx_spi_cs_control(struct spi_device *spi, bool on)
1152 {
1153 struct device *dev = spi->dev.parent;
1154 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
1155 u16 cs = spi->chip_select;
1156 int gpio = pinfo->gpios[cs];
1157 bool alow = pinfo->alow_flags[cs];
1158
1159 gpio_set_value(gpio, on ^ alow);
1160 }
1161
1162 static int of_mpc8xxx_spi_get_chipselects(struct device *dev)
1163 {
1164 struct device_node *np = dev->of_node;
1165 struct fsl_spi_platform_data *pdata = dev->platform_data;
1166 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
1167 unsigned int ngpios;
1168 int i = 0;
1169 int ret;
1170
1171 ngpios = of_gpio_count(np);
1172 if (!ngpios) {
1173 /*
1174 * SPI w/o chip-select line. One SPI device is still permitted
1175 * though.
1176 */
1177 pdata->max_chipselect = 1;
1178 return 0;
1179 }
1180
1181 pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
1182 if (!pinfo->gpios)
1183 return -ENOMEM;
1184 memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
1185
1186 pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
1187 GFP_KERNEL);
1188 if (!pinfo->alow_flags) {
1189 ret = -ENOMEM;
1190 goto err_alloc_flags;
1191 }
1192
1193 for (; i < ngpios; i++) {
1194 int gpio;
1195 enum of_gpio_flags flags;
1196
1197 gpio = of_get_gpio_flags(np, i, &flags);
1198 if (!gpio_is_valid(gpio)) {
1199 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
1200 ret = gpio;
1201 goto err_loop;
1202 }
1203
1204 ret = gpio_request(gpio, dev_name(dev));
1205 if (ret) {
1206 dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
1207 goto err_loop;
1208 }
1209
1210 pinfo->gpios[i] = gpio;
1211 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
1212
1213 ret = gpio_direction_output(pinfo->gpios[i],
1214 pinfo->alow_flags[i]);
1215 if (ret) {
1216 dev_err(dev, "can't set output direction for gpio "
1217 "#%d: %d\n", i, ret);
1218 goto err_loop;
1219 }
1220 }
1221
1222 pdata->max_chipselect = ngpios;
1223 pdata->cs_control = mpc8xxx_spi_cs_control;
1224
1225 return 0;
1226
1227 err_loop:
1228 while (i >= 0) {
1229 if (gpio_is_valid(pinfo->gpios[i]))
1230 gpio_free(pinfo->gpios[i]);
1231 i--;
1232 }
1233
1234 kfree(pinfo->alow_flags);
1235 pinfo->alow_flags = NULL;
1236 err_alloc_flags:
1237 kfree(pinfo->gpios);
1238 pinfo->gpios = NULL;
1239 return ret;
1240 }
1241
1242 static int of_mpc8xxx_spi_free_chipselects(struct device *dev)
1243 {
1244 struct fsl_spi_platform_data *pdata = dev->platform_data;
1245 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
1246 int i;
1247
1248 if (!pinfo->gpios)
1249 return 0;
1250
1251 for (i = 0; i < pdata->max_chipselect; i++) {
1252 if (gpio_is_valid(pinfo->gpios[i]))
1253 gpio_free(pinfo->gpios[i]);
1254 }
1255
1256 kfree(pinfo->gpios);
1257 kfree(pinfo->alow_flags);
1258 return 0;
1259 }
1260
1261 static int __devinit of_mpc8xxx_spi_probe(struct of_device *ofdev,
1262 const struct of_device_id *ofid)
1263 {
1264 struct device *dev = &ofdev->dev;
1265 struct device_node *np = ofdev->dev.of_node;
1266 struct mpc8xxx_spi_probe_info *pinfo;
1267 struct fsl_spi_platform_data *pdata;
1268 struct spi_master *master;
1269 struct resource mem;
1270 struct resource irq;
1271 const void *prop;
1272 int ret = -ENOMEM;
1273
1274 pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL);
1275 if (!pinfo)
1276 return -ENOMEM;
1277
1278 pdata = &pinfo->pdata;
1279 dev->platform_data = pdata;
1280
1281 /* Allocate bus num dynamically. */
1282 pdata->bus_num = -1;
1283
1284 /* SPI controller is either clocked from QE or SoC clock. */
1285 pdata->sysclk = get_brgfreq();
1286 if (pdata->sysclk == -1) {
1287 pdata->sysclk = fsl_get_sys_freq();
1288 if (pdata->sysclk == -1) {
1289 ret = -ENODEV;
1290 goto err_clk;
1291 }
1292 }
1293
1294 prop = of_get_property(np, "mode", NULL);
1295 if (prop && !strcmp(prop, "cpu-qe"))
1296 pdata->flags = SPI_QE_CPU_MODE;
1297 else if (prop && !strcmp(prop, "qe"))
1298 pdata->flags = SPI_CPM_MODE | SPI_QE;
1299 else if (of_device_is_compatible(np, "fsl,cpm2-spi"))
1300 pdata->flags = SPI_CPM_MODE | SPI_CPM2;
1301 else if (of_device_is_compatible(np, "fsl,cpm1-spi"))
1302 pdata->flags = SPI_CPM_MODE | SPI_CPM1;
1303
1304 ret = of_mpc8xxx_spi_get_chipselects(dev);
1305 if (ret)
1306 goto err;
1307
1308 ret = of_address_to_resource(np, 0, &mem);
1309 if (ret)
1310 goto err;
1311
1312 ret = of_irq_to_resource(np, 0, &irq);
1313 if (!ret) {
1314 ret = -EINVAL;
1315 goto err;
1316 }
1317
1318 master = mpc8xxx_spi_probe(dev, &mem, irq.start);
1319 if (IS_ERR(master)) {
1320 ret = PTR_ERR(master);
1321 goto err;
1322 }
1323
1324 of_register_spi_devices(master, np);
1325
1326 return 0;
1327
1328 err:
1329 of_mpc8xxx_spi_free_chipselects(dev);
1330 err_clk:
1331 kfree(pinfo);
1332 return ret;
1333 }
1334
1335 static int __devexit of_mpc8xxx_spi_remove(struct of_device *ofdev)
1336 {
1337 int ret;
1338
1339 ret = mpc8xxx_spi_remove(&ofdev->dev);
1340 if (ret)
1341 return ret;
1342 of_mpc8xxx_spi_free_chipselects(&ofdev->dev);
1343 return 0;
1344 }
1345
1346 static const struct of_device_id of_mpc8xxx_spi_match[] = {
1347 { .compatible = "fsl,spi" },
1348 {},
1349 };
1350 MODULE_DEVICE_TABLE(of, of_mpc8xxx_spi_match);
1351
1352 static struct of_platform_driver of_mpc8xxx_spi_driver = {
1353 .driver = {
1354 .name = "mpc8xxx_spi",
1355 .owner = THIS_MODULE,
1356 .of_match_table = of_mpc8xxx_spi_match,
1357 },
1358 .probe = of_mpc8xxx_spi_probe,
1359 .remove = __devexit_p(of_mpc8xxx_spi_remove),
1360 };
1361
1362 #ifdef CONFIG_MPC832x_RDB
1363 /*
1364 * XXX XXX XXX
1365 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
1366 * only. The driver should go away soon, since newer MPC8323E-RDB's device
1367 * tree can work with OpenFirmware driver. But for now we support old trees
1368 * as well.
1369 */
1370 static int __devinit plat_mpc8xxx_spi_probe(struct platform_device *pdev)
1371 {
1372 struct resource *mem;
1373 int irq;
1374 struct spi_master *master;
1375
1376 if (!pdev->dev.platform_data)
1377 return -EINVAL;
1378
1379 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1380 if (!mem)
1381 return -EINVAL;
1382
1383 irq = platform_get_irq(pdev, 0);
1384 if (irq <= 0)
1385 return -EINVAL;
1386
1387 master = mpc8xxx_spi_probe(&pdev->dev, mem, irq);
1388 if (IS_ERR(master))
1389 return PTR_ERR(master);
1390 return 0;
1391 }
1392
1393 static int __devexit plat_mpc8xxx_spi_remove(struct platform_device *pdev)
1394 {
1395 return mpc8xxx_spi_remove(&pdev->dev);
1396 }
1397
1398 MODULE_ALIAS("platform:mpc8xxx_spi");
1399 static struct platform_driver mpc8xxx_spi_driver = {
1400 .probe = plat_mpc8xxx_spi_probe,
1401 .remove = __devexit_p(plat_mpc8xxx_spi_remove),
1402 .driver = {
1403 .name = "mpc8xxx_spi",
1404 .owner = THIS_MODULE,
1405 },
1406 };
1407
1408 static bool legacy_driver_failed;
1409
1410 static void __init legacy_driver_register(void)
1411 {
1412 legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
1413 }
1414
1415 static void __exit legacy_driver_unregister(void)
1416 {
1417 if (legacy_driver_failed)
1418 return;
1419 platform_driver_unregister(&mpc8xxx_spi_driver);
1420 }
1421 #else
1422 static void __init legacy_driver_register(void) {}
1423 static void __exit legacy_driver_unregister(void) {}
1424 #endif /* CONFIG_MPC832x_RDB */
1425
1426 static int __init mpc8xxx_spi_init(void)
1427 {
1428 legacy_driver_register();
1429 return of_register_platform_driver(&of_mpc8xxx_spi_driver);
1430 }
1431
1432 static void __exit mpc8xxx_spi_exit(void)
1433 {
1434 of_unregister_platform_driver(&of_mpc8xxx_spi_driver);
1435 legacy_driver_unregister();
1436 }
1437
1438 module_init(mpc8xxx_spi_init);
1439 module_exit(mpc8xxx_spi_exit);
1440
1441 MODULE_AUTHOR("Kumar Gala");
1442 MODULE_DESCRIPTION("Simple MPC8xxx SPI Driver");
1443 MODULE_LICENSE("GPL");
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