arch/i386/pci/fixup.c

   1 /*
   2  * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
   3  */
   4
   5 #include <linux/delay.h>
   6 #include <linux/dmi.h>
   7 #include <linux/pci.h>
   8 #include <linux/init.h>
   9 #include "pci.h"
  10
  11
  12 static void __devinit pci_fixup_i450nx(struct pci_dev *d)
  13 {
  14         /*
  15          * i450NX -- Find and scan all secondary buses on all PXB's.
  16          */
  17         int pxb, reg;
  18         u8 busno, suba, subb;
  19
  20         printk(KERN_WARNING "PCI: Searching for i450NX host bridges on %s\n", pci_name(d));
  21         reg = 0xd0;
  22         for(pxb=0; pxb<2; pxb++) {
  23                 pci_read_config_byte(d, reg++, &busno);
  24                 pci_read_config_byte(d, reg++, &suba);
  25                 pci_read_config_byte(d, reg++, &subb);
  26                 DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
  27                 if (busno)
  28                         pci_scan_bus(busno, &pci_root_ops, NULL);       /* Bus A */
  29                 if (suba < subb)
  30                         pci_scan_bus(suba+1, &pci_root_ops, NULL);      /* Bus B */
  31         }
  32         pcibios_last_bus = -1;
  33 }
  34 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
  35
  36 static void __devinit pci_fixup_i450gx(struct pci_dev *d)
  37 {
  38         /*
  39          * i450GX and i450KX -- Find and scan all secondary buses.
  40          * (called separately for each PCI bridge found)
  41          */
  42         u8 busno;
  43         pci_read_config_byte(d, 0x4a, &busno);
  44         printk(KERN_INFO "PCI: i440KX/GX host bridge %s: secondary bus %02x\n", pci_name(d), busno);
  45         pci_scan_bus(busno, &pci_root_ops, NULL);
  46         pcibios_last_bus = -1;
  47 }
  48 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx);
  49
  50 static void __devinit  pci_fixup_umc_ide(struct pci_dev *d)
  51 {
  52         /*
  53          * UM8886BF IDE controller sets region type bits incorrectly,
  54          * therefore they look like memory despite of them being I/O.
  55          */
  56         int i;
  57
  58         printk(KERN_WARNING "PCI: Fixing base address flags for device %s\n", pci_name(d));
  59         for(i=0; i<4; i++)
  60                 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
  61 }
  62 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
  63
  64 static void __devinit  pci_fixup_ncr53c810(struct pci_dev *d)
  65 {
  66         /*
  67          * NCR 53C810 returns class code 0 (at least on some systems).
  68          * Fix class to be PCI_CLASS_STORAGE_SCSI
  69          */
  70         if (!d->class) {
  71                 printk(KERN_WARNING "PCI: fixing NCR 53C810 class code for %s\n", pci_name(d));
  72                 d->class = PCI_CLASS_STORAGE_SCSI << 8;
  73         }
  74 }
  75 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810);
  76
  77 static void __devinit  pci_fixup_latency(struct pci_dev *d)
  78 {
  79         /*
  80          *  SiS 5597 and 5598 chipsets require latency timer set to
  81          *  at most 32 to avoid lockups.
  82          */
  83         DBG("PCI: Setting max latency to 32\n");
  84         pcibios_max_latency = 32;
  85 }
  86 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
  87 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
  88
  89 static void __devinit pci_fixup_piix4_acpi(struct pci_dev *d)
  90 {
  91         /*
  92          * PIIX4 ACPI device: hardwired IRQ9
  93          */
  94         d->irq = 9;
  95 }
  96 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi);
  97
  98 /*
  99  * Addresses issues with problems in the memory write queue timer in
 100  * certain VIA Northbridges.  This bugfix is per VIA's specifications,
 101  * except for the KL133/KM133: clearing bit 5 on those Northbridges seems
 102  * to trigger a bug in its integrated ProSavage video card, which
 103  * causes screen corruption.  We only clear bits 6 and 7 for that chipset,
 104  * until VIA can provide us with definitive information on why screen
 105  * corruption occurs, and what exactly those bits do.
 106  *
 107  * VIA 8363,8622,8361 Northbridges:
 108  *  - bits  5, 6, 7 at offset 0x55 need to be turned off
 109  * VIA 8367 (KT266x) Northbridges:
 110  *  - bits  5, 6, 7 at offset 0x95 need to be turned off
 111  * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
 112  *  - bits     6, 7 at offset 0x55 need to be turned off
 113  */
 114
 115 #define VIA_8363_KL133_REVISION_ID 0x81
 116 #define VIA_8363_KM133_REVISION_ID 0x84
 117
 118 static void pci_fixup_via_northbridge_bug(struct pci_dev *d)
 119 {
 120         u8 v;
 121         u8 revision;
 122         int where = 0x55;
 123         int mask = 0x1f; /* clear bits 5, 6, 7 by default */
 124
 125         pci_read_config_byte(d, PCI_REVISION_ID, &revision);
 126
 127         if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
 128                 /* fix pci bus latency issues resulted by NB bios error
 129                    it appears on bug free^Wreduced kt266x's bios forces
 130                    NB latency to zero */
 131                 pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
 132
 133                 where = 0x95; /* the memory write queue timer register is
 134                                 different for the KT266x's: 0x95 not 0x55 */
 135         } else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
 136                         (revision == VIA_8363_KL133_REVISION_ID ||
 137                         revision == VIA_8363_KM133_REVISION_ID)) {
 138                         mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
 139                                         causes screen corruption on the KL133/KM133 */
 140         }
 141
 142         pci_read_config_byte(d, where, &v);
 143         if (v & ~mask) {
 144                 printk(KERN_WARNING "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
 145                         d->device, revision, where, v, mask, v & mask);
 146                 v &= mask;
 147                 pci_write_config_byte(d, where, v);
 148         }
 149 }
 150 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
 151 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
 152 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
 153 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
 154 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
 155 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
 156 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
 157 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
 158
 159 /*
 160  * For some reasons Intel decided that certain parts of their
 161  * 815, 845 and some other chipsets must look like PCI-to-PCI bridges
 162  * while they are obviously not. The 82801 family (AA, AB, BAM/CAM,
 163  * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according
 164  * to Intel terminology. These devices do forward all addresses from
 165  * system to PCI bus no matter what are their window settings, so they are
 166  * "transparent" (or subtractive decoding) from programmers point of view.
 167  */
 168 static void __devinit pci_fixup_transparent_bridge(struct pci_dev *dev)
 169 {
 170         if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
 171             (dev->device & 0xff00) == 0x2400)
 172                 dev->transparent = 1;
 173 }
 174 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_bridge);
 175
 176 /*
 177  * Fixup for C1 Halt Disconnect problem on nForce2 systems.
 178  *
 179  * From information provided by "Allen Martin" <AMartin@nvidia.com>:
 180  *
 181  * A hang is caused when the CPU generates a very fast CONNECT/HALT cycle
 182  * sequence.  Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns.
 183  * This allows the state-machine and timer to return to a proper state within
 184  * 80 ns of the CONNECT and probe appearing together.  Since the CPU will not
 185  * issue another HALT within 80 ns of the initial HALT, the failure condition
 186  * is avoided.
 187  */
 188 static void pci_fixup_nforce2(struct pci_dev *dev)
 189 {
 190         u32 val;
 191
 192         /*
 193          * Chip  Old value   New value
 194          * C17   0x1F0FFF01  0x1F01FF01
 195          * C18D  0x9F0FFF01  0x9F01FF01
 196          *
 197          * Northbridge chip version may be determined by
 198          * reading the PCI revision ID (0xC1 or greater is C18D).
 199          */
 200         pci_read_config_dword(dev, 0x6c, &val);
 201
 202         /*
 203          * Apply fixup if needed, but don't touch disconnect state
 204          */
 205         if ((val & 0x00FF0000) != 0x00010000) {
 206                 printk(KERN_WARNING "PCI: nForce2 C1 Halt Disconnect fixup\n");
 207                 pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000);
 208         }
 209 }
 210 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
 211 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
 212
 213 /* Max PCI Express root ports */
 214 #define MAX_PCIEROOT    6
 215 static int quirk_aspm_offset[MAX_PCIEROOT << 3];
 216
 217 #define GET_INDEX(a, b) ((((a) - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + ((b) & 7))
 218
 219 static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
 220 {
 221         return raw_pci_ops->read(0, bus->number, devfn, where, size, value);
 222 }
 223
 224 /*
 225  * Replace the original pci bus ops for write with a new one that will filter
 226  * the request to insure ASPM cannot be enabled.
 227  */
 228 static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
 229 {
 230         u8 offset;
 231
 232         offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)];
 233
 234         if ((offset) && (where == offset))
 235                 value = value & 0xfffffffc;
 236
 237         return raw_pci_ops->write(0, bus->number, devfn, where, size, value);
 238 }
 239
 240 static struct pci_ops quirk_pcie_aspm_ops = {
 241         .read = quirk_pcie_aspm_read,
 242         .write = quirk_pcie_aspm_write,
 243 };
 244
 245 /*
 246  * Prevents PCI Express ASPM (Active State Power Management) being enabled.
 247  *
 248  * Save the register offset, where the ASPM control bits are located,
 249  * for each PCI Express device that is in the device list of
 250  * the root port in an array for fast indexing. Replace the bus ops
 251  * with the modified one.
 252  */
 253 static void pcie_rootport_aspm_quirk(struct pci_dev *pdev)
 254 {
 255         int cap_base, i;
 256         struct pci_bus  *pbus;
 257         struct pci_dev *dev;
 258
 259         if ((pbus = pdev->subordinate) == NULL)
 260                 return;
 261
 262         /*
 263          * Check if the DID of pdev matches one of the six root ports. This
 264          * check is needed in the case this function is called directly by the
 265          * hot-plug driver.
 266          */
 267         if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) ||
 268             (pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1))
 269                 return;
 270
 271         if (list_empty(&pbus->devices)) {
 272                 /*
 273                  * If no device is attached to the root port at power-up or
 274                  * after hot-remove, the pbus->devices is empty and this code
 275                  * will set the offsets to zero and the bus ops to parent's bus
 276                  * ops, which is unmodified.
 277                  */
 278                 for (i= GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i)
 279                         quirk_aspm_offset[i] = 0;
 280
 281                 pbus->ops = pbus->parent->ops;
 282         } else {
 283                 /*
 284                  * If devices are attached to the root port at power-up or
 285                  * after hot-add, the code loops through the device list of
 286                  * each root port to save the register offsets and replace the
 287                  * bus ops.
 288                  */
 289                 list_for_each_entry(dev, &pbus->devices, bus_list) {
 290                         /* There are 0 to 8 devices attached to this bus */
 291                         cap_base = pci_find_capability(dev, PCI_CAP_ID_EXP);
 292                         quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)]= cap_base + 0x10;
 293                 }
 294                 pbus->ops = &quirk_pcie_aspm_ops;
 295         }
 296 }
 297 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_MCH_PA,     pcie_rootport_aspm_quirk );
 298 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_MCH_PA1,    pcie_rootport_aspm_quirk );
 299 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_MCH_PB,     pcie_rootport_aspm_quirk );
 300 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_MCH_PB1,    pcie_rootport_aspm_quirk );
 301 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_MCH_PC,     pcie_rootport_aspm_quirk );
 302 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_MCH_PC1,    pcie_rootport_aspm_quirk );
 303
 304 /*
 305  * Fixup to mark boot BIOS video selected by BIOS before it changes
 306  *
 307  * From information provided by "Jon Smirl" <jonsmirl@gmail.com>
 308  *
 309  * The standard boot ROM sequence for an x86 machine uses the BIOS
 310  * to select an initial video card for boot display. This boot video
 311  * card will have it's BIOS copied to C0000 in system RAM.
 312  * IORESOURCE_ROM_SHADOW is used to associate the boot video
 313  * card with this copy. On laptops this copy has to be used since
 314  * the main ROM may be compressed or combined with another image.
 315  * See pci_map_rom() for use of this flag. IORESOURCE_ROM_SHADOW
 316  * is marked here since the boot video device will be the only enabled
 317  * video device at this point.
 318  */
 319
 320 static void __devinit pci_fixup_video(struct pci_dev *pdev)
 321 {
 322         struct pci_dev *bridge;
 323         struct pci_bus *bus;
 324         u16 config;
 325
 326         if ((pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
 327                 return;
 328
 329         /* Is VGA routed to us? */
 330         bus = pdev->bus;
 331         while (bus) {
 332                 bridge = bus->self;
 333
 334                 /*
 335                  * From information provided by
 336                  * "David Miller" <davem@davemloft.net>
 337                  * The bridge control register is valid for PCI header
 338                  * type BRIDGE, or CARDBUS. Host to PCI controllers use
 339                  * PCI header type NORMAL.
 340                  */
 341                 if (bridge
 342                     &&((bridge->hdr_type == PCI_HEADER_TYPE_BRIDGE)
 343                        ||(bridge->hdr_type == PCI_HEADER_TYPE_CARDBUS))) {
 344                         pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
 345                                                 &config);
 346                         if (!(config & PCI_BRIDGE_CTL_VGA))
 347                                 return;
 348                 }
 349                 bus = bus->parent;
 350         }
 351         pci_read_config_word(pdev, PCI_COMMAND, &config);
 352         if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
 353                 pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW;
 354                 printk(KERN_DEBUG "Boot video device is %s\n", pci_name(pdev));
 355         }
 356 }
 357 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video);
 358
 359 /*
 360  * Some Toshiba laptops need extra code to enable their TI TSB43AB22/A.
 361  *
 362  * We pretend to bring them out of full D3 state, and restore the proper
 363  * IRQ, PCI cache line size, and BARs, otherwise the device won't function
 364  * properly.  In some cases, the device will generate an interrupt on
 365  * the wrong IRQ line, causing any devices sharing the line it's
 366  * *supposed* to use to be disabled by the kernel's IRQ debug code.
 367  */
 368 static u16 toshiba_line_size;
 369
 370 static struct dmi_system_id __devinitdata toshiba_ohci1394_dmi_table[] = {
 371         {
 372                 .ident = "Toshiba PS5 based laptop",
 373                 .matches = {
 374                         DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 375                         DMI_MATCH(DMI_PRODUCT_VERSION, "PS5"),
 376                 },
 377         },
 378         {
 379                 .ident = "Toshiba PSM4 based laptop",
 380                 .matches = {
 381                         DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 382                         DMI_MATCH(DMI_PRODUCT_VERSION, "PSM4"),
 383                 },
 384         },
 385         {
 386                 .ident = "Toshiba A40 based laptop",
 387                 .matches = {
 388                         DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 389                         DMI_MATCH(DMI_PRODUCT_VERSION, "PSA40U"),
 390                 },
 391         },
 392         { }
 393 };
 394
 395 static void __devinit pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev)
 396 {
 397         if (!dmi_check_system(toshiba_ohci1394_dmi_table))
 398                 return; /* only applies to certain Toshibas (so far) */
 399
 400         dev->current_state = PCI_D3cold;
 401         pci_read_config_word(dev, PCI_CACHE_LINE_SIZE, &toshiba_line_size);
 402 }
 403 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032,
 404                          pci_pre_fixup_toshiba_ohci1394);
 405
 406 static void __devinit pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev)
 407 {
 408         if (!dmi_check_system(toshiba_ohci1394_dmi_table))
 409                 return; /* only applies to certain Toshibas (so far) */
 410
 411         /* Restore config space on Toshiba laptops */
 412         pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size);
 413         pci_read_config_byte(dev, PCI_INTERRUPT_LINE, (u8 *)&dev->irq);
 414         pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
 415                                pci_resource_start(dev, 0));
 416         pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
 417                                pci_resource_start(dev, 1));
 418 }
 419 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032,
 420                          pci_post_fixup_toshiba_ohci1394);
 421
 422
 423 /*
 424  * Prevent the BIOS trapping accesses to the Cyrix CS5530A video device
 425  * configuration space.
 426  */
 427 static void pci_early_fixup_cyrix_5530(struct pci_dev *dev)
 428 {
 429         u8 r;
 430         /* clear 'F4 Video Configuration Trap' bit */
 431         pci_read_config_byte(dev, 0x42, &r);
 432         r &= 0xfd;
 433         pci_write_config_byte(dev, 0x42, r);
 434 }
 435 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
 436                         pci_early_fixup_cyrix_5530);
 437 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
 438                         pci_early_fixup_cyrix_5530);