arch/mips/philips/pnx8550/common/time.c

   1 /*
   2  * Copyright 2001, 2002, 2003 MontaVista Software Inc.
   3  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
   4  *
   5  * Common time service routines for MIPS machines. See
   6  * Documents/MIPS/README.txt.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13 #include <linux/types.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/sched.h>
  17 #include <linux/param.h>
  18 #include <linux/time.h>
  19 #include <linux/timer.h>
  20 #include <linux/smp.h>
  21 #include <linux/kernel_stat.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25
  26 #include <asm/bootinfo.h>
  27 #include <asm/cpu.h>
  28 #include <asm/time.h>
  29 #include <asm/hardirq.h>
  30 #include <asm/div64.h>
  31 #include <asm/debug.h>
  32
  33 #include <int.h>
  34 #include <cm.h>
  35
  36 static unsigned long cpj;
  37
  38 static cycle_t hpt_read(void)
  39 {
  40         return read_c0_count2();
  41 }
  42
  43 static void timer_ack(void)
  44 {
  45         write_c0_compare(cpj);
  46 }
  47
  48 /*
  49  * pnx8550_time_init() - it does the following things:
  50  *
  51  * 1) board_time_init() -
  52  *      a) (optional) set up RTC routines,
  53  *      b) (optional) calibrate and set the mips_hpt_frequency
  54  *          (only needed if you intended to use cpu counter as timer interrupt
  55  *           source)
  56  */
  57
  58 void pnx8550_time_init(void)
  59 {
  60         unsigned int             n;
  61         unsigned int             m;
  62         unsigned int             p;
  63         unsigned int             pow2p;
  64
  65         /* PLL0 sets MIPS clock (PLL1 <=> TM1, PLL6 <=> TM2, PLL5 <=> mem) */
  66         /* (but only if CLK_MIPS_CTL select value [bits 3:1] is 1:  FIXME) */
  67
  68         n = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_N_MASK) >> 16;
  69         m = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_M_MASK) >> 8;
  70         p = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_P_MASK) >> 2;
  71         pow2p = (1 << p);
  72
  73         db_assert(m != 0 && pow2p != 0);
  74
  75         /*
  76          * Compute the frequency as in the PNX8550 User Manual 1.0, p.186
  77          * (a.k.a. 8-10).  Divide by HZ for a timer offset that results in
  78          * HZ timer interrupts per second.
  79          */
  80         mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p));
  81         cpj = (mips_hpt_frequency + HZ / 2) / HZ;
  82         write_c0_count(0);
  83         timer_ack();
  84
  85         /* Setup Timer 2 */
  86         write_c0_count2(0);
  87         write_c0_compare2(0xffffffff);
  88
  89         clocksource_mips.read = hpt_read;
  90         mips_timer_ack = timer_ack;
  91 }
  92
  93 static irqreturn_t monotonic_interrupt(int irq, void *dev_id)
  94 {
  95         /* Timer 2 clear interrupt */
  96         write_c0_compare2(-1);
  97         return IRQ_HANDLED;
  98 }
  99
 100 static struct irqaction monotonic_irqaction = {
 101         .handler = monotonic_interrupt,
 102         .flags = IRQF_DISABLED,
 103         .name = "Monotonic timer",
 104 };
 105
 106 void __init plat_timer_setup(struct irqaction *irq)
 107 {
 108         int configPR;
 109
 110         setup_irq(PNX8550_INT_TIMER1, irq);
 111         setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction);
 112
 113         /* Timer 1 start */
 114         configPR = read_c0_config7();
 115         configPR &= ~0x00000008;
 116         write_c0_config7(configPR);
 117
 118         /* Timer 2 start */
 119         configPR = read_c0_config7();
 120         configPR &= ~0x00000010;
 121         write_c0_config7(configPR);
 122
 123         /* Timer 3 stop */
 124         configPR = read_c0_config7();
 125         configPR |= 0x00000020;
 126         write_c0_config7(configPR);
 127 }