Linux 2.6.22-rc3
[linux-2.6/next.git] / arch / x86_64 / kernel / hpet.c
blobb8286968662d0d19d21a99443f604016e0883ce2
1 #include <linux/kernel.h>
2 #include <linux/sched.h>
3 #include <linux/init.h>
4 #include <linux/mc146818rtc.h>
5 #include <linux/time.h>
6 #include <linux/clocksource.h>
7 #include <linux/ioport.h>
8 #include <linux/acpi.h>
9 #include <linux/hpet.h>
10 #include <asm/pgtable.h>
11 #include <asm/vsyscall.h>
12 #include <asm/timex.h>
13 #include <asm/hpet.h>
15 #define HPET_MASK 0xFFFFFFFF
16 #define HPET_SHIFT 22
18 /* FSEC = 10^-15 NSEC = 10^-9 */
19 #define FSEC_PER_NSEC 1000000
21 int nohpet __initdata;
23 unsigned long hpet_address;
24 unsigned long hpet_period; /* fsecs / HPET clock */
25 unsigned long hpet_tick; /* HPET clocks / interrupt */
27 int hpet_use_timer; /* Use counter of hpet for time keeping,
28 * otherwise PIT
31 #ifdef CONFIG_HPET
32 static __init int late_hpet_init(void)
34 struct hpet_data hd;
35 unsigned int ntimer;
37 if (!hpet_address)
38 return 0;
40 memset(&hd, 0, sizeof(hd));
42 ntimer = hpet_readl(HPET_ID);
43 ntimer = (ntimer & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
44 ntimer++;
47 * Register with driver.
48 * Timer0 and Timer1 is used by platform.
50 hd.hd_phys_address = hpet_address;
51 hd.hd_address = (void __iomem *)fix_to_virt(FIX_HPET_BASE);
52 hd.hd_nirqs = ntimer;
53 hd.hd_flags = HPET_DATA_PLATFORM;
54 hpet_reserve_timer(&hd, 0);
55 #ifdef CONFIG_HPET_EMULATE_RTC
56 hpet_reserve_timer(&hd, 1);
57 #endif
58 hd.hd_irq[0] = HPET_LEGACY_8254;
59 hd.hd_irq[1] = HPET_LEGACY_RTC;
60 if (ntimer > 2) {
61 struct hpet *hpet;
62 struct hpet_timer *timer;
63 int i;
65 hpet = (struct hpet *) fix_to_virt(FIX_HPET_BASE);
66 timer = &hpet->hpet_timers[2];
67 for (i = 2; i < ntimer; timer++, i++)
68 hd.hd_irq[i] = (timer->hpet_config &
69 Tn_INT_ROUTE_CNF_MASK) >>
70 Tn_INT_ROUTE_CNF_SHIFT;
74 hpet_alloc(&hd);
75 return 0;
77 fs_initcall(late_hpet_init);
78 #endif
80 int hpet_timer_stop_set_go(unsigned long tick)
82 unsigned int cfg;
85 * Stop the timers and reset the main counter.
88 cfg = hpet_readl(HPET_CFG);
89 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
90 hpet_writel(cfg, HPET_CFG);
91 hpet_writel(0, HPET_COUNTER);
92 hpet_writel(0, HPET_COUNTER + 4);
95 * Set up timer 0, as periodic with first interrupt to happen at hpet_tick,
96 * and period also hpet_tick.
98 if (hpet_use_timer) {
99 hpet_writel(HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
100 HPET_TN_32BIT, HPET_T0_CFG);
101 hpet_writel(hpet_tick, HPET_T0_CMP); /* next interrupt */
102 hpet_writel(hpet_tick, HPET_T0_CMP); /* period */
103 cfg |= HPET_CFG_LEGACY;
106 * Go!
109 cfg |= HPET_CFG_ENABLE;
110 hpet_writel(cfg, HPET_CFG);
112 return 0;
115 static cycle_t read_hpet(void)
117 return (cycle_t)hpet_readl(HPET_COUNTER);
120 static cycle_t __vsyscall_fn vread_hpet(void)
122 return readl((void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
125 struct clocksource clocksource_hpet = {
126 .name = "hpet",
127 .rating = 250,
128 .read = read_hpet,
129 .mask = (cycle_t)HPET_MASK,
130 .mult = 0, /* set below */
131 .shift = HPET_SHIFT,
132 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
133 .vread = vread_hpet,
136 int hpet_arch_init(void)
138 unsigned int id;
139 u64 tmp;
141 if (!hpet_address)
142 return -1;
143 set_fixmap_nocache(FIX_HPET_BASE, hpet_address);
144 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
147 * Read the period, compute tick and quotient.
150 id = hpet_readl(HPET_ID);
152 if (!(id & HPET_ID_VENDOR) || !(id & HPET_ID_NUMBER))
153 return -1;
155 hpet_period = hpet_readl(HPET_PERIOD);
156 if (hpet_period < 100000 || hpet_period > 100000000)
157 return -1;
159 hpet_tick = (FSEC_PER_TICK + hpet_period / 2) / hpet_period;
161 hpet_use_timer = (id & HPET_ID_LEGSUP);
164 * hpet period is in femto seconds per cycle
165 * so we need to convert this to ns/cyc units
166 * aproximated by mult/2^shift
168 * fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift
169 * fsec/cyc * 1ns/1000000fsec * 2^shift = mult
170 * fsec/cyc * 2^shift * 1nsec/1000000fsec = mult
171 * (fsec/cyc << shift)/1000000 = mult
172 * (hpet_period << shift)/FSEC_PER_NSEC = mult
174 tmp = (u64)hpet_period << HPET_SHIFT;
175 do_div(tmp, FSEC_PER_NSEC);
176 clocksource_hpet.mult = (u32)tmp;
177 clocksource_register(&clocksource_hpet);
179 return hpet_timer_stop_set_go(hpet_tick);
182 int hpet_reenable(void)
184 return hpet_timer_stop_set_go(hpet_tick);
188 * calibrate_tsc() calibrates the processor TSC in a very simple way, comparing
189 * it to the HPET timer of known frequency.
192 #define TICK_COUNT 100000000
193 #define TICK_MIN 5000
194 #define MAX_TRIES 5
197 * Some platforms take periodic SMI interrupts with 5ms duration. Make sure none
198 * occurs between the reads of the hpet & TSC.
200 static void __init read_hpet_tsc(int *hpet, int *tsc)
202 int tsc1, tsc2, hpet1, i;
204 for (i = 0; i < MAX_TRIES; i++) {
205 tsc1 = get_cycles_sync();
206 hpet1 = hpet_readl(HPET_COUNTER);
207 tsc2 = get_cycles_sync();
208 if (tsc2 - tsc1 > TICK_MIN)
209 break;
211 *hpet = hpet1;
212 *tsc = tsc2;
215 unsigned int __init hpet_calibrate_tsc(void)
217 int tsc_start, hpet_start;
218 int tsc_now, hpet_now;
219 unsigned long flags;
221 local_irq_save(flags);
223 read_hpet_tsc(&hpet_start, &tsc_start);
225 do {
226 local_irq_disable();
227 read_hpet_tsc(&hpet_now, &tsc_now);
228 local_irq_restore(flags);
229 } while ((tsc_now - tsc_start) < TICK_COUNT &&
230 (hpet_now - hpet_start) < TICK_COUNT);
232 return (tsc_now - tsc_start) * 1000000000L
233 / ((hpet_now - hpet_start) * hpet_period / 1000);
236 #ifdef CONFIG_HPET_EMULATE_RTC
237 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
238 * is enabled, we support RTC interrupt functionality in software.
239 * RTC has 3 kinds of interrupts:
240 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
241 * is updated
242 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
243 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
244 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
245 * (1) and (2) above are implemented using polling at a frequency of
246 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
247 * overhead. (DEFAULT_RTC_INT_FREQ)
248 * For (3), we use interrupts at 64Hz or user specified periodic
249 * frequency, whichever is higher.
251 #include <linux/rtc.h>
253 #define DEFAULT_RTC_INT_FREQ 64
254 #define RTC_NUM_INTS 1
256 static unsigned long UIE_on;
257 static unsigned long prev_update_sec;
259 static unsigned long AIE_on;
260 static struct rtc_time alarm_time;
262 static unsigned long PIE_on;
263 static unsigned long PIE_freq = DEFAULT_RTC_INT_FREQ;
264 static unsigned long PIE_count;
266 static unsigned long hpet_rtc_int_freq; /* RTC interrupt frequency */
267 static unsigned int hpet_t1_cmp; /* cached comparator register */
269 int is_hpet_enabled(void)
271 return hpet_address != 0;
275 * Timer 1 for RTC, we do not use periodic interrupt feature,
276 * even if HPET supports periodic interrupts on Timer 1.
277 * The reason being, to set up a periodic interrupt in HPET, we need to
278 * stop the main counter. And if we do that everytime someone diables/enables
279 * RTC, we will have adverse effect on main kernel timer running on Timer 0.
280 * So, for the time being, simulate the periodic interrupt in software.
282 * hpet_rtc_timer_init() is called for the first time and during subsequent
283 * interuppts reinit happens through hpet_rtc_timer_reinit().
285 int hpet_rtc_timer_init(void)
287 unsigned int cfg, cnt;
288 unsigned long flags;
290 if (!is_hpet_enabled())
291 return 0;
293 * Set the counter 1 and enable the interrupts.
295 if (PIE_on && (PIE_freq > DEFAULT_RTC_INT_FREQ))
296 hpet_rtc_int_freq = PIE_freq;
297 else
298 hpet_rtc_int_freq = DEFAULT_RTC_INT_FREQ;
300 local_irq_save(flags);
302 cnt = hpet_readl(HPET_COUNTER);
303 cnt += ((hpet_tick*HZ)/hpet_rtc_int_freq);
304 hpet_writel(cnt, HPET_T1_CMP);
305 hpet_t1_cmp = cnt;
307 cfg = hpet_readl(HPET_T1_CFG);
308 cfg &= ~HPET_TN_PERIODIC;
309 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
310 hpet_writel(cfg, HPET_T1_CFG);
312 local_irq_restore(flags);
314 return 1;
317 static void hpet_rtc_timer_reinit(void)
319 unsigned int cfg, cnt, ticks_per_int, lost_ints;
321 if (unlikely(!(PIE_on | AIE_on | UIE_on))) {
322 cfg = hpet_readl(HPET_T1_CFG);
323 cfg &= ~HPET_TN_ENABLE;
324 hpet_writel(cfg, HPET_T1_CFG);
325 return;
328 if (PIE_on && (PIE_freq > DEFAULT_RTC_INT_FREQ))
329 hpet_rtc_int_freq = PIE_freq;
330 else
331 hpet_rtc_int_freq = DEFAULT_RTC_INT_FREQ;
333 /* It is more accurate to use the comparator value than current count.*/
334 ticks_per_int = hpet_tick * HZ / hpet_rtc_int_freq;
335 hpet_t1_cmp += ticks_per_int;
336 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
339 * If the interrupt handler was delayed too long, the write above tries
340 * to schedule the next interrupt in the past and the hardware would
341 * not interrupt until the counter had wrapped around.
342 * So we have to check that the comparator wasn't set to a past time.
344 cnt = hpet_readl(HPET_COUNTER);
345 if (unlikely((int)(cnt - hpet_t1_cmp) > 0)) {
346 lost_ints = (cnt - hpet_t1_cmp) / ticks_per_int + 1;
347 /* Make sure that, even with the time needed to execute
348 * this code, the next scheduled interrupt has been moved
349 * back to the future: */
350 lost_ints++;
352 hpet_t1_cmp += lost_ints * ticks_per_int;
353 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
355 if (PIE_on)
356 PIE_count += lost_ints;
358 if (printk_ratelimit())
359 printk(KERN_WARNING "rtc: lost some interrupts at %ldHz.\n",
360 hpet_rtc_int_freq);
365 * The functions below are called from rtc driver.
366 * Return 0 if HPET is not being used.
367 * Otherwise do the necessary changes and return 1.
369 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
371 if (!is_hpet_enabled())
372 return 0;
374 if (bit_mask & RTC_UIE)
375 UIE_on = 0;
376 if (bit_mask & RTC_PIE)
377 PIE_on = 0;
378 if (bit_mask & RTC_AIE)
379 AIE_on = 0;
381 return 1;
384 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
386 int timer_init_reqd = 0;
388 if (!is_hpet_enabled())
389 return 0;
391 if (!(PIE_on | AIE_on | UIE_on))
392 timer_init_reqd = 1;
394 if (bit_mask & RTC_UIE) {
395 UIE_on = 1;
397 if (bit_mask & RTC_PIE) {
398 PIE_on = 1;
399 PIE_count = 0;
401 if (bit_mask & RTC_AIE) {
402 AIE_on = 1;
405 if (timer_init_reqd)
406 hpet_rtc_timer_init();
408 return 1;
411 int hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec)
413 if (!is_hpet_enabled())
414 return 0;
416 alarm_time.tm_hour = hrs;
417 alarm_time.tm_min = min;
418 alarm_time.tm_sec = sec;
420 return 1;
423 int hpet_set_periodic_freq(unsigned long freq)
425 if (!is_hpet_enabled())
426 return 0;
428 PIE_freq = freq;
429 PIE_count = 0;
431 return 1;
434 int hpet_rtc_dropped_irq(void)
436 if (!is_hpet_enabled())
437 return 0;
439 return 1;
442 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
444 struct rtc_time curr_time;
445 unsigned long rtc_int_flag = 0;
446 int call_rtc_interrupt = 0;
448 hpet_rtc_timer_reinit();
450 if (UIE_on | AIE_on) {
451 rtc_get_rtc_time(&curr_time);
453 if (UIE_on) {
454 if (curr_time.tm_sec != prev_update_sec) {
455 /* Set update int info, call real rtc int routine */
456 call_rtc_interrupt = 1;
457 rtc_int_flag = RTC_UF;
458 prev_update_sec = curr_time.tm_sec;
461 if (PIE_on) {
462 PIE_count++;
463 if (PIE_count >= hpet_rtc_int_freq/PIE_freq) {
464 /* Set periodic int info, call real rtc int routine */
465 call_rtc_interrupt = 1;
466 rtc_int_flag |= RTC_PF;
467 PIE_count = 0;
470 if (AIE_on) {
471 if ((curr_time.tm_sec == alarm_time.tm_sec) &&
472 (curr_time.tm_min == alarm_time.tm_min) &&
473 (curr_time.tm_hour == alarm_time.tm_hour)) {
474 /* Set alarm int info, call real rtc int routine */
475 call_rtc_interrupt = 1;
476 rtc_int_flag |= RTC_AF;
479 if (call_rtc_interrupt) {
480 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
481 rtc_interrupt(rtc_int_flag, dev_id);
483 return IRQ_HANDLED;
485 #endif
487 static int __init nohpet_setup(char *s)
489 nohpet = 1;
490 return 1;
493 __setup("nohpet", nohpet_setup);