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Linux 2.6.22-rc3
[linux-2.6/next.git] / drivers / ata / ata_piix.c
blob9c07b88631be6d50635d292d67fa632996c57e4f
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
83 */
84
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94
95 #define DRV_NAME "ata_piix"
96 #define DRV_VERSION "2.11"
97
98 enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
102 PIIX_SCC = 0x0A, /* sub-class code register */
103
104 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
105 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
106 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
107
108 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
109 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
110
111 /* combined mode. if set, PATA is channel 0.
112 * if clear, PATA is channel 1.
113 */
114 PIIX_PORT_ENABLED = (1 << 0),
115 PIIX_PORT_PRESENT = (1 << 4),
116
117 PIIX_80C_PRI = (1 << 5) | (1 << 4),
118 PIIX_80C_SEC = (1 << 7) | (1 << 6),
119
120 /* controller IDs */
121 piix_pata_33 = 0, /* PIIX4 at 33Mhz */
122 ich_pata_33 = 1, /* ICH up to UDMA 33 only */
123 ich_pata_66 = 2, /* ICH up to 66 Mhz */
124 ich_pata_100 = 3, /* ICH up to UDMA 100 */
125 ich_pata_133 = 4, /* ICH up to UDMA 133 */
126 ich5_sata = 5,
127 ich6_sata = 6,
128 ich6_sata_ahci = 7,
129 ich6m_sata_ahci = 8,
130 ich8_sata_ahci = 9,
131 piix_pata_mwdma = 10, /* PIIX3 MWDMA only */
132
133 /* constants for mapping table */
134 P0 = 0, /* port 0 */
135 P1 = 1, /* port 1 */
136 P2 = 2, /* port 2 */
137 P3 = 3, /* port 3 */
138 IDE = -1, /* IDE */
139 NA = -2, /* not avaliable */
140 RV = -3, /* reserved */
141
142 PIIX_AHCI_DEVICE = 6,
143 };
144
145 struct piix_map_db {
146 const u32 mask;
147 const u16 port_enable;
148 const int map[][4];
149 };
150
151 struct piix_host_priv {
152 const int *map;
153 };
154
155 static int piix_init_one (struct pci_dev *pdev,
156 const struct pci_device_id *ent);
157 static void piix_pata_error_handler(struct ata_port *ap);
158 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
159 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
160 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev);
161 static int ich_pata_cable_detect(struct ata_port *ap);
162
163 static unsigned int in_module_init = 1;
164
165 static const struct pci_device_id piix_pci_tbl[] = {
166 /* Intel PIIX3 for the 430HX etc */
167 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
168 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
169 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
170 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
171 /* Intel PIIX4 */
172 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
173 /* Intel PIIX4 */
174 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
175 /* Intel PIIX */
176 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
177 /* Intel ICH (i810, i815, i840) UDMA 66*/
178 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
179 /* Intel ICH0 : UDMA 33*/
180 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
181 /* Intel ICH2M */
182 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
183 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
184 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
185 /* Intel ICH3M */
186 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
187 /* Intel ICH3 (E7500/1) UDMA 100 */
188 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
189 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
190 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
191 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
192 /* Intel ICH5 */
193 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
194 /* C-ICH (i810E2) */
195 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
196 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
197 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
198 /* ICH6 (and 6) (i915) UDMA 100 */
199 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
200 /* ICH7/7-R (i945, i975) UDMA 100*/
201 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
202 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203
204 /* NOTE: The following PCI ids must be kept in sync with the
205 * list in drivers/pci/quirks.c.
206 */
207
208 /* 82801EB (ICH5) */
209 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
210 /* 82801EB (ICH5) */
211 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
212 /* 6300ESB (ICH5 variant with broken PCS present bits) */
213 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
214 /* 6300ESB pretending RAID */
215 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
216 /* 82801FB/FW (ICH6/ICH6W) */
217 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
218 /* 82801FR/FRW (ICH6R/ICH6RW) */
219 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
220 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
221 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
222 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
223 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
224 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
225 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
226 /* Enterprise Southbridge 2 (631xESB/632xESB) */
227 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
228 /* SATA Controller 1 IDE (ICH8) */
229 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
230 /* SATA Controller 2 IDE (ICH8) */
231 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
232 /* Mobile SATA Controller IDE (ICH8M) */
233 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
234 /* SATA Controller IDE (ICH9) */
235 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
236 /* SATA Controller IDE (ICH9) */
237 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
238 /* SATA Controller IDE (ICH9) */
239 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
240 /* SATA Controller IDE (ICH9M) */
241 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
242 /* SATA Controller IDE (ICH9M) */
243 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
244 /* SATA Controller IDE (ICH9M) */
245 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
246
247 { } /* terminate list */
248 };
249
250 static struct pci_driver piix_pci_driver = {
251 .name = DRV_NAME,
252 .id_table = piix_pci_tbl,
253 .probe = piix_init_one,
254 .remove = ata_pci_remove_one,
255 #ifdef CONFIG_PM
256 .suspend = ata_pci_device_suspend,
257 .resume = ata_pci_device_resume,
258 #endif
259 };
260
261 static struct scsi_host_template piix_sht = {
262 .module = THIS_MODULE,
263 .name = DRV_NAME,
264 .ioctl = ata_scsi_ioctl,
265 .queuecommand = ata_scsi_queuecmd,
266 .can_queue = ATA_DEF_QUEUE,
267 .this_id = ATA_SHT_THIS_ID,
268 .sg_tablesize = LIBATA_MAX_PRD,
269 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
270 .emulated = ATA_SHT_EMULATED,
271 .use_clustering = ATA_SHT_USE_CLUSTERING,
272 .proc_name = DRV_NAME,
273 .dma_boundary = ATA_DMA_BOUNDARY,
274 .slave_configure = ata_scsi_slave_config,
275 .slave_destroy = ata_scsi_slave_destroy,
276 .bios_param = ata_std_bios_param,
277 };
278
279 static const struct ata_port_operations piix_pata_ops = {
280 .port_disable = ata_port_disable,
281 .set_piomode = piix_set_piomode,
282 .set_dmamode = piix_set_dmamode,
283 .mode_filter = ata_pci_default_filter,
284
285 .tf_load = ata_tf_load,
286 .tf_read = ata_tf_read,
287 .check_status = ata_check_status,
288 .exec_command = ata_exec_command,
289 .dev_select = ata_std_dev_select,
290
291 .bmdma_setup = ata_bmdma_setup,
292 .bmdma_start = ata_bmdma_start,
293 .bmdma_stop = ata_bmdma_stop,
294 .bmdma_status = ata_bmdma_status,
295 .qc_prep = ata_qc_prep,
296 .qc_issue = ata_qc_issue_prot,
297 .data_xfer = ata_data_xfer,
298
299 .freeze = ata_bmdma_freeze,
300 .thaw = ata_bmdma_thaw,
301 .error_handler = piix_pata_error_handler,
302 .post_internal_cmd = ata_bmdma_post_internal_cmd,
303 .cable_detect = ata_cable_40wire,
304
305 .irq_handler = ata_interrupt,
306 .irq_clear = ata_bmdma_irq_clear,
307 .irq_on = ata_irq_on,
308 .irq_ack = ata_irq_ack,
309
310 .port_start = ata_port_start,
311 };
312
313 static const struct ata_port_operations ich_pata_ops = {
314 .port_disable = ata_port_disable,
315 .set_piomode = piix_set_piomode,
316 .set_dmamode = ich_set_dmamode,
317 .mode_filter = ata_pci_default_filter,
318
319 .tf_load = ata_tf_load,
320 .tf_read = ata_tf_read,
321 .check_status = ata_check_status,
322 .exec_command = ata_exec_command,
323 .dev_select = ata_std_dev_select,
324
325 .bmdma_setup = ata_bmdma_setup,
326 .bmdma_start = ata_bmdma_start,
327 .bmdma_stop = ata_bmdma_stop,
328 .bmdma_status = ata_bmdma_status,
329 .qc_prep = ata_qc_prep,
330 .qc_issue = ata_qc_issue_prot,
331 .data_xfer = ata_data_xfer,
332
333 .freeze = ata_bmdma_freeze,
334 .thaw = ata_bmdma_thaw,
335 .error_handler = piix_pata_error_handler,
336 .post_internal_cmd = ata_bmdma_post_internal_cmd,
337 .cable_detect = ich_pata_cable_detect,
338
339 .irq_handler = ata_interrupt,
340 .irq_clear = ata_bmdma_irq_clear,
341 .irq_on = ata_irq_on,
342 .irq_ack = ata_irq_ack,
343
344 .port_start = ata_port_start,
345 };
346
347 static const struct ata_port_operations piix_sata_ops = {
348 .port_disable = ata_port_disable,
349
350 .tf_load = ata_tf_load,
351 .tf_read = ata_tf_read,
352 .check_status = ata_check_status,
353 .exec_command = ata_exec_command,
354 .dev_select = ata_std_dev_select,
355
356 .bmdma_setup = ata_bmdma_setup,
357 .bmdma_start = ata_bmdma_start,
358 .bmdma_stop = ata_bmdma_stop,
359 .bmdma_status = ata_bmdma_status,
360 .qc_prep = ata_qc_prep,
361 .qc_issue = ata_qc_issue_prot,
362 .data_xfer = ata_data_xfer,
363
364 .freeze = ata_bmdma_freeze,
365 .thaw = ata_bmdma_thaw,
366 .error_handler = ata_bmdma_error_handler,
367 .post_internal_cmd = ata_bmdma_post_internal_cmd,
368
369 .irq_handler = ata_interrupt,
370 .irq_clear = ata_bmdma_irq_clear,
371 .irq_on = ata_irq_on,
372 .irq_ack = ata_irq_ack,
373
374 .port_start = ata_port_start,
375 };
376
377 static const struct piix_map_db ich5_map_db = {
378 .mask = 0x7,
379 .port_enable = 0x3,
380 .map = {
381 /* PM PS SM SS MAP */
382 { P0, NA, P1, NA }, /* 000b */
383 { P1, NA, P0, NA }, /* 001b */
384 { RV, RV, RV, RV },
385 { RV, RV, RV, RV },
386 { P0, P1, IDE, IDE }, /* 100b */
387 { P1, P0, IDE, IDE }, /* 101b */
388 { IDE, IDE, P0, P1 }, /* 110b */
389 { IDE, IDE, P1, P0 }, /* 111b */
390 },
391 };
392
393 static const struct piix_map_db ich6_map_db = {
394 .mask = 0x3,
395 .port_enable = 0xf,
396 .map = {
397 /* PM PS SM SS MAP */
398 { P0, P2, P1, P3 }, /* 00b */
399 { IDE, IDE, P1, P3 }, /* 01b */
400 { P0, P2, IDE, IDE }, /* 10b */
401 { RV, RV, RV, RV },
402 },
403 };
404
405 static const struct piix_map_db ich6m_map_db = {
406 .mask = 0x3,
407 .port_enable = 0x5,
408
409 /* Map 01b isn't specified in the doc but some notebooks use
410 * it anyway. MAP 01b have been spotted on both ICH6M and
411 * ICH7M.
412 */
413 .map = {
414 /* PM PS SM SS MAP */
415 { P0, P2, RV, RV }, /* 00b */
416 { IDE, IDE, P1, P3 }, /* 01b */
417 { P0, P2, IDE, IDE }, /* 10b */
418 { RV, RV, RV, RV },
419 },
420 };
421
422 static const struct piix_map_db ich8_map_db = {
423 .mask = 0x3,
424 .port_enable = 0x3,
425 .map = {
426 /* PM PS SM SS MAP */
427 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
428 { RV, RV, RV, RV },
429 { IDE, IDE, NA, NA }, /* 10b (IDE mode) */
430 { RV, RV, RV, RV },
431 },
432 };
433
434 static const struct piix_map_db *piix_map_db_table[] = {
435 [ich5_sata] = &ich5_map_db,
436 [ich6_sata] = &ich6_map_db,
437 [ich6_sata_ahci] = &ich6_map_db,
438 [ich6m_sata_ahci] = &ich6m_map_db,
439 [ich8_sata_ahci] = &ich8_map_db,
440 };
441
442 static struct ata_port_info piix_port_info[] = {
443 /* piix_pata_33: 0: PIIX4 at 33MHz */
444 {
445 .sht = &piix_sht,
446 .flags = PIIX_PATA_FLAGS,
447 .pio_mask = 0x1f, /* pio0-4 */
448 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
449 .udma_mask = ATA_UDMA_MASK_40C,
450 .port_ops = &piix_pata_ops,
451 },
452
453 /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/
454 {
455 .sht = &piix_sht,
456 .flags = PIIX_PATA_FLAGS,
457 .pio_mask = 0x1f, /* pio 0-4 */
458 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
459 .udma_mask = ATA_UDMA2, /* UDMA33 */
460 .port_ops = &ich_pata_ops,
461 },
462 /* ich_pata_66: 2 ICH controllers up to 66MHz */
463 {
464 .sht = &piix_sht,
465 .flags = PIIX_PATA_FLAGS,
466 .pio_mask = 0x1f, /* pio 0-4 */
467 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
468 .udma_mask = ATA_UDMA4,
469 .port_ops = &ich_pata_ops,
470 },
471
472 /* ich_pata_100: 3 */
473 {
474 .sht = &piix_sht,
475 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
476 .pio_mask = 0x1f, /* pio0-4 */
477 .mwdma_mask = 0x06, /* mwdma1-2 */
478 .udma_mask = ATA_UDMA5, /* udma0-5 */
479 .port_ops = &ich_pata_ops,
480 },
481
482 /* ich_pata_133: 4 ICH with full UDMA6 */
483 {
484 .sht = &piix_sht,
485 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
486 .pio_mask = 0x1f, /* pio 0-4 */
487 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
488 .udma_mask = ATA_UDMA6, /* UDMA133 */
489 .port_ops = &ich_pata_ops,
490 },
491
492 /* ich5_sata: 5 */
493 {
494 .sht = &piix_sht,
495 .flags = PIIX_SATA_FLAGS,
496 .pio_mask = 0x1f, /* pio0-4 */
497 .mwdma_mask = 0x07, /* mwdma0-2 */
498 .udma_mask = 0x7f, /* udma0-6 */
499 .port_ops = &piix_sata_ops,
500 },
501
502 /* ich6_sata: 6 */
503 {
504 .sht = &piix_sht,
505 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
506 .pio_mask = 0x1f, /* pio0-4 */
507 .mwdma_mask = 0x07, /* mwdma0-2 */
508 .udma_mask = 0x7f, /* udma0-6 */
509 .port_ops = &piix_sata_ops,
510 },
511
512 /* ich6_sata_ahci: 7 */
513 {
514 .sht = &piix_sht,
515 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
516 PIIX_FLAG_AHCI,
517 .pio_mask = 0x1f, /* pio0-4 */
518 .mwdma_mask = 0x07, /* mwdma0-2 */
519 .udma_mask = 0x7f, /* udma0-6 */
520 .port_ops = &piix_sata_ops,
521 },
522
523 /* ich6m_sata_ahci: 8 */
524 {
525 .sht = &piix_sht,
526 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
527 PIIX_FLAG_AHCI,
528 .pio_mask = 0x1f, /* pio0-4 */
529 .mwdma_mask = 0x07, /* mwdma0-2 */
530 .udma_mask = 0x7f, /* udma0-6 */
531 .port_ops = &piix_sata_ops,
532 },
533
534 /* ich8_sata_ahci: 9 */
535 {
536 .sht = &piix_sht,
537 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
538 PIIX_FLAG_AHCI,
539 .pio_mask = 0x1f, /* pio0-4 */
540 .mwdma_mask = 0x07, /* mwdma0-2 */
541 .udma_mask = 0x7f, /* udma0-6 */
542 .port_ops = &piix_sata_ops,
543 },
544
545 /* piix_pata_mwdma: 10: PIIX3 MWDMA only */
546 {
547 .sht = &piix_sht,
548 .flags = PIIX_PATA_FLAGS,
549 .pio_mask = 0x1f, /* pio0-4 */
550 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
551 .port_ops = &piix_pata_ops,
552 },
553 };
554
555 static struct pci_bits piix_enable_bits[] = {
556 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
557 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
558 };
559
560 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
561 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
562 MODULE_LICENSE("GPL");
563 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
564 MODULE_VERSION(DRV_VERSION);
565
566 struct ich_laptop {
567 u16 device;
568 u16 subvendor;
569 u16 subdevice;
570 };
571
572 /*
573 * List of laptops that use short cables rather than 80 wire
574 */
575
576 static const struct ich_laptop ich_laptop[] = {
577 /* devid, subvendor, subdev */
578 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
579 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
580 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
581 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
582 /* end marker */
583 { 0, }
584 };
585
586 /**
587 * ich_pata_cable_detect - Probe host controller cable detect info
588 * @ap: Port for which cable detect info is desired
589 *
590 * Read 80c cable indicator from ATA PCI device's PCI config
591 * register. This register is normally set by firmware (BIOS).
592 *
593 * LOCKING:
594 * None (inherited from caller).
595 */
596
597 static int ich_pata_cable_detect(struct ata_port *ap)
598 {
599 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
600 const struct ich_laptop *lap = &ich_laptop[0];
601 u8 tmp, mask;
602
603 /* Check for specials - Acer Aspire 5602WLMi */
604 while (lap->device) {
605 if (lap->device == pdev->device &&
606 lap->subvendor == pdev->subsystem_vendor &&
607 lap->subdevice == pdev->subsystem_device) {
608 return ATA_CBL_PATA40_SHORT;
609 }
610 lap++;
611 }
612
613 /* check BIOS cable detect results */
614 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
615 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
616 if ((tmp & mask) == 0)
617 return ATA_CBL_PATA40;
618 return ATA_CBL_PATA80;
619 }
620
621 /**
622 * piix_pata_prereset - prereset for PATA host controller
623 * @ap: Target port
624 * @deadline: deadline jiffies for the operation
625 *
626 * LOCKING:
627 * None (inherited from caller).
628 */
629 static int piix_pata_prereset(struct ata_port *ap, unsigned long deadline)
630 {
631 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
632
633 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
634 return -ENOENT;
635 return ata_std_prereset(ap, deadline);
636 }
637
638 static void piix_pata_error_handler(struct ata_port *ap)
639 {
640 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
641 ata_std_postreset);
642 }
643
644 /**
645 * piix_set_piomode - Initialize host controller PATA PIO timings
646 * @ap: Port whose timings we are configuring
647 * @adev: um
648 *
649 * Set PIO mode for device, in host controller PCI config space.
650 *
651 * LOCKING:
652 * None (inherited from caller).
653 */
654
655 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
656 {
657 unsigned int pio = adev->pio_mode - XFER_PIO_0;
658 struct pci_dev *dev = to_pci_dev(ap->host->dev);
659 unsigned int is_slave = (adev->devno != 0);
660 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
661 unsigned int slave_port = 0x44;
662 u16 master_data;
663 u8 slave_data;
664 u8 udma_enable;
665 int control = 0;
666
667 /*
668 * See Intel Document 298600-004 for the timing programing rules
669 * for ICH controllers.
670 */
671
672 static const /* ISP RTC */
673 u8 timings[][2] = { { 0, 0 },
674 { 0, 0 },
675 { 1, 0 },
676 { 2, 1 },
677 { 2, 3 }, };
678
679 if (pio >= 2)
680 control |= 1; /* TIME1 enable */
681 if (ata_pio_need_iordy(adev))
682 control |= 2; /* IE enable */
683
684 /* Intel specifies that the PPE functionality is for disk only */
685 if (adev->class == ATA_DEV_ATA)
686 control |= 4; /* PPE enable */
687
688 pci_read_config_word(dev, master_port, &master_data);
689 if (is_slave) {
690 /* Enable SITRE (seperate slave timing register) */
691 master_data |= 0x4000;
692 /* enable PPE1, IE1 and TIME1 as needed */
693 master_data |= (control << 4);
694 pci_read_config_byte(dev, slave_port, &slave_data);
695 slave_data &= (ap->port_no ? 0x0f : 0xf0);
696 /* Load the timing nibble for this slave */
697 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
698 } else {
699 /* Master keeps the bits in a different format */
700 master_data &= 0xccf8;
701 /* Enable PPE, IE and TIME as appropriate */
702 master_data |= control;
703 master_data |=
704 (timings[pio][0] << 12) |
705 (timings[pio][1] << 8);
706 }
707 pci_write_config_word(dev, master_port, master_data);
708 if (is_slave)
709 pci_write_config_byte(dev, slave_port, slave_data);
710
711 /* Ensure the UDMA bit is off - it will be turned back on if
712 UDMA is selected */
713
714 if (ap->udma_mask) {
715 pci_read_config_byte(dev, 0x48, &udma_enable);
716 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
717 pci_write_config_byte(dev, 0x48, udma_enable);
718 }
719 }
720
721 /**
722 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
723 * @ap: Port whose timings we are configuring
724 * @adev: Drive in question
725 * @udma: udma mode, 0 - 6
726 * @isich: set if the chip is an ICH device
727 *
728 * Set UDMA mode for device, in host controller PCI config space.
729 *
730 * LOCKING:
731 * None (inherited from caller).
732 */
733
734 static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich)
735 {
736 struct pci_dev *dev = to_pci_dev(ap->host->dev);
737 u8 master_port = ap->port_no ? 0x42 : 0x40;
738 u16 master_data;
739 u8 speed = adev->dma_mode;
740 int devid = adev->devno + 2 * ap->port_no;
741 u8 udma_enable = 0;
742
743 static const /* ISP RTC */
744 u8 timings[][2] = { { 0, 0 },
745 { 0, 0 },
746 { 1, 0 },
747 { 2, 1 },
748 { 2, 3 }, };
749
750 pci_read_config_word(dev, master_port, &master_data);
751 if (ap->udma_mask)
752 pci_read_config_byte(dev, 0x48, &udma_enable);
753
754 if (speed >= XFER_UDMA_0) {
755 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
756 u16 udma_timing;
757 u16 ideconf;
758 int u_clock, u_speed;
759
760 /*
761 * UDMA is handled by a combination of clock switching and
762 * selection of dividers
763 *
764 * Handy rule: Odd modes are UDMATIMx 01, even are 02
765 * except UDMA0 which is 00
766 */
767 u_speed = min(2 - (udma & 1), udma);
768 if (udma == 5)
769 u_clock = 0x1000; /* 100Mhz */
770 else if (udma > 2)
771 u_clock = 1; /* 66Mhz */
772 else
773 u_clock = 0; /* 33Mhz */
774
775 udma_enable |= (1 << devid);
776
777 /* Load the CT/RP selection */
778 pci_read_config_word(dev, 0x4A, &udma_timing);
779 udma_timing &= ~(3 << (4 * devid));
780 udma_timing |= u_speed << (4 * devid);
781 pci_write_config_word(dev, 0x4A, udma_timing);
782
783 if (isich) {
784 /* Select a 33/66/100Mhz clock */
785 pci_read_config_word(dev, 0x54, &ideconf);
786 ideconf &= ~(0x1001 << devid);
787 ideconf |= u_clock << devid;
788 /* For ICH or later we should set bit 10 for better
789 performance (WR_PingPong_En) */
790 pci_write_config_word(dev, 0x54, ideconf);
791 }
792 } else {
793 /*
794 * MWDMA is driven by the PIO timings. We must also enable
795 * IORDY unconditionally along with TIME1. PPE has already
796 * been set when the PIO timing was set.
797 */
798 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
799 unsigned int control;
800 u8 slave_data;
801 const unsigned int needed_pio[3] = {
802 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
803 };
804 int pio = needed_pio[mwdma] - XFER_PIO_0;
805
806 control = 3; /* IORDY|TIME1 */
807
808 /* If the drive MWDMA is faster than it can do PIO then
809 we must force PIO into PIO0 */
810
811 if (adev->pio_mode < needed_pio[mwdma])
812 /* Enable DMA timing only */
813 control |= 8; /* PIO cycles in PIO0 */
814
815 if (adev->devno) { /* Slave */
816 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
817 master_data |= control << 4;
818 pci_read_config_byte(dev, 0x44, &slave_data);
819 slave_data &= (0x0F + 0xE1 * ap->port_no);
820 /* Load the matching timing */
821 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
822 pci_write_config_byte(dev, 0x44, slave_data);
823 } else { /* Master */
824 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
825 and master timing bits */
826 master_data |= control;
827 master_data |=
828 (timings[pio][0] << 12) |
829 (timings[pio][1] << 8);
830 }
831 udma_enable &= ~(1 << devid);
832 pci_write_config_word(dev, master_port, master_data);
833 }
834 /* Don't scribble on 0x48 if the controller does not support UDMA */
835 if (ap->udma_mask)
836 pci_write_config_byte(dev, 0x48, udma_enable);
837 }
838
839 /**
840 * piix_set_dmamode - Initialize host controller PATA DMA timings
841 * @ap: Port whose timings we are configuring
842 * @adev: um
843 *
844 * Set MW/UDMA mode for device, in host controller PCI config space.
845 *
846 * LOCKING:
847 * None (inherited from caller).
848 */
849
850 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
851 {
852 do_pata_set_dmamode(ap, adev, 0);
853 }
854
855 /**
856 * ich_set_dmamode - Initialize host controller PATA DMA timings
857 * @ap: Port whose timings we are configuring
858 * @adev: um
859 *
860 * Set MW/UDMA mode for device, in host controller PCI config space.
861 *
862 * LOCKING:
863 * None (inherited from caller).
864 */
865
866 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev)
867 {
868 do_pata_set_dmamode(ap, adev, 1);
869 }
870
871 #define AHCI_PCI_BAR 5
872 #define AHCI_GLOBAL_CTL 0x04
873 #define AHCI_ENABLE (1 << 31)
874 static int piix_disable_ahci(struct pci_dev *pdev)
875 {
876 void __iomem *mmio;
877 u32 tmp;
878 int rc = 0;
879
880 /* BUG: pci_enable_device has not yet been called. This
881 * works because this device is usually set up by BIOS.
882 */
883
884 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
885 !pci_resource_len(pdev, AHCI_PCI_BAR))
886 return 0;
887
888 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
889 if (!mmio)
890 return -ENOMEM;
891
892 tmp = readl(mmio + AHCI_GLOBAL_CTL);
893 if (tmp & AHCI_ENABLE) {
894 tmp &= ~AHCI_ENABLE;
895 writel(tmp, mmio + AHCI_GLOBAL_CTL);
896
897 tmp = readl(mmio + AHCI_GLOBAL_CTL);
898 if (tmp & AHCI_ENABLE)
899 rc = -EIO;
900 }
901
902 pci_iounmap(pdev, mmio);
903 return rc;
904 }
905
906 /**
907 * piix_check_450nx_errata - Check for problem 450NX setup
908 * @ata_dev: the PCI device to check
909 *
910 * Check for the present of 450NX errata #19 and errata #25. If
911 * they are found return an error code so we can turn off DMA
912 */
913
914 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
915 {
916 struct pci_dev *pdev = NULL;
917 u16 cfg;
918 u8 rev;
919 int no_piix_dma = 0;
920
921 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
922 {
923 /* Look for 450NX PXB. Check for problem configurations
924 A PCI quirk checks bit 6 already */
925 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
926 pci_read_config_word(pdev, 0x41, &cfg);
927 /* Only on the original revision: IDE DMA can hang */
928 if (rev == 0x00)
929 no_piix_dma = 1;
930 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
931 else if (cfg & (1<<14) && rev < 5)
932 no_piix_dma = 2;
933 }
934 if (no_piix_dma)
935 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
936 if (no_piix_dma == 2)
937 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
938 return no_piix_dma;
939 }
940
941 static void __devinit piix_init_pcs(struct pci_dev *pdev,
942 struct ata_port_info *pinfo,
943 const struct piix_map_db *map_db)
944 {
945 u16 pcs, new_pcs;
946
947 pci_read_config_word(pdev, ICH5_PCS, &pcs);
948
949 new_pcs = pcs | map_db->port_enable;
950
951 if (new_pcs != pcs) {
952 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
953 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
954 msleep(150);
955 }
956 }
957
958 static void __devinit piix_init_sata_map(struct pci_dev *pdev,
959 struct ata_port_info *pinfo,
960 const struct piix_map_db *map_db)
961 {
962 struct piix_host_priv *hpriv = pinfo[0].private_data;
963 const unsigned int *map;
964 int i, invalid_map = 0;
965 u8 map_value;
966
967 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
968
969 map = map_db->map[map_value & map_db->mask];
970
971 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
972 for (i = 0; i < 4; i++) {
973 switch (map[i]) {
974 case RV:
975 invalid_map = 1;
976 printk(" XX");
977 break;
978
979 case NA:
980 printk(" --");
981 break;
982
983 case IDE:
984 WARN_ON((i & 1) || map[i + 1] != IDE);
985 pinfo[i / 2] = piix_port_info[ich_pata_100];
986 pinfo[i / 2].private_data = hpriv;
987 i++;
988 printk(" IDE IDE");
989 break;
990
991 default:
992 printk(" P%d", map[i]);
993 if (i & 1)
994 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
995 break;
996 }
997 }
998 printk(" ]\n");
999
1000 if (invalid_map)
1001 dev_printk(KERN_ERR, &pdev->dev,
1002 "invalid MAP value %u\n", map_value);
1003
1004 hpriv->map = map;
1005 }
1006
1007 /**
1008 * piix_init_one - Register PIIX ATA PCI device with kernel services
1009 * @pdev: PCI device to register
1010 * @ent: Entry in piix_pci_tbl matching with @pdev
1011 *
1012 * Called from kernel PCI layer. We probe for combined mode (sigh),
1013 * and then hand over control to libata, for it to do the rest.
1014 *
1015 * LOCKING:
1016 * Inherited from PCI layer (may sleep).
1017 *
1018 * RETURNS:
1019 * Zero on success, or -ERRNO value.
1020 */
1021
1022 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1023 {
1024 static int printed_version;
1025 struct device *dev = &pdev->dev;
1026 struct ata_port_info port_info[2];
1027 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1028 struct piix_host_priv *hpriv;
1029 unsigned long port_flags;
1030
1031 if (!printed_version++)
1032 dev_printk(KERN_DEBUG, &pdev->dev,
1033 "version " DRV_VERSION "\n");
1034
1035 /* no hotplugging support (FIXME) */
1036 if (!in_module_init)
1037 return -ENODEV;
1038
1039 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1040 if (!hpriv)
1041 return -ENOMEM;
1042
1043 port_info[0] = piix_port_info[ent->driver_data];
1044 port_info[1] = piix_port_info[ent->driver_data];
1045 port_info[0].private_data = hpriv;
1046 port_info[1].private_data = hpriv;
1047
1048 port_flags = port_info[0].flags;
1049
1050 if (port_flags & PIIX_FLAG_AHCI) {
1051 u8 tmp;
1052 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1053 if (tmp == PIIX_AHCI_DEVICE) {
1054 int rc = piix_disable_ahci(pdev);
1055 if (rc)
1056 return rc;
1057 }
1058 }
1059
1060 /* Initialize SATA map */
1061 if (port_flags & ATA_FLAG_SATA) {
1062 piix_init_sata_map(pdev, port_info,
1063 piix_map_db_table[ent->driver_data]);
1064 piix_init_pcs(pdev, port_info,
1065 piix_map_db_table[ent->driver_data]);
1066 }
1067
1068 /* On ICH5, some BIOSen disable the interrupt using the
1069 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1070 * On ICH6, this bit has the same effect, but only when
1071 * MSI is disabled (and it is disabled, as we don't use
1072 * message-signalled interrupts currently).
1073 */
1074 if (port_flags & PIIX_FLAG_CHECKINTR)
1075 pci_intx(pdev, 1);
1076
1077 if (piix_check_450nx_errata(pdev)) {
1078 /* This writes into the master table but it does not
1079 really matter for this errata as we will apply it to
1080 all the PIIX devices on the board */
1081 port_info[0].mwdma_mask = 0;
1082 port_info[0].udma_mask = 0;
1083 port_info[1].mwdma_mask = 0;
1084 port_info[1].udma_mask = 0;
1085 }
1086 return ata_pci_init_one(pdev, ppi);
1087 }
1088
1089 static int __init piix_init(void)
1090 {
1091 int rc;
1092
1093 DPRINTK("pci_register_driver\n");
1094 rc = pci_register_driver(&piix_pci_driver);
1095 if (rc)
1096 return rc;
1097
1098 in_module_init = 0;
1099
1100 DPRINTK("done\n");
1101 return 0;
1102 }
1103
1104 static void __exit piix_exit(void)
1105 {
1106 pci_unregister_driver(&piix_pci_driver);
1107 }
1108
1109 module_init(piix_init);
1110 module_exit(piix_exit);
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