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Linux 2.6.22-rc3
[linux-2.6/next.git] / drivers / ata / pata_serverworks.c
blob1e8f421963c7259dada806d741e9a0d42d2626d8
1 /*
2 * pata_serverworks.c - Serverworks PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * based upon
7 *
8 * serverworks.c
9 *
10 * Copyright (C) 1998-2000 Michel Aubry
11 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
12 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
13 * Portions copyright (c) 2001 Sun Microsystems
14 *
15 *
16 * RCC/ServerWorks IDE driver for Linux
17 *
18 * OSB4: `Open South Bridge' IDE Interface (fn 1)
19 * supports UDMA mode 2 (33 MB/s)
20 *
21 * CSB5: `Champion South Bridge' IDE Interface (fn 1)
22 * all revisions support UDMA mode 4 (66 MB/s)
23 * revision A2.0 and up support UDMA mode 5 (100 MB/s)
24 *
25 * *** The CSB5 does not provide ANY register ***
26 * *** to detect 80-conductor cable presence. ***
27 *
28 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
29 *
30 * Documentation:
31 * Available under NDA only. Errata info very hard to get.
32 */
33
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <scsi/scsi_host.h>
41 #include <linux/libata.h>
42
43 #define DRV_NAME "pata_serverworks"
44 #define DRV_VERSION "0.4.1"
45
46 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
47 #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
48
49 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
50 * can overrun their FIFOs when used with the CSB5 */
51
52 static const char *csb_bad_ata100[] = {
53 "ST320011A",
54 "ST340016A",
55 "ST360021A",
56 "ST380021A",
57 NULL
58 };
59
60 /**
61 * dell_cable - Dell serverworks cable detection
62 * @ap: ATA port to do cable detect
63 *
64 * Dell hide the 40/80 pin select for their interfaces in the top two
65 * bits of the subsystem ID.
66 */
67
68 static int dell_cable(struct ata_port *ap) {
69 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
70
71 if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
72 return ATA_CBL_PATA80;
73 return ATA_CBL_PATA40;
74 }
75
76 /**
77 * sun_cable - Sun Cobalt 'Alpine' cable detection
78 * @ap: ATA port to do cable select
79 *
80 * Cobalt CSB5 IDE hides the 40/80pin in the top two bits of the
81 * subsystem ID the same as dell. We could use one function but we may
82 * need to extend the Dell one in future
83 */
84
85 static int sun_cable(struct ata_port *ap) {
86 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
87
88 if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
89 return ATA_CBL_PATA80;
90 return ATA_CBL_PATA40;
91 }
92
93 /**
94 * osb4_cable - OSB4 cable detect
95 * @ap: ATA port to check
96 *
97 * The OSB4 isn't UDMA66 capable so this is easy
98 */
99
100 static int osb4_cable(struct ata_port *ap) {
101 return ATA_CBL_PATA40;
102 }
103
104 /**
105 * csb4_cable - CSB5/6 cable detect
106 * @ap: ATA port to check
107 *
108 * Serverworks default arrangement is to use the drive side detection
109 * only.
110 */
111
112 static int csb_cable(struct ata_port *ap) {
113 return ATA_CBL_PATA80;
114 }
115
116 struct sv_cable_table {
117 int device;
118 int subvendor;
119 int (*cable_detect)(struct ata_port *ap);
120 };
121
122 /*
123 * Note that we don't copy the old serverworks code because the old
124 * code contains obvious mistakes
125 */
126
127 static struct sv_cable_table cable_detect[] = {
128 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_DELL, dell_cable },
129 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_VENDOR_ID_DELL, dell_cable },
130 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_SUN, sun_cable },
131 { PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, osb4_cable },
132 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, csb_cable },
133 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, csb_cable },
134 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, csb_cable },
135 { PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, csb_cable },
136 { }
137 };
138
139 /**
140 * serverworks_cable_detect - cable detection
141 * @ap: ATA port
142 * @deadline: deadline jiffies for the operation
143 *
144 * Perform cable detection according to the device and subvendor
145 * identifications
146 */
147
148 static int serverworks_cable_detect(struct ata_port *ap)
149 {
150 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
151 struct sv_cable_table *cb = cable_detect;
152
153 while(cb->device) {
154 if (cb->device == pdev->device &&
155 (cb->subvendor == pdev->subsystem_vendor ||
156 cb->subvendor == PCI_ANY_ID)) {
157 return cb->cable_detect(ap);
158 }
159 cb++;
160 }
161
162 BUG();
163 return -1; /* kill compiler warning */
164 }
165
166 /**
167 * serverworks_is_csb - Check for CSB or OSB
168 * @pdev: PCI device to check
169 *
170 * Returns true if the device being checked is known to be a CSB
171 * series device.
172 */
173
174 static u8 serverworks_is_csb(struct pci_dev *pdev)
175 {
176 switch (pdev->device) {
177 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
178 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
179 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
180 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
181 return 1;
182 default:
183 break;
184 }
185 return 0;
186 }
187
188 /**
189 * serverworks_osb4_filter - mode selection filter
190 * @adev: ATA device
191 * @mask: Mask of proposed modes
192 *
193 * Filter the offered modes for the device to apply controller
194 * specific rules. OSB4 requires no UDMA for disks due to a FIFO
195 * bug we hit.
196 */
197
198 static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned long mask)
199 {
200 if (adev->class == ATA_DEV_ATA)
201 mask &= ~ATA_MASK_UDMA;
202 return ata_pci_default_filter(adev, mask);
203 }
204
205
206 /**
207 * serverworks_csb_filter - mode selection filter
208 * @adev: ATA device
209 * @mask: Mask of proposed modes
210 *
211 * Check the blacklist and disable UDMA5 if matched
212 */
213
214 static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned long mask)
215 {
216 const char *p;
217 char model_num[ATA_ID_PROD_LEN + 1];
218 int i;
219
220 /* Disk, UDMA */
221 if (adev->class != ATA_DEV_ATA)
222 return ata_pci_default_filter(adev, mask);
223
224 /* Actually do need to check */
225 ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));
226
227 for (i = 0; (p = csb_bad_ata100[i]) != NULL; i++) {
228 if (!strcmp(p, model_num))
229 mask &= ~(0x1F << ATA_SHIFT_UDMA);
230 }
231 return ata_pci_default_filter(adev, mask);
232 }
233
234
235 /**
236 * serverworks_set_piomode - set initial PIO mode data
237 * @ap: ATA interface
238 * @adev: ATA device
239 *
240 * Program the OSB4/CSB5 timing registers for PIO. The PIO register
241 * load is done as a simple lookup.
242 */
243 static void serverworks_set_piomode(struct ata_port *ap, struct ata_device *adev)
244 {
245 static const u8 pio_mode[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
246 int offset = 1 + (2 * ap->port_no) - adev->devno;
247 int devbits = (2 * ap->port_no + adev->devno) * 4;
248 u16 csb5_pio;
249 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
250 int pio = adev->pio_mode - XFER_PIO_0;
251
252 pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]);
253
254 /* The OSB4 just requires the timing but the CSB series want the
255 mode number as well */
256 if (serverworks_is_csb(pdev)) {
257 pci_read_config_word(pdev, 0x4A, &csb5_pio);
258 csb5_pio &= ~(0x0F << devbits);
259 pci_write_config_byte(pdev, 0x4A, csb5_pio | (pio << devbits));
260 }
261 }
262
263 /**
264 * serverworks_set_dmamode - set initial DMA mode data
265 * @ap: ATA interface
266 * @adev: ATA device
267 *
268 * Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5
269 * chipset. The MWDMA mode values are pulled from a lookup table
270 * while the chipset uses mode number for UDMA.
271 */
272
273 static void serverworks_set_dmamode(struct ata_port *ap, struct ata_device *adev)
274 {
275 static const u8 dma_mode[] = { 0x77, 0x21, 0x20 };
276 int offset = 1 + 2 * ap->port_no - adev->devno;
277 int devbits = (2 * ap->port_no + adev->devno);
278 u8 ultra;
279 u8 ultra_cfg;
280 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
281
282 pci_read_config_byte(pdev, 0x54, &ultra_cfg);
283
284 if (adev->dma_mode >= XFER_UDMA_0) {
285 pci_write_config_byte(pdev, 0x44 + offset, 0x20);
286
287 pci_read_config_byte(pdev, 0x56 + ap->port_no, &ultra);
288 ultra &= ~(0x0F << (ap->port_no * 4));
289 ultra |= (adev->dma_mode - XFER_UDMA_0)
290 << (ap->port_no * 4);
291 pci_write_config_byte(pdev, 0x56 + ap->port_no, ultra);
292
293 ultra_cfg |= (1 << devbits);
294 } else {
295 pci_write_config_byte(pdev, 0x44 + offset,
296 dma_mode[adev->dma_mode - XFER_MW_DMA_0]);
297 ultra_cfg &= ~(1 << devbits);
298 }
299 pci_write_config_byte(pdev, 0x54, ultra_cfg);
300 }
301
302 static struct scsi_host_template serverworks_sht = {
303 .module = THIS_MODULE,
304 .name = DRV_NAME,
305 .ioctl = ata_scsi_ioctl,
306 .queuecommand = ata_scsi_queuecmd,
307 .can_queue = ATA_DEF_QUEUE,
308 .this_id = ATA_SHT_THIS_ID,
309 .sg_tablesize = LIBATA_MAX_PRD,
310 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
311 .emulated = ATA_SHT_EMULATED,
312 .use_clustering = ATA_SHT_USE_CLUSTERING,
313 .proc_name = DRV_NAME,
314 .dma_boundary = ATA_DMA_BOUNDARY,
315 .slave_configure = ata_scsi_slave_config,
316 .slave_destroy = ata_scsi_slave_destroy,
317 .bios_param = ata_std_bios_param,
318 };
319
320 static struct ata_port_operations serverworks_osb4_port_ops = {
321 .port_disable = ata_port_disable,
322 .set_piomode = serverworks_set_piomode,
323 .set_dmamode = serverworks_set_dmamode,
324 .mode_filter = serverworks_osb4_filter,
325
326 .tf_load = ata_tf_load,
327 .tf_read = ata_tf_read,
328 .check_status = ata_check_status,
329 .exec_command = ata_exec_command,
330 .dev_select = ata_std_dev_select,
331
332 .freeze = ata_bmdma_freeze,
333 .thaw = ata_bmdma_thaw,
334 .error_handler = ata_bmdma_error_handler,
335 .post_internal_cmd = ata_bmdma_post_internal_cmd,
336 .cable_detect = serverworks_cable_detect,
337
338 .bmdma_setup = ata_bmdma_setup,
339 .bmdma_start = ata_bmdma_start,
340 .bmdma_stop = ata_bmdma_stop,
341 .bmdma_status = ata_bmdma_status,
342
343 .qc_prep = ata_qc_prep,
344 .qc_issue = ata_qc_issue_prot,
345
346 .data_xfer = ata_data_xfer,
347
348 .irq_handler = ata_interrupt,
349 .irq_clear = ata_bmdma_irq_clear,
350 .irq_on = ata_irq_on,
351 .irq_ack = ata_irq_ack,
352
353 .port_start = ata_port_start,
354 };
355
356 static struct ata_port_operations serverworks_csb_port_ops = {
357 .port_disable = ata_port_disable,
358 .set_piomode = serverworks_set_piomode,
359 .set_dmamode = serverworks_set_dmamode,
360 .mode_filter = serverworks_csb_filter,
361
362 .tf_load = ata_tf_load,
363 .tf_read = ata_tf_read,
364 .check_status = ata_check_status,
365 .exec_command = ata_exec_command,
366 .dev_select = ata_std_dev_select,
367
368 .freeze = ata_bmdma_freeze,
369 .thaw = ata_bmdma_thaw,
370 .error_handler = ata_bmdma_error_handler,
371 .post_internal_cmd = ata_bmdma_post_internal_cmd,
372 .cable_detect = serverworks_cable_detect,
373
374 .bmdma_setup = ata_bmdma_setup,
375 .bmdma_start = ata_bmdma_start,
376 .bmdma_stop = ata_bmdma_stop,
377 .bmdma_status = ata_bmdma_status,
378
379 .qc_prep = ata_qc_prep,
380 .qc_issue = ata_qc_issue_prot,
381
382 .data_xfer = ata_data_xfer,
383
384 .irq_handler = ata_interrupt,
385 .irq_clear = ata_bmdma_irq_clear,
386 .irq_on = ata_irq_on,
387 .irq_ack = ata_irq_ack,
388
389 .port_start = ata_port_start,
390 };
391
392 static int serverworks_fixup_osb4(struct pci_dev *pdev)
393 {
394 u32 reg;
395 struct pci_dev *isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
396 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
397 if (isa_dev) {
398 pci_read_config_dword(isa_dev, 0x64, &reg);
399 reg &= ~0x00002000; /* disable 600ns interrupt mask */
400 if (!(reg & 0x00004000))
401 printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n");
402 reg |= 0x00004000; /* enable UDMA/33 support */
403 pci_write_config_dword(isa_dev, 0x64, reg);
404 pci_dev_put(isa_dev);
405 return 0;
406 }
407 printk(KERN_WARNING "ata_serverworks: Unable to find bridge.\n");
408 return -ENODEV;
409 }
410
411 static int serverworks_fixup_csb(struct pci_dev *pdev)
412 {
413 u8 rev;
414 u8 btr;
415
416 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
417
418 /* Third Channel Test */
419 if (!(PCI_FUNC(pdev->devfn) & 1)) {
420 struct pci_dev * findev = NULL;
421 u32 reg4c = 0;
422 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
423 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
424 if (findev) {
425 pci_read_config_dword(findev, 0x4C, &reg4c);
426 reg4c &= ~0x000007FF;
427 reg4c |= 0x00000040;
428 reg4c |= 0x00000020;
429 pci_write_config_dword(findev, 0x4C, reg4c);
430 pci_dev_put(findev);
431 }
432 } else {
433 struct pci_dev * findev = NULL;
434 u8 reg41 = 0;
435
436 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
437 PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
438 if (findev) {
439 pci_read_config_byte(findev, 0x41, &reg41);
440 reg41 &= ~0x40;
441 pci_write_config_byte(findev, 0x41, reg41);
442 pci_dev_put(findev);
443 }
444 }
445 /* setup the UDMA Control register
446 *
447 * 1. clear bit 6 to enable DMA
448 * 2. enable DMA modes with bits 0-1
449 * 00 : legacy
450 * 01 : udma2
451 * 10 : udma2/udma4
452 * 11 : udma2/udma4/udma5
453 */
454 pci_read_config_byte(pdev, 0x5A, &btr);
455 btr &= ~0x40;
456 if (!(PCI_FUNC(pdev->devfn) & 1))
457 btr |= 0x2;
458 else
459 btr |= (rev >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
460 pci_write_config_byte(pdev, 0x5A, btr);
461
462 return btr;
463 }
464
465 static void serverworks_fixup_ht1000(struct pci_dev *pdev)
466 {
467 u8 btr;
468 /* Setup HT1000 SouthBridge Controller - Single Channel Only */
469 pci_read_config_byte(pdev, 0x5A, &btr);
470 btr &= ~0x40;
471 btr |= 0x3;
472 pci_write_config_byte(pdev, 0x5A, btr);
473 }
474
475
476 static int serverworks_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
477 {
478 static const struct ata_port_info info[4] = {
479 { /* OSB4 */
480 .sht = &serverworks_sht,
481 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
482 .pio_mask = 0x1f,
483 .mwdma_mask = 0x07,
484 .udma_mask = 0x07,
485 .port_ops = &serverworks_osb4_port_ops
486 }, { /* OSB4 no UDMA */
487 .sht = &serverworks_sht,
488 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
489 .pio_mask = 0x1f,
490 .mwdma_mask = 0x07,
491 .udma_mask = 0x00,
492 .port_ops = &serverworks_osb4_port_ops
493 }, { /* CSB5 */
494 .sht = &serverworks_sht,
495 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
496 .pio_mask = 0x1f,
497 .mwdma_mask = 0x07,
498 .udma_mask = 0x1f,
499 .port_ops = &serverworks_csb_port_ops
500 }, { /* CSB5 - later revisions*/
501 .sht = &serverworks_sht,
502 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
503 .pio_mask = 0x1f,
504 .mwdma_mask = 0x07,
505 .udma_mask = 0x3f,
506 .port_ops = &serverworks_csb_port_ops
507 }
508 };
509 const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
510
511 /* Force master latency timer to 64 PCI clocks */
512 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
513
514 /* OSB4 : South Bridge and IDE */
515 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
516 /* Select non UDMA capable OSB4 if we can't do fixups */
517 if ( serverworks_fixup_osb4(pdev) < 0)
518 ppi[0] = &info[1];
519 }
520 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
521 else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
522 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
523 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
524
525 /* If the returned btr is the newer revision then
526 select the right info block */
527 if (serverworks_fixup_csb(pdev) == 3)
528 ppi[0] = &info[3];
529
530 /* Is this the 3rd channel CSB6 IDE ? */
531 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)
532 ppi[1] = &ata_dummy_port_info;
533 }
534 /* setup HT1000E */
535 else if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
536 serverworks_fixup_ht1000(pdev);
537
538 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
539 ata_pci_clear_simplex(pdev);
540
541 return ata_pci_init_one(pdev, ppi);
542 }
543
544 #ifdef CONFIG_PM
545 static int serverworks_reinit_one(struct pci_dev *pdev)
546 {
547 /* Force master latency timer to 64 PCI clocks */
548 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
549
550 switch (pdev->device)
551 {
552 case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE:
553 serverworks_fixup_osb4(pdev);
554 break;
555 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
556 ata_pci_clear_simplex(pdev);
557 /* fall through */
558 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
559 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
560 serverworks_fixup_csb(pdev);
561 break;
562 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
563 serverworks_fixup_ht1000(pdev);
564 break;
565 }
566 return ata_pci_device_resume(pdev);
567 }
568 #endif
569
570 static const struct pci_device_id serverworks[] = {
571 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0},
572 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 2},
573 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2},
574 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 2},
575 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 2},
576
577 { },
578 };
579
580 static struct pci_driver serverworks_pci_driver = {
581 .name = DRV_NAME,
582 .id_table = serverworks,
583 .probe = serverworks_init_one,
584 .remove = ata_pci_remove_one,
585 #ifdef CONFIG_PM
586 .suspend = ata_pci_device_suspend,
587 .resume = serverworks_reinit_one,
588 #endif
589 };
590
591 static int __init serverworks_init(void)
592 {
593 return pci_register_driver(&serverworks_pci_driver);
594 }
595
596 static void __exit serverworks_exit(void)
597 {
598 pci_unregister_driver(&serverworks_pci_driver);
599 }
600
601 MODULE_AUTHOR("Alan Cox");
602 MODULE_DESCRIPTION("low-level driver for Serverworks OSB4/CSB5/CSB6");
603 MODULE_LICENSE("GPL");
604 MODULE_DEVICE_TABLE(pci, serverworks);
605 MODULE_VERSION(DRV_VERSION);
606
607 module_init(serverworks_init);
608 module_exit(serverworks_exit);
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