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Linux 2.6.22-rc3
[linux-2.6/next.git] / drivers / char / drm / i915_dma.c
blob1ba15d9a171ab469ac3ec99c368575feeaf7d7d2
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "i915_drm.h"
32 #include "i915_drv.h"
33
34 #define IS_I965G(dev) (dev->pci_device == 0x2972 || \
35 dev->pci_device == 0x2982 || \
36 dev->pci_device == 0x2992 || \
37 dev->pci_device == 0x29A2 || \
38 dev->pci_device == 0x2A02)
39
40 /* Really want an OS-independent resettable timer. Would like to have
41 * this loop run for (eg) 3 sec, but have the timer reset every time
42 * the head pointer changes, so that EBUSY only happens if the ring
43 * actually stalls for (eg) 3 seconds.
44 */
45 int i915_wait_ring(drm_device_t * dev, int n, const char *caller)
46 {
47 drm_i915_private_t *dev_priv = dev->dev_private;
48 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
49 u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
50 int i;
51
52 for (i = 0; i < 10000; i++) {
53 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
54 ring->space = ring->head - (ring->tail + 8);
55 if (ring->space < 0)
56 ring->space += ring->Size;
57 if (ring->space >= n)
58 return 0;
59
60 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
61
62 if (ring->head != last_head)
63 i = 0;
64
65 last_head = ring->head;
66 }
67
68 return DRM_ERR(EBUSY);
69 }
70
71 void i915_kernel_lost_context(drm_device_t * dev)
72 {
73 drm_i915_private_t *dev_priv = dev->dev_private;
74 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
75
76 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
77 ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
78 ring->space = ring->head - (ring->tail + 8);
79 if (ring->space < 0)
80 ring->space += ring->Size;
81
82 if (ring->head == ring->tail)
83 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
84 }
85
86 static int i915_dma_cleanup(drm_device_t * dev)
87 {
88 /* Make sure interrupts are disabled here because the uninstall ioctl
89 * may not have been called from userspace and after dev_private
90 * is freed, it's too late.
91 */
92 if (dev->irq)
93 drm_irq_uninstall(dev);
94
95 if (dev->dev_private) {
96 drm_i915_private_t *dev_priv =
97 (drm_i915_private_t *) dev->dev_private;
98
99 if (dev_priv->ring.virtual_start) {
100 drm_core_ioremapfree(&dev_priv->ring.map, dev);
101 }
102
103 if (dev_priv->status_page_dmah) {
104 drm_pci_free(dev, dev_priv->status_page_dmah);
105 /* Need to rewrite hardware status page */
106 I915_WRITE(0x02080, 0x1ffff000);
107 }
108
109 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
110 DRM_MEM_DRIVER);
111
112 dev->dev_private = NULL;
113 }
114
115 return 0;
116 }
117
118 static int i915_initialize(drm_device_t * dev,
119 drm_i915_private_t * dev_priv,
120 drm_i915_init_t * init)
121 {
122 memset(dev_priv, 0, sizeof(drm_i915_private_t));
123
124 DRM_GETSAREA();
125 if (!dev_priv->sarea) {
126 DRM_ERROR("can not find sarea!\n");
127 dev->dev_private = (void *)dev_priv;
128 i915_dma_cleanup(dev);
129 return DRM_ERR(EINVAL);
130 }
131
132 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
133 if (!dev_priv->mmio_map) {
134 dev->dev_private = (void *)dev_priv;
135 i915_dma_cleanup(dev);
136 DRM_ERROR("can not find mmio map!\n");
137 return DRM_ERR(EINVAL);
138 }
139
140 dev_priv->sarea_priv = (drm_i915_sarea_t *)
141 ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
142
143 dev_priv->ring.Start = init->ring_start;
144 dev_priv->ring.End = init->ring_end;
145 dev_priv->ring.Size = init->ring_size;
146 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
147
148 dev_priv->ring.map.offset = init->ring_start;
149 dev_priv->ring.map.size = init->ring_size;
150 dev_priv->ring.map.type = 0;
151 dev_priv->ring.map.flags = 0;
152 dev_priv->ring.map.mtrr = 0;
153
154 drm_core_ioremap(&dev_priv->ring.map, dev);
155
156 if (dev_priv->ring.map.handle == NULL) {
157 dev->dev_private = (void *)dev_priv;
158 i915_dma_cleanup(dev);
159 DRM_ERROR("can not ioremap virtual address for"
160 " ring buffer\n");
161 return DRM_ERR(ENOMEM);
162 }
163
164 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
165
166 dev_priv->cpp = init->cpp;
167 dev_priv->back_offset = init->back_offset;
168 dev_priv->front_offset = init->front_offset;
169 dev_priv->current_page = 0;
170 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
171
172 /* We are using separate values as placeholders for mechanisms for
173 * private backbuffer/depthbuffer usage.
174 */
175 dev_priv->use_mi_batchbuffer_start = 0;
176
177 /* Allow hardware batchbuffers unless told otherwise.
178 */
179 dev_priv->allow_batchbuffer = 1;
180
181 /* Program Hardware Status Page */
182 dev_priv->status_page_dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE,
183 0xffffffff);
184
185 if (!dev_priv->status_page_dmah) {
186 dev->dev_private = (void *)dev_priv;
187 i915_dma_cleanup(dev);
188 DRM_ERROR("Can not allocate hardware status page\n");
189 return DRM_ERR(ENOMEM);
190 }
191 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
192 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
193
194 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
195 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
196
197 I915_WRITE(0x02080, dev_priv->dma_status_page);
198 DRM_DEBUG("Enabled hardware status page\n");
199
200 dev->dev_private = (void *)dev_priv;
201
202 return 0;
203 }
204
205 static int i915_dma_resume(drm_device_t * dev)
206 {
207 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
208
209 DRM_DEBUG("%s\n", __FUNCTION__);
210
211 if (!dev_priv->sarea) {
212 DRM_ERROR("can not find sarea!\n");
213 return DRM_ERR(EINVAL);
214 }
215
216 if (!dev_priv->mmio_map) {
217 DRM_ERROR("can not find mmio map!\n");
218 return DRM_ERR(EINVAL);
219 }
220
221 if (dev_priv->ring.map.handle == NULL) {
222 DRM_ERROR("can not ioremap virtual address for"
223 " ring buffer\n");
224 return DRM_ERR(ENOMEM);
225 }
226
227 /* Program Hardware Status Page */
228 if (!dev_priv->hw_status_page) {
229 DRM_ERROR("Can not find hardware status page\n");
230 return DRM_ERR(EINVAL);
231 }
232 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
233
234 I915_WRITE(0x02080, dev_priv->dma_status_page);
235 DRM_DEBUG("Enabled hardware status page\n");
236
237 return 0;
238 }
239
240 static int i915_dma_init(DRM_IOCTL_ARGS)
241 {
242 DRM_DEVICE;
243 drm_i915_private_t *dev_priv;
244 drm_i915_init_t init;
245 int retcode = 0;
246
247 DRM_COPY_FROM_USER_IOCTL(init, (drm_i915_init_t __user *) data,
248 sizeof(init));
249
250 switch (init.func) {
251 case I915_INIT_DMA:
252 dev_priv = drm_alloc(sizeof(drm_i915_private_t),
253 DRM_MEM_DRIVER);
254 if (dev_priv == NULL)
255 return DRM_ERR(ENOMEM);
256 retcode = i915_initialize(dev, dev_priv, &init);
257 break;
258 case I915_CLEANUP_DMA:
259 retcode = i915_dma_cleanup(dev);
260 break;
261 case I915_RESUME_DMA:
262 retcode = i915_dma_resume(dev);
263 break;
264 default:
265 retcode = DRM_ERR(EINVAL);
266 break;
267 }
268
269 return retcode;
270 }
271
272 /* Implement basically the same security restrictions as hardware does
273 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
274 *
275 * Most of the calculations below involve calculating the size of a
276 * particular instruction. It's important to get the size right as
277 * that tells us where the next instruction to check is. Any illegal
278 * instruction detected will be given a size of zero, which is a
279 * signal to abort the rest of the buffer.
280 */
281 static int do_validate_cmd(int cmd)
282 {
283 switch (((cmd >> 29) & 0x7)) {
284 case 0x0:
285 switch ((cmd >> 23) & 0x3f) {
286 case 0x0:
287 return 1; /* MI_NOOP */
288 case 0x4:
289 return 1; /* MI_FLUSH */
290 default:
291 return 0; /* disallow everything else */
292 }
293 break;
294 case 0x1:
295 return 0; /* reserved */
296 case 0x2:
297 return (cmd & 0xff) + 2; /* 2d commands */
298 case 0x3:
299 if (((cmd >> 24) & 0x1f) <= 0x18)
300 return 1;
301
302 switch ((cmd >> 24) & 0x1f) {
303 case 0x1c:
304 return 1;
305 case 0x1d:
306 switch ((cmd >> 16) & 0xff) {
307 case 0x3:
308 return (cmd & 0x1f) + 2;
309 case 0x4:
310 return (cmd & 0xf) + 2;
311 default:
312 return (cmd & 0xffff) + 2;
313 }
314 case 0x1e:
315 if (cmd & (1 << 23))
316 return (cmd & 0xffff) + 1;
317 else
318 return 1;
319 case 0x1f:
320 if ((cmd & (1 << 23)) == 0) /* inline vertices */
321 return (cmd & 0x1ffff) + 2;
322 else if (cmd & (1 << 17)) /* indirect random */
323 if ((cmd & 0xffff) == 0)
324 return 0; /* unknown length, too hard */
325 else
326 return (((cmd & 0xffff) + 1) / 2) + 1;
327 else
328 return 2; /* indirect sequential */
329 default:
330 return 0;
331 }
332 default:
333 return 0;
334 }
335
336 return 0;
337 }
338
339 static int validate_cmd(int cmd)
340 {
341 int ret = do_validate_cmd(cmd);
342
343 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
344
345 return ret;
346 }
347
348 static int i915_emit_cmds(drm_device_t * dev, int __user * buffer, int dwords)
349 {
350 drm_i915_private_t *dev_priv = dev->dev_private;
351 int i;
352 RING_LOCALS;
353
354 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
355 return DRM_ERR(EINVAL);
356
357 BEGIN_LP_RING((dwords+1)&~1);
358
359 for (i = 0; i < dwords;) {
360 int cmd, sz;
361
362 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
363 return DRM_ERR(EINVAL);
364
365 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
366 return DRM_ERR(EINVAL);
367
368 OUT_RING(cmd);
369
370 while (++i, --sz) {
371 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
372 sizeof(cmd))) {
373 return DRM_ERR(EINVAL);
374 }
375 OUT_RING(cmd);
376 }
377 }
378
379 if (dwords & 1)
380 OUT_RING(0);
381
382 ADVANCE_LP_RING();
383
384 return 0;
385 }
386
387 static int i915_emit_box(drm_device_t * dev,
388 drm_clip_rect_t __user * boxes,
389 int i, int DR1, int DR4)
390 {
391 drm_i915_private_t *dev_priv = dev->dev_private;
392 drm_clip_rect_t box;
393 RING_LOCALS;
394
395 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
396 return DRM_ERR(EFAULT);
397 }
398
399 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
400 DRM_ERROR("Bad box %d,%d..%d,%d\n",
401 box.x1, box.y1, box.x2, box.y2);
402 return DRM_ERR(EINVAL);
403 }
404
405 if (IS_I965G(dev)) {
406 BEGIN_LP_RING(4);
407 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
408 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
409 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
410 OUT_RING(DR4);
411 ADVANCE_LP_RING();
412 } else {
413 BEGIN_LP_RING(6);
414 OUT_RING(GFX_OP_DRAWRECT_INFO);
415 OUT_RING(DR1);
416 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
417 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
418 OUT_RING(DR4);
419 OUT_RING(0);
420 ADVANCE_LP_RING();
421 }
422
423 return 0;
424 }
425
426 /* XXX: Emitting the counter should really be moved to part of the IRQ
427 * emit. For now, do it in both places:
428 */
429
430 static void i915_emit_breadcrumb(drm_device_t *dev)
431 {
432 drm_i915_private_t *dev_priv = dev->dev_private;
433 RING_LOCALS;
434
435 dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter;
436
437 if (dev_priv->counter > 0x7FFFFFFFUL)
438 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
439
440 BEGIN_LP_RING(4);
441 OUT_RING(CMD_STORE_DWORD_IDX);
442 OUT_RING(20);
443 OUT_RING(dev_priv->counter);
444 OUT_RING(0);
445 ADVANCE_LP_RING();
446 }
447
448 static int i915_dispatch_cmdbuffer(drm_device_t * dev,
449 drm_i915_cmdbuffer_t * cmd)
450 {
451 int nbox = cmd->num_cliprects;
452 int i = 0, count, ret;
453
454 if (cmd->sz & 0x3) {
455 DRM_ERROR("alignment");
456 return DRM_ERR(EINVAL);
457 }
458
459 i915_kernel_lost_context(dev);
460
461 count = nbox ? nbox : 1;
462
463 for (i = 0; i < count; i++) {
464 if (i < nbox) {
465 ret = i915_emit_box(dev, cmd->cliprects, i,
466 cmd->DR1, cmd->DR4);
467 if (ret)
468 return ret;
469 }
470
471 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
472 if (ret)
473 return ret;
474 }
475
476 i915_emit_breadcrumb(dev);
477 return 0;
478 }
479
480 static int i915_dispatch_batchbuffer(drm_device_t * dev,
481 drm_i915_batchbuffer_t * batch)
482 {
483 drm_i915_private_t *dev_priv = dev->dev_private;
484 drm_clip_rect_t __user *boxes = batch->cliprects;
485 int nbox = batch->num_cliprects;
486 int i = 0, count;
487 RING_LOCALS;
488
489 if ((batch->start | batch->used) & 0x7) {
490 DRM_ERROR("alignment");
491 return DRM_ERR(EINVAL);
492 }
493
494 i915_kernel_lost_context(dev);
495
496 count = nbox ? nbox : 1;
497
498 for (i = 0; i < count; i++) {
499 if (i < nbox) {
500 int ret = i915_emit_box(dev, boxes, i,
501 batch->DR1, batch->DR4);
502 if (ret)
503 return ret;
504 }
505
506 if (dev_priv->use_mi_batchbuffer_start) {
507 BEGIN_LP_RING(2);
508 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
509 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
510 ADVANCE_LP_RING();
511 } else {
512 BEGIN_LP_RING(4);
513 OUT_RING(MI_BATCH_BUFFER);
514 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
515 OUT_RING(batch->start + batch->used - 4);
516 OUT_RING(0);
517 ADVANCE_LP_RING();
518 }
519 }
520
521 i915_emit_breadcrumb(dev);
522
523 return 0;
524 }
525
526 static int i915_dispatch_flip(drm_device_t * dev)
527 {
528 drm_i915_private_t *dev_priv = dev->dev_private;
529 RING_LOCALS;
530
531 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
532 __FUNCTION__,
533 dev_priv->current_page,
534 dev_priv->sarea_priv->pf_current_page);
535
536 i915_kernel_lost_context(dev);
537
538 BEGIN_LP_RING(2);
539 OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
540 OUT_RING(0);
541 ADVANCE_LP_RING();
542
543 BEGIN_LP_RING(6);
544 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
545 OUT_RING(0);
546 if (dev_priv->current_page == 0) {
547 OUT_RING(dev_priv->back_offset);
548 dev_priv->current_page = 1;
549 } else {
550 OUT_RING(dev_priv->front_offset);
551 dev_priv->current_page = 0;
552 }
553 OUT_RING(0);
554 ADVANCE_LP_RING();
555
556 BEGIN_LP_RING(2);
557 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
558 OUT_RING(0);
559 ADVANCE_LP_RING();
560
561 dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
562
563 BEGIN_LP_RING(4);
564 OUT_RING(CMD_STORE_DWORD_IDX);
565 OUT_RING(20);
566 OUT_RING(dev_priv->counter);
567 OUT_RING(0);
568 ADVANCE_LP_RING();
569
570 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
571 return 0;
572 }
573
574 static int i915_quiescent(drm_device_t * dev)
575 {
576 drm_i915_private_t *dev_priv = dev->dev_private;
577
578 i915_kernel_lost_context(dev);
579 return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
580 }
581
582 static int i915_flush_ioctl(DRM_IOCTL_ARGS)
583 {
584 DRM_DEVICE;
585
586 LOCK_TEST_WITH_RETURN(dev, filp);
587
588 return i915_quiescent(dev);
589 }
590
591 static int i915_batchbuffer(DRM_IOCTL_ARGS)
592 {
593 DRM_DEVICE;
594 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
595 u32 *hw_status = dev_priv->hw_status_page;
596 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
597 dev_priv->sarea_priv;
598 drm_i915_batchbuffer_t batch;
599 int ret;
600
601 if (!dev_priv->allow_batchbuffer) {
602 DRM_ERROR("Batchbuffer ioctl disabled\n");
603 return DRM_ERR(EINVAL);
604 }
605
606 DRM_COPY_FROM_USER_IOCTL(batch, (drm_i915_batchbuffer_t __user *) data,
607 sizeof(batch));
608
609 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
610 batch.start, batch.used, batch.num_cliprects);
611
612 LOCK_TEST_WITH_RETURN(dev, filp);
613
614 if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects,
615 batch.num_cliprects *
616 sizeof(drm_clip_rect_t)))
617 return DRM_ERR(EFAULT);
618
619 ret = i915_dispatch_batchbuffer(dev, &batch);
620
621 sarea_priv->last_dispatch = (int)hw_status[5];
622 return ret;
623 }
624
625 static int i915_cmdbuffer(DRM_IOCTL_ARGS)
626 {
627 DRM_DEVICE;
628 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
629 u32 *hw_status = dev_priv->hw_status_page;
630 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
631 dev_priv->sarea_priv;
632 drm_i915_cmdbuffer_t cmdbuf;
633 int ret;
634
635 DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_i915_cmdbuffer_t __user *) data,
636 sizeof(cmdbuf));
637
638 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
639 cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects);
640
641 LOCK_TEST_WITH_RETURN(dev, filp);
642
643 if (cmdbuf.num_cliprects &&
644 DRM_VERIFYAREA_READ(cmdbuf.cliprects,
645 cmdbuf.num_cliprects *
646 sizeof(drm_clip_rect_t))) {
647 DRM_ERROR("Fault accessing cliprects\n");
648 return DRM_ERR(EFAULT);
649 }
650
651 ret = i915_dispatch_cmdbuffer(dev, &cmdbuf);
652 if (ret) {
653 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
654 return ret;
655 }
656
657 sarea_priv->last_dispatch = (int)hw_status[5];
658 return 0;
659 }
660
661 static int i915_flip_bufs(DRM_IOCTL_ARGS)
662 {
663 DRM_DEVICE;
664
665 DRM_DEBUG("%s\n", __FUNCTION__);
666
667 LOCK_TEST_WITH_RETURN(dev, filp);
668
669 return i915_dispatch_flip(dev);
670 }
671
672 static int i915_getparam(DRM_IOCTL_ARGS)
673 {
674 DRM_DEVICE;
675 drm_i915_private_t *dev_priv = dev->dev_private;
676 drm_i915_getparam_t param;
677 int value;
678
679 if (!dev_priv) {
680 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
681 return DRM_ERR(EINVAL);
682 }
683
684 DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_getparam_t __user *) data,
685 sizeof(param));
686
687 switch (param.param) {
688 case I915_PARAM_IRQ_ACTIVE:
689 value = dev->irq ? 1 : 0;
690 break;
691 case I915_PARAM_ALLOW_BATCHBUFFER:
692 value = dev_priv->allow_batchbuffer ? 1 : 0;
693 break;
694 case I915_PARAM_LAST_DISPATCH:
695 value = READ_BREADCRUMB(dev_priv);
696 break;
697 default:
698 DRM_ERROR("Unknown parameter %d\n", param.param);
699 return DRM_ERR(EINVAL);
700 }
701
702 if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
703 DRM_ERROR("DRM_COPY_TO_USER failed\n");
704 return DRM_ERR(EFAULT);
705 }
706
707 return 0;
708 }
709
710 static int i915_setparam(DRM_IOCTL_ARGS)
711 {
712 DRM_DEVICE;
713 drm_i915_private_t *dev_priv = dev->dev_private;
714 drm_i915_setparam_t param;
715
716 if (!dev_priv) {
717 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
718 return DRM_ERR(EINVAL);
719 }
720
721 DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_setparam_t __user *) data,
722 sizeof(param));
723
724 switch (param.param) {
725 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
726 dev_priv->use_mi_batchbuffer_start = param.value;
727 break;
728 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
729 dev_priv->tex_lru_log_granularity = param.value;
730 break;
731 case I915_SETPARAM_ALLOW_BATCHBUFFER:
732 dev_priv->allow_batchbuffer = param.value;
733 break;
734 default:
735 DRM_ERROR("unknown parameter %d\n", param.param);
736 return DRM_ERR(EINVAL);
737 }
738
739 return 0;
740 }
741
742 int i915_driver_load(drm_device_t *dev, unsigned long flags)
743 {
744 /* i915 has 4 more counters */
745 dev->counters += 4;
746 dev->types[6] = _DRM_STAT_IRQ;
747 dev->types[7] = _DRM_STAT_PRIMARY;
748 dev->types[8] = _DRM_STAT_SECONDARY;
749 dev->types[9] = _DRM_STAT_DMA;
750
751 return 0;
752 }
753
754 void i915_driver_lastclose(drm_device_t * dev)
755 {
756 if (dev->dev_private) {
757 drm_i915_private_t *dev_priv = dev->dev_private;
758 i915_mem_takedown(&(dev_priv->agp_heap));
759 }
760 i915_dma_cleanup(dev);
761 }
762
763 void i915_driver_preclose(drm_device_t * dev, DRMFILE filp)
764 {
765 if (dev->dev_private) {
766 drm_i915_private_t *dev_priv = dev->dev_private;
767 i915_mem_release(dev, filp, dev_priv->agp_heap);
768 }
769 }
770
771 drm_ioctl_desc_t i915_ioctls[] = {
772 [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
773 [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, DRM_AUTH},
774 [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, DRM_AUTH},
775 [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, DRM_AUTH},
776 [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, DRM_AUTH},
777 [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, DRM_AUTH},
778 [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, DRM_AUTH},
779 [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
780 [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, DRM_AUTH},
781 [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, DRM_AUTH},
782 [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
783 [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, DRM_AUTH},
784 [DRM_IOCTL_NR(DRM_I915_DESTROY_HEAP)] = { i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
785 [DRM_IOCTL_NR(DRM_I915_SET_VBLANK_PIPE)] = { i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
786 [DRM_IOCTL_NR(DRM_I915_GET_VBLANK_PIPE)] = { i915_vblank_pipe_get, DRM_AUTH },
787 [DRM_IOCTL_NR(DRM_I915_VBLANK_SWAP)] = {i915_vblank_swap, DRM_AUTH},
788 };
789
790 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
791
792 /**
793 * Determine if the device really is AGP or not.
794 *
795 * All Intel graphics chipsets are treated as AGP, even if they are really
796 * PCI-e.
797 *
798 * \param dev The device to be tested.
799 *
800 * \returns
801 * A value of 1 is always retured to indictate every i9x5 is AGP.
802 */
803 int i915_driver_device_is_agp(drm_device_t * dev)
804 {
805 return 1;
806 }
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