drivers/clocksource/sh_cmt.c

   1 /*
   2  * SuperH Timer Support - CMT
   3  *
   4  *  Copyright (C) 2008 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/ioport.h>
  25 #include <linux/io.h>
  26 #include <linux/clk.h>
  27 #include <linux/irq.h>
  28 #include <linux/err.h>
  29 #include <linux/clocksource.h>
  30 #include <linux/clockchips.h>
  31 #include <linux/sh_timer.h>
  32 #include <linux/slab.h>
  33 #include <linux/module.h>
  34
  35 struct sh_cmt_priv {
  36         void __iomem *mapbase;
  37         struct clk *clk;
  38         unsigned long width; /* 16 or 32 bit version of hardware block */
  39         unsigned long overflow_bit;
  40         unsigned long clear_bits;
  41         struct irqaction irqaction;
  42         struct platform_device *pdev;
  43
  44         unsigned long flags;
  45         unsigned long match_value;
  46         unsigned long next_match_value;
  47         unsigned long max_match_value;
  48         unsigned long rate;
  49         spinlock_t lock;
  50         struct clock_event_device ced;
  51         struct clocksource cs;
  52         unsigned long total_cycles;
  53 };
  54
  55 static DEFINE_SPINLOCK(sh_cmt_lock);
  56
  57 #define CMSTR -1 /* shared register */
  58 #define CMCSR 0 /* channel register */
  59 #define CMCNT 1 /* channel register */
  60 #define CMCOR 2 /* channel register */
  61
  62 static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr)
  63 {
  64         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
  65         void __iomem *base = p->mapbase;
  66         unsigned long offs;
  67
  68         if (reg_nr == CMSTR) {
  69                 offs = 0;
  70                 base -= cfg->channel_offset;
  71         } else
  72                 offs = reg_nr;
  73
  74         if (p->width == 16)
  75                 offs <<= 1;
  76         else {
  77                 offs <<= 2;
  78                 if ((reg_nr == CMCNT) || (reg_nr == CMCOR))
  79                         return ioread32(base + offs);
  80         }
  81
  82         return ioread16(base + offs);
  83 }
  84
  85 static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr,
  86                                 unsigned long value)
  87 {
  88         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
  89         void __iomem *base = p->mapbase;
  90         unsigned long offs;
  91
  92         if (reg_nr == CMSTR) {
  93                 offs = 0;
  94                 base -= cfg->channel_offset;
  95         } else
  96                 offs = reg_nr;
  97
  98         if (p->width == 16)
  99                 offs <<= 1;
 100         else {
 101                 offs <<= 2;
 102                 if ((reg_nr == CMCNT) || (reg_nr == CMCOR)) {
 103                         iowrite32(value, base + offs);
 104                         return;
 105                 }
 106         }
 107
 108         iowrite16(value, base + offs);
 109 }
 110
 111 static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
 112                                         int *has_wrapped)
 113 {
 114         unsigned long v1, v2, v3;
 115         int o1, o2;
 116
 117         o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
 118
 119         /* Make sure the timer value is stable. Stolen from acpi_pm.c */
 120         do {
 121                 o2 = o1;
 122                 v1 = sh_cmt_read(p, CMCNT);
 123                 v2 = sh_cmt_read(p, CMCNT);
 124                 v3 = sh_cmt_read(p, CMCNT);
 125                 o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
 126         } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
 127                           || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
 128
 129         *has_wrapped = o1;
 130         return v2;
 131 }
 132
 133
 134 static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
 135 {
 136         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
 137         unsigned long flags, value;
 138
 139         /* start stop register shared by multiple timer channels */
 140         spin_lock_irqsave(&sh_cmt_lock, flags);
 141         value = sh_cmt_read(p, CMSTR);
 142
 143         if (start)
 144                 value |= 1 << cfg->timer_bit;
 145         else
 146                 value &= ~(1 << cfg->timer_bit);
 147
 148         sh_cmt_write(p, CMSTR, value);
 149         spin_unlock_irqrestore(&sh_cmt_lock, flags);
 150 }
 151
 152 static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
 153 {
 154         int ret;
 155
 156         /* enable clock */
 157         ret = clk_enable(p->clk);
 158         if (ret) {
 159                 dev_err(&p->pdev->dev, "cannot enable clock\n");
 160                 return ret;
 161         }
 162
 163         /* make sure channel is disabled */
 164         sh_cmt_start_stop_ch(p, 0);
 165
 166         /* configure channel, periodic mode and maximum timeout */
 167         if (p->width == 16) {
 168                 *rate = clk_get_rate(p->clk) / 512;
 169                 sh_cmt_write(p, CMCSR, 0x43);
 170         } else {
 171                 *rate = clk_get_rate(p->clk) / 8;
 172                 sh_cmt_write(p, CMCSR, 0x01a4);
 173         }
 174
 175         sh_cmt_write(p, CMCOR, 0xffffffff);
 176         sh_cmt_write(p, CMCNT, 0);
 177
 178         /* enable channel */
 179         sh_cmt_start_stop_ch(p, 1);
 180         return 0;
 181 }
 182
 183 static void sh_cmt_disable(struct sh_cmt_priv *p)
 184 {
 185         /* disable channel */
 186         sh_cmt_start_stop_ch(p, 0);
 187
 188         /* disable interrupts in CMT block */
 189         sh_cmt_write(p, CMCSR, 0);
 190
 191         /* stop clock */
 192         clk_disable(p->clk);
 193 }
 194
 195 /* private flags */
 196 #define FLAG_CLOCKEVENT (1 << 0)
 197 #define FLAG_CLOCKSOURCE (1 << 1)
 198 #define FLAG_REPROGRAM (1 << 2)
 199 #define FLAG_SKIPEVENT (1 << 3)
 200 #define FLAG_IRQCONTEXT (1 << 4)
 201
 202 static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p,
 203                                               int absolute)
 204 {
 205         unsigned long new_match;
 206         unsigned long value = p->next_match_value;
 207         unsigned long delay = 0;
 208         unsigned long now = 0;
 209         int has_wrapped;
 210
 211         now = sh_cmt_get_counter(p, &has_wrapped);
 212         p->flags |= FLAG_REPROGRAM; /* force reprogram */
 213
 214         if (has_wrapped) {
 215                 /* we're competing with the interrupt handler.
 216                  *  -> let the interrupt handler reprogram the timer.
 217                  *  -> interrupt number two handles the event.
 218                  */
 219                 p->flags |= FLAG_SKIPEVENT;
 220                 return;
 221         }
 222
 223         if (absolute)
 224                 now = 0;
 225
 226         do {
 227                 /* reprogram the timer hardware,
 228                  * but don't save the new match value yet.
 229                  */
 230                 new_match = now + value + delay;
 231                 if (new_match > p->max_match_value)
 232                         new_match = p->max_match_value;
 233
 234                 sh_cmt_write(p, CMCOR, new_match);
 235
 236                 now = sh_cmt_get_counter(p, &has_wrapped);
 237                 if (has_wrapped && (new_match > p->match_value)) {
 238                         /* we are changing to a greater match value,
 239                          * so this wrap must be caused by the counter
 240                          * matching the old value.
 241                          * -> first interrupt reprograms the timer.
 242                          * -> interrupt number two handles the event.
 243                          */
 244                         p->flags |= FLAG_SKIPEVENT;
 245                         break;
 246                 }
 247
 248                 if (has_wrapped) {
 249                         /* we are changing to a smaller match value,
 250                          * so the wrap must be caused by the counter
 251                          * matching the new value.
 252                          * -> save programmed match value.
 253                          * -> let isr handle the event.
 254                          */
 255                         p->match_value = new_match;
 256                         break;
 257                 }
 258
 259                 /* be safe: verify hardware settings */
 260                 if (now < new_match) {
 261                         /* timer value is below match value, all good.
 262                          * this makes sure we won't miss any match events.
 263                          * -> save programmed match value.
 264                          * -> let isr handle the event.
 265                          */
 266                         p->match_value = new_match;
 267                         break;
 268                 }
 269
 270                 /* the counter has reached a value greater
 271                  * than our new match value. and since the
 272                  * has_wrapped flag isn't set we must have
 273                  * programmed a too close event.
 274                  * -> increase delay and retry.
 275                  */
 276                 if (delay)
 277                         delay <<= 1;
 278                 else
 279                         delay = 1;
 280
 281                 if (!delay)
 282                         dev_warn(&p->pdev->dev, "too long delay\n");
 283
 284         } while (delay);
 285 }
 286
 287 static void __sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
 288 {
 289         if (delta > p->max_match_value)
 290                 dev_warn(&p->pdev->dev, "delta out of range\n");
 291
 292         p->next_match_value = delta;
 293         sh_cmt_clock_event_program_verify(p, 0);
 294 }
 295
 296 static void sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
 297 {
 298         unsigned long flags;
 299
 300         spin_lock_irqsave(&p->lock, flags);
 301         __sh_cmt_set_next(p, delta);
 302         spin_unlock_irqrestore(&p->lock, flags);
 303 }
 304
 305 static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
 306 {
 307         struct sh_cmt_priv *p = dev_id;
 308
 309         /* clear flags */
 310         sh_cmt_write(p, CMCSR, sh_cmt_read(p, CMCSR) & p->clear_bits);
 311
 312         /* update clock source counter to begin with if enabled
 313          * the wrap flag should be cleared by the timer specific
 314          * isr before we end up here.
 315          */
 316         if (p->flags & FLAG_CLOCKSOURCE)
 317                 p->total_cycles += p->match_value + 1;
 318
 319         if (!(p->flags & FLAG_REPROGRAM))
 320                 p->next_match_value = p->max_match_value;
 321
 322         p->flags |= FLAG_IRQCONTEXT;
 323
 324         if (p->flags & FLAG_CLOCKEVENT) {
 325                 if (!(p->flags & FLAG_SKIPEVENT)) {
 326                         if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT) {
 327                                 p->next_match_value = p->max_match_value;
 328                                 p->flags |= FLAG_REPROGRAM;
 329                         }
 330
 331                         p->ced.event_handler(&p->ced);
 332                 }
 333         }
 334
 335         p->flags &= ~FLAG_SKIPEVENT;
 336
 337         if (p->flags & FLAG_REPROGRAM) {
 338                 p->flags &= ~FLAG_REPROGRAM;
 339                 sh_cmt_clock_event_program_verify(p, 1);
 340
 341                 if (p->flags & FLAG_CLOCKEVENT)
 342                         if ((p->ced.mode == CLOCK_EVT_MODE_SHUTDOWN)
 343                             || (p->match_value == p->next_match_value))
 344                                 p->flags &= ~FLAG_REPROGRAM;
 345         }
 346
 347         p->flags &= ~FLAG_IRQCONTEXT;
 348
 349         return IRQ_HANDLED;
 350 }
 351
 352 static int sh_cmt_start(struct sh_cmt_priv *p, unsigned long flag)
 353 {
 354         int ret = 0;
 355         unsigned long flags;
 356
 357         spin_lock_irqsave(&p->lock, flags);
 358
 359         if (!(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
 360                 ret = sh_cmt_enable(p, &p->rate);
 361
 362         if (ret)
 363                 goto out;
 364         p->flags |= flag;
 365
 366         /* setup timeout if no clockevent */
 367         if ((flag == FLAG_CLOCKSOURCE) && (!(p->flags & FLAG_CLOCKEVENT)))
 368                 __sh_cmt_set_next(p, p->max_match_value);
 369  out:
 370         spin_unlock_irqrestore(&p->lock, flags);
 371
 372         return ret;
 373 }
 374
 375 static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag)
 376 {
 377         unsigned long flags;
 378         unsigned long f;
 379
 380         spin_lock_irqsave(&p->lock, flags);
 381
 382         f = p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
 383         p->flags &= ~flag;
 384
 385         if (f && !(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
 386                 sh_cmt_disable(p);
 387
 388         /* adjust the timeout to maximum if only clocksource left */
 389         if ((flag == FLAG_CLOCKEVENT) && (p->flags & FLAG_CLOCKSOURCE))
 390                 __sh_cmt_set_next(p, p->max_match_value);
 391
 392         spin_unlock_irqrestore(&p->lock, flags);
 393 }
 394
 395 static struct sh_cmt_priv *cs_to_sh_cmt(struct clocksource *cs)
 396 {
 397         return container_of(cs, struct sh_cmt_priv, cs);
 398 }
 399
 400 static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
 401 {
 402         struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
 403         unsigned long flags, raw;
 404         unsigned long value;
 405         int has_wrapped;
 406
 407         spin_lock_irqsave(&p->lock, flags);
 408         value = p->total_cycles;
 409         raw = sh_cmt_get_counter(p, &has_wrapped);
 410
 411         if (unlikely(has_wrapped))
 412                 raw += p->match_value + 1;
 413         spin_unlock_irqrestore(&p->lock, flags);
 414
 415         return value + raw;
 416 }
 417
 418 static int sh_cmt_clocksource_enable(struct clocksource *cs)
 419 {
 420         int ret;
 421         struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
 422
 423         p->total_cycles = 0;
 424
 425         ret = sh_cmt_start(p, FLAG_CLOCKSOURCE);
 426         if (!ret)
 427                 __clocksource_updatefreq_hz(cs, p->rate);
 428         return ret;
 429 }
 430
 431 static void sh_cmt_clocksource_disable(struct clocksource *cs)
 432 {
 433         sh_cmt_stop(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
 434 }
 435
 436 static void sh_cmt_clocksource_resume(struct clocksource *cs)
 437 {
 438         sh_cmt_start(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
 439 }
 440
 441 static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
 442                                        char *name, unsigned long rating)
 443 {
 444         struct clocksource *cs = &p->cs;
 445
 446         cs->name = name;
 447         cs->rating = rating;
 448         cs->read = sh_cmt_clocksource_read;
 449         cs->enable = sh_cmt_clocksource_enable;
 450         cs->disable = sh_cmt_clocksource_disable;
 451         cs->suspend = sh_cmt_clocksource_disable;
 452         cs->resume = sh_cmt_clocksource_resume;
 453         cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
 454         cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
 455
 456         dev_info(&p->pdev->dev, "used as clock source\n");
 457
 458         /* Register with dummy 1 Hz value, gets updated in ->enable() */
 459         clocksource_register_hz(cs, 1);
 460         return 0;
 461 }
 462
 463 static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced)
 464 {
 465         return container_of(ced, struct sh_cmt_priv, ced);
 466 }
 467
 468 static void sh_cmt_clock_event_start(struct sh_cmt_priv *p, int periodic)
 469 {
 470         struct clock_event_device *ced = &p->ced;
 471
 472         sh_cmt_start(p, FLAG_CLOCKEVENT);
 473
 474         /* TODO: calculate good shift from rate and counter bit width */
 475
 476         ced->shift = 32;
 477         ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
 478         ced->max_delta_ns = clockevent_delta2ns(p->max_match_value, ced);
 479         ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
 480
 481         if (periodic)
 482                 sh_cmt_set_next(p, ((p->rate + HZ/2) / HZ) - 1);
 483         else
 484                 sh_cmt_set_next(p, p->max_match_value);
 485 }
 486
 487 static void sh_cmt_clock_event_mode(enum clock_event_mode mode,
 488                                     struct clock_event_device *ced)
 489 {
 490         struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
 491
 492         /* deal with old setting first */
 493         switch (ced->mode) {
 494         case CLOCK_EVT_MODE_PERIODIC:
 495         case CLOCK_EVT_MODE_ONESHOT:
 496                 sh_cmt_stop(p, FLAG_CLOCKEVENT);
 497                 break;
 498         default:
 499                 break;
 500         }
 501
 502         switch (mode) {
 503         case CLOCK_EVT_MODE_PERIODIC:
 504                 dev_info(&p->pdev->dev, "used for periodic clock events\n");
 505                 sh_cmt_clock_event_start(p, 1);
 506                 break;
 507         case CLOCK_EVT_MODE_ONESHOT:
 508                 dev_info(&p->pdev->dev, "used for oneshot clock events\n");
 509                 sh_cmt_clock_event_start(p, 0);
 510                 break;
 511         case CLOCK_EVT_MODE_SHUTDOWN:
 512         case CLOCK_EVT_MODE_UNUSED:
 513                 sh_cmt_stop(p, FLAG_CLOCKEVENT);
 514                 break;
 515         default:
 516                 break;
 517         }
 518 }
 519
 520 static int sh_cmt_clock_event_next(unsigned long delta,
 521                                    struct clock_event_device *ced)
 522 {
 523         struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
 524
 525         BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
 526         if (likely(p->flags & FLAG_IRQCONTEXT))
 527                 p->next_match_value = delta - 1;
 528         else
 529                 sh_cmt_set_next(p, delta - 1);
 530
 531         return 0;
 532 }
 533
 534 static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,
 535                                        char *name, unsigned long rating)
 536 {
 537         struct clock_event_device *ced = &p->ced;
 538
 539         memset(ced, 0, sizeof(*ced));
 540
 541         ced->name = name;
 542         ced->features = CLOCK_EVT_FEAT_PERIODIC;
 543         ced->features |= CLOCK_EVT_FEAT_ONESHOT;
 544         ced->rating = rating;
 545         ced->cpumask = cpumask_of(0);
 546         ced->set_next_event = sh_cmt_clock_event_next;
 547         ced->set_mode = sh_cmt_clock_event_mode;
 548
 549         dev_info(&p->pdev->dev, "used for clock events\n");
 550         clockevents_register_device(ced);
 551 }
 552
 553 static int sh_cmt_register(struct sh_cmt_priv *p, char *name,
 554                            unsigned long clockevent_rating,
 555                            unsigned long clocksource_rating)
 556 {
 557         if (p->width == (sizeof(p->max_match_value) * 8))
 558                 p->max_match_value = ~0;
 559         else
 560                 p->max_match_value = (1 << p->width) - 1;
 561
 562         p->match_value = p->max_match_value;
 563         spin_lock_init(&p->lock);
 564
 565         if (clockevent_rating)
 566                 sh_cmt_register_clockevent(p, name, clockevent_rating);
 567
 568         if (clocksource_rating)
 569                 sh_cmt_register_clocksource(p, name, clocksource_rating);
 570
 571         return 0;
 572 }
 573
 574 static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
 575 {
 576         struct sh_timer_config *cfg = pdev->dev.platform_data;
 577         struct resource *res;
 578         int irq, ret;
 579         ret = -ENXIO;
 580
 581         memset(p, 0, sizeof(*p));
 582         p->pdev = pdev;
 583
 584         if (!cfg) {
 585                 dev_err(&p->pdev->dev, "missing platform data\n");
 586                 goto err0;
 587         }
 588
 589         platform_set_drvdata(pdev, p);
 590
 591         res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
 592         if (!res) {
 593                 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
 594                 goto err0;
 595         }
 596
 597         irq = platform_get_irq(p->pdev, 0);
 598         if (irq < 0) {
 599                 dev_err(&p->pdev->dev, "failed to get irq\n");
 600                 goto err0;
 601         }
 602
 603         /* map memory, let mapbase point to our channel */
 604         p->mapbase = ioremap_nocache(res->start, resource_size(res));
 605         if (p->mapbase == NULL) {
 606                 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
 607                 goto err0;
 608         }
 609
 610         /* request irq using setup_irq() (too early for request_irq()) */
 611         p->irqaction.name = dev_name(&p->pdev->dev);
 612         p->irqaction.handler = sh_cmt_interrupt;
 613         p->irqaction.dev_id = p;
 614         p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
 615                              IRQF_IRQPOLL  | IRQF_NOBALANCING;
 616
 617         /* get hold of clock */
 618         p->clk = clk_get(&p->pdev->dev, "cmt_fck");
 619         if (IS_ERR(p->clk)) {
 620                 dev_err(&p->pdev->dev, "cannot get clock\n");
 621                 ret = PTR_ERR(p->clk);
 622                 goto err1;
 623         }
 624
 625         if (resource_size(res) == 6) {
 626                 p->width = 16;
 627                 p->overflow_bit = 0x80;
 628                 p->clear_bits = ~0x80;
 629         } else {
 630                 p->width = 32;
 631                 p->overflow_bit = 0x8000;
 632                 p->clear_bits = ~0xc000;
 633         }
 634
 635         ret = sh_cmt_register(p, (char *)dev_name(&p->pdev->dev),
 636                               cfg->clockevent_rating,
 637                               cfg->clocksource_rating);
 638         if (ret) {
 639                 dev_err(&p->pdev->dev, "registration failed\n");
 640                 goto err1;
 641         }
 642
 643         ret = setup_irq(irq, &p->irqaction);
 644         if (ret) {
 645                 dev_err(&p->pdev->dev, "failed to request irq %d\n", irq);
 646                 goto err1;
 647         }
 648
 649         return 0;
 650
 651 err1:
 652         iounmap(p->mapbase);
 653 err0:
 654         return ret;
 655 }
 656
 657 static int __devinit sh_cmt_probe(struct platform_device *pdev)
 658 {
 659         struct sh_cmt_priv *p = platform_get_drvdata(pdev);
 660         int ret;
 661
 662         if (p) {
 663                 dev_info(&pdev->dev, "kept as earlytimer\n");
 664                 return 0;
 665         }
 666
 667         p = kmalloc(sizeof(*p), GFP_KERNEL);
 668         if (p == NULL) {
 669                 dev_err(&pdev->dev, "failed to allocate driver data\n");
 670                 return -ENOMEM;
 671         }
 672
 673         ret = sh_cmt_setup(p, pdev);
 674         if (ret) {
 675                 kfree(p);
 676                 platform_set_drvdata(pdev, NULL);
 677         }
 678         return ret;
 679 }
 680
 681 static int __devexit sh_cmt_remove(struct platform_device *pdev)
 682 {
 683         return -EBUSY; /* cannot unregister clockevent and clocksource */
 684 }
 685
 686 static struct platform_driver sh_cmt_device_driver = {
 687         .probe          = sh_cmt_probe,
 688         .remove         = __devexit_p(sh_cmt_remove),
 689         .driver         = {
 690                 .name   = "sh_cmt",
 691         }
 692 };
 693
 694 static int __init sh_cmt_init(void)
 695 {
 696         return platform_driver_register(&sh_cmt_device_driver);
 697 }
 698
 699 static void __exit sh_cmt_exit(void)
 700 {
 701         platform_driver_unregister(&sh_cmt_device_driver);
 702 }
 703
 704 early_platform_init("earlytimer", &sh_cmt_device_driver);
 705 module_init(sh_cmt_init);
 706 module_exit(sh_cmt_exit);
 707
 708 MODULE_AUTHOR("Magnus Damm");
 709 MODULE_DESCRIPTION("SuperH CMT Timer Driver");
 710 MODULE_LICENSE("GPL v2");