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Add RapidIO mport driver for IDT TSI721 PCI Express-to-SRIO bridge device.
[linux-2.6/next.git] / drivers / rapidio / devices / tsi721.c
blobdafedc8cc558316afd79fcf81b8b18752d2bc224
1 /*
2 * RapidIO mport driver for Tsi721 PCIExpress-to-SRIO bridge
3 *
4 * Copyright 2011 Integrated Device Technology, Inc.
5 * Alexandre Bounine <alexandre.bounine@idt.com>
6 * Chul Kim <chul.kim@idt.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23 #include <linux/io.h>
24 #include <linux/errno.h>
25 #include <linux/init.h>
26 #include <linux/ioport.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/rio.h>
31 #include <linux/rio_drv.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/interrupt.h>
34 #include <linux/kfifo.h>
35 #include <linux/delay.h>
36
37 #include "tsi721.h"
38
39 #define DEBUG_PW /* Inbound Port-Write debugging */
40
41 static void tsi721_omsg_handler(struct tsi721_device *priv, int ch);
42 static void tsi721_imsg_handler(struct tsi721_device *priv, int ch);
43
44 /**
45 * tsi721_lcread - read from local SREP config space
46 * @mport: RapidIO master port info
47 * @index: ID of RapdiIO interface
48 * @offset: Offset into configuration space
49 * @len: Length (in bytes) of the maintenance transaction
50 * @data: Value to be read into
51 *
52 * Generates a local SREP space read. Returns %0 on
53 * success or %-EINVAL on failure.
54 */
55 static int tsi721_lcread(struct rio_mport *mport, int index, u32 offset,
56 int len, u32 *data)
57 {
58 struct tsi721_device *priv = mport->priv;
59
60 if (len != sizeof(u32))
61 return -EINVAL; /* only 32-bit access is supported */
62
63 *data = ioread32(priv->regs + offset);
64
65 return 0;
66 }
67
68 /**
69 * tsi721_lcwrite - write into local SREP config space
70 * @mport: RapidIO master port info
71 * @index: ID of RapdiIO interface
72 * @offset: Offset into configuration space
73 * @len: Length (in bytes) of the maintenance transaction
74 * @data: Value to be written
75 *
76 * Generates a local write into SREP configuration space. Returns %0 on
77 * success or %-EINVAL on failure.
78 */
79 static int tsi721_lcwrite(struct rio_mport *mport, int index, u32 offset,
80 int len, u32 data)
81 {
82 struct tsi721_device *priv = mport->priv;
83
84 if (len != sizeof(u32))
85 return -EINVAL; /* only 32-bit access is supported */
86
87 iowrite32(data, priv->regs + offset);
88
89 return 0;
90 }
91
92 /**
93 * tsi721_maint_dma - Helper function to generate RapidIO maintenance
94 * transactions using designated Tsi721 DMA channel.
95 * @priv: pointer to tsi721 private data
96 * @sys_size: RapdiIO transport system size
97 * @destid: Destination ID of transaction
98 * @hopcount: Number of hops to target device
99 * @offset: Offset into configuration space
100 * @len: Length (in bytes) of the maintenance transaction
101 * @data: Location to be read from or write into
102 * @do_wr: Operation flag (1 == MAINT_WR)
103 *
104 * Generates a RapidIO maintenance transaction (Read or Write).
105 * Returns %0 on success and %-EINVAL or %-EFAULT on failure.
106 */
107 static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size,
108 u16 destid, u8 hopcount, u32 offset, int len,
109 u32 *data, int do_wr)
110 {
111 struct tsi721_dma_desc *bd_ptr;
112 u32 rd_count, swr_ptr, ch_stat;
113 int i, err = 0;
114 u32 op = do_wr ? MAINT_WR : MAINT_RD;
115
116 if (offset > (RIO_MAINT_SPACE_SZ - len) || (len != sizeof(u32)))
117 return -EINVAL;
118
119 bd_ptr = priv->bdma[TSI721_DMACH_MAINT].bd_base;
120
121 rd_count = ioread32(
122 priv->regs + TSI721_DMAC_DRDCNT(TSI721_DMACH_MAINT));
123
124 /* Initialize DMA descriptor */
125 bd_ptr[0].type_id = cpu_to_le32((DTYPE2 << 29) | (op << 19) | destid);
126 bd_ptr[0].bcount = cpu_to_le32((sys_size << 26) | 0x04);
127 bd_ptr[0].raddr_lo = cpu_to_le32((hopcount << 24) | offset);
128 bd_ptr[0].raddr_hi = 0;
129 if (do_wr)
130 bd_ptr[0].data[0] = cpu_to_be32p(data);
131 else
132 bd_ptr[0].data[0] = 0xffffffff;
133
134 mb();
135
136 /* Start DMA operation */
137 iowrite32(rd_count + 2,
138 priv->regs + TSI721_DMAC_DWRCNT(TSI721_DMACH_MAINT));
139 (void)ioread32(priv->regs + TSI721_DMAC_DWRCNT(TSI721_DMACH_MAINT));
140 i = 0;
141
142 /* Wait until DMA transfer is finished */
143 while ((ch_stat = ioread32(priv->regs +
144 TSI721_DMAC_STS(TSI721_DMACH_MAINT))) & TSI721_DMAC_STS_RUN) {
145 udelay(10);
146 i++;
147 if (i >= 5000000) {
148 dev_dbg(&priv->pdev->dev,
149 "%s : DMA[%d] read timeout ch_status=%x\n",
150 __func__, TSI721_DMACH_MAINT, ch_stat);
151 if (!do_wr)
152 *data = 0xffffffff;
153 err = -EFAULT;
154 goto err_out;
155 }
156 }
157
158 if (ch_stat & TSI721_DMAC_STS_ABORT) {
159 /* If DMA operation aborted due to error,
160 * reinitialize DMA channel
161 */
162 dev_dbg(&priv->pdev->dev, "%s : DMA ABORT ch_stat=%x\n",
163 __func__, ch_stat);
164 dev_dbg(&priv->pdev->dev, "OP=%d : destid=%x hc=%x off=%x\n",
165 do_wr ? MAINT_WR : MAINT_RD, destid, hopcount, offset);
166 iowrite32(TSI721_DMAC_INT_ALL,
167 priv->regs + TSI721_DMAC_INT(TSI721_DMACH_MAINT));
168 iowrite32(TSI721_DMAC_CTL_INIT,
169 priv->regs + TSI721_DMAC_CTL(TSI721_DMACH_MAINT));
170 udelay(10);
171 iowrite32(0, priv->regs +
172 TSI721_DMAC_DWRCNT(TSI721_DMACH_MAINT));
173 udelay(1);
174 if (!do_wr)
175 *data = 0xffffffff;
176 err = -EFAULT;
177 goto err_out;
178 }
179
180 if (!do_wr)
181 *data = be32_to_cpu(bd_ptr[0].data[0]);
182
183 /*
184 * Update descriptor status FIFO RD pointer.
185 * NOTE: Skipping check and clear FIFO entries because we are waiting
186 * for transfer to be completed.
187 */
188 swr_ptr = ioread32(priv->regs + TSI721_DMAC_DSWP(TSI721_DMACH_MAINT));
189 iowrite32(swr_ptr, priv->regs + TSI721_DMAC_DSRP(TSI721_DMACH_MAINT));
190 err_out:
191
192 return err;
193 }
194
195 /**
196 * tsi721_cread_dma - Generate a RapidIO maintenance read transaction
197 * using Tsi721 BDMA engine.
198 * @mport: RapidIO master port control structure
199 * @index: ID of RapdiIO interface
200 * @destid: Destination ID of transaction
201 * @hopcount: Number of hops to target device
202 * @offset: Offset into configuration space
203 * @len: Length (in bytes) of the maintenance transaction
204 * @val: Location to be read into
205 *
206 * Generates a RapidIO maintenance read transaction.
207 * Returns %0 on success and %-EINVAL or %-EFAULT on failure.
208 */
209 static int tsi721_cread_dma(struct rio_mport *mport, int index, u16 destid,
210 u8 hopcount, u32 offset, int len, u32 *data)
211 {
212 struct tsi721_device *priv = mport->priv;
213
214 return tsi721_maint_dma(priv, mport->sys_size, destid, hopcount,
215 offset, len, data, 0);
216 }
217
218 /**
219 * tsi721_cwrite_dma - Generate a RapidIO maintenance write transaction
220 * using Tsi721 BDMA engine
221 * @mport: RapidIO master port control structure
222 * @index: ID of RapdiIO interface
223 * @destid: Destination ID of transaction
224 * @hopcount: Number of hops to target device
225 * @offset: Offset into configuration space
226 * @len: Length (in bytes) of the maintenance transaction
227 * @val: Value to be written
228 *
229 * Generates a RapidIO maintenance write transaction.
230 * Returns %0 on success and %-EINVAL or %-EFAULT on failure.
231 */
232 static int tsi721_cwrite_dma(struct rio_mport *mport, int index, u16 destid,
233 u8 hopcount, u32 offset, int len, u32 data)
234 {
235 struct tsi721_device *priv = mport->priv;
236 u32 temp = data;
237
238 return tsi721_maint_dma(priv, mport->sys_size, destid, hopcount,
239 offset, len, &temp, 1);
240 }
241
242 /**
243 * tsi721_pw_handler - Tsi721 inbound port-write interrupt handler
244 * @mport: RapidIO master port structure
245 *
246 * Handles inbound port-write interrupts. Copies PW message from an internal
247 * buffer into PW message FIFO and schedules deferred routine to process
248 * queued messages.
249 */
250 static int
251 tsi721_pw_handler(struct rio_mport *mport)
252 {
253 struct tsi721_device *priv = mport->priv;
254 u32 pw_stat;
255 u32 pw_buf[TSI721_RIO_PW_MSG_SIZE/sizeof(u32)];
256
257
258 pw_stat = ioread32(priv->regs + TSI721_RIO_PW_RX_STAT);
259
260 if (pw_stat & TSI721_RIO_PW_RX_STAT_PW_VAL) {
261 pw_buf[0] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(0));
262 pw_buf[1] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(1));
263 pw_buf[2] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(2));
264 pw_buf[3] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(3));
265
266 /* Queue PW message (if there is room in FIFO),
267 * otherwise discard it.
268 */
269 spin_lock(&priv->pw_fifo_lock);
270 if (kfifo_avail(&priv->pw_fifo) >= TSI721_RIO_PW_MSG_SIZE)
271 kfifo_in(&priv->pw_fifo, pw_buf,
272 TSI721_RIO_PW_MSG_SIZE);
273 else
274 priv->pw_discard_count++;
275 spin_unlock(&priv->pw_fifo_lock);
276 }
277
278 /* Clear pending PW interrupts */
279 iowrite32(TSI721_RIO_PW_RX_STAT_PW_DISC | TSI721_RIO_PW_RX_STAT_PW_VAL,
280 priv->regs + TSI721_RIO_PW_RX_STAT);
281
282 schedule_work(&priv->pw_work);
283
284 return 0;
285 }
286
287 static void tsi721_pw_dpc(struct work_struct *work)
288 {
289 struct tsi721_device *priv = container_of(work, struct tsi721_device,
290 pw_work);
291 unsigned long flags;
292 u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)]; /* Use full size PW message
293 buffer for RIO layer */
294
295 /*
296 * Process port-write messages
297 */
298 spin_lock_irqsave(&priv->pw_fifo_lock, flags);
299 while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer,
300 TSI721_RIO_PW_MSG_SIZE)) {
301 /* Process one message */
302 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
303 #ifdef DEBUG_PW
304 {
305 u32 i;
306 pr_debug("%s : Port-Write Message:", __func__);
307 for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); ) {
308 pr_debug("0x%02x: %08x %08x %08x %08x", i*4,
309 msg_buffer[i], msg_buffer[i + 1],
310 msg_buffer[i + 2], msg_buffer[i + 3]);
311 i += 4;
312 }
313 pr_debug("\n");
314 }
315 #endif
316 /* Pass the port-write message to RIO core for processing */
317 rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer);
318 spin_lock_irqsave(&priv->pw_fifo_lock, flags);
319 }
320 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
321 }
322
323 /**
324 * tsi721_pw_enable - enable/disable port-write interface init
325 * @mport: Master port implementing the port write unit
326 * @enable: 1=enable; 0=disable port-write message handling
327 */
328 static int tsi721_pw_enable(struct rio_mport *mport, int enable)
329 {
330 struct tsi721_device *priv = mport->priv;
331 u32 rval;
332
333 rval = ioread32(priv->regs + TSI721_RIO_EM_INT_ENABLE);
334
335 if (enable)
336 rval |= TSI721_RIO_EM_INT_ENABLE_PW_RX;
337 else
338 rval &= ~TSI721_RIO_EM_INT_ENABLE_PW_RX;
339
340 /* Clear pending PW interrupts */
341 iowrite32(TSI721_RIO_PW_RX_STAT_PW_DISC | TSI721_RIO_PW_RX_STAT_PW_VAL,
342 priv->regs + TSI721_RIO_PW_RX_STAT);
343 /* Update enable bits */
344 iowrite32(rval, priv->regs + TSI721_RIO_EM_INT_ENABLE);
345
346 return 0;
347 }
348
349 /**
350 * tsi721_dsend - Send a RapidIO doorbell
351 * @mport: RapidIO master port info
352 * @index: ID of RapidIO interface
353 * @destid: Destination ID of target device
354 * @data: 16-bit info field of RapidIO doorbell
355 *
356 * Sends a RapidIO doorbell message. Always returns %0.
357 */
358 static int tsi721_dsend(struct rio_mport *mport, int index,
359 u16 destid, u16 data)
360 {
361 struct tsi721_device *priv = mport->priv;
362 u32 offset;
363
364 offset = (((mport->sys_size) ? RIO_TT_CODE_16 : RIO_TT_CODE_8) << 18) |
365 (destid << 2);
366
367 dev_dbg(&priv->pdev->dev,
368 "Send Doorbell 0x%04x to destID 0x%x\n", data, destid);
369 iowrite16be(data, priv->odb_base + offset);
370
371 return 0;
372 }
373
374 /**
375 * tsi721_dbell_handler - Tsi721 doorbell interrupt handler
376 * @mport: RapidIO master port structure
377 *
378 * Handles inbound doorbell interrupts. Copies doorbell entry from an internal
379 * buffer into DB message FIFO and schedules deferred routine to process
380 * queued DBs.
381 */
382 static int
383 tsi721_dbell_handler(struct rio_mport *mport)
384 {
385 struct tsi721_device *priv = mport->priv;
386 u32 regval;
387
388 /* Disable IDB interrupts */
389 regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
390 regval &= ~TSI721_SR_CHINT_IDBQRCV;
391 iowrite32(regval,
392 priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
393
394 schedule_work(&priv->idb_work);
395
396 return 0;
397 }
398
399 static void tsi721_db_dpc(struct work_struct *work)
400 {
401 struct tsi721_device *priv = container_of(work, struct tsi721_device,
402 idb_work);
403 struct rio_mport *mport;
404 struct rio_dbell *dbell;
405 int found = 0;
406 u32 wr_ptr, rd_ptr;
407 u64 *idb_entry;
408 u32 regval;
409 union {
410 u64 msg;
411 u8 bytes[8];
412 } idb;
413
414 /*
415 * Process queued inbound doorbells
416 */
417 mport = priv->mport;
418
419 wr_ptr = ioread32(priv->regs + TSI721_IDQ_WP(IDB_QUEUE));
420 rd_ptr = ioread32(priv->regs + TSI721_IDQ_RP(IDB_QUEUE));
421
422 while (wr_ptr != rd_ptr) {
423 idb_entry = (u64 *)(priv->idb_base +
424 (TSI721_IDB_ENTRY_SIZE * rd_ptr));
425 rd_ptr++;
426 idb.msg = *idb_entry;
427 *idb_entry = 0;
428
429 /* Process one doorbell */
430 list_for_each_entry(dbell, &mport->dbells, node) {
431 if ((dbell->res->start <= DBELL_INF(idb.bytes)) &&
432 (dbell->res->end >= DBELL_INF(idb.bytes))) {
433 found = 1;
434 break;
435 }
436 }
437
438 if (found) {
439 dbell->dinb(mport, dbell->dev_id, DBELL_SID(idb.bytes),
440 DBELL_TID(idb.bytes), DBELL_INF(idb.bytes));
441 } else {
442 dev_dbg(&priv->pdev->dev,
443 "spurious inb doorbell, sid %2.2x tid %2.2x"
444 " info %4.4x\n", DBELL_SID(idb.bytes),
445 DBELL_TID(idb.bytes), DBELL_INF(idb.bytes));
446 }
447 }
448
449 iowrite32(rd_ptr & (IDB_QSIZE - 1),
450 priv->regs + TSI721_IDQ_RP(IDB_QUEUE));
451
452 /* Re-enable IDB interrupts */
453 regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
454 regval |= TSI721_SR_CHINT_IDBQRCV;
455 iowrite32(regval,
456 priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
457 }
458
459 /**
460 * tsi721_srio_msix - Tsi721 MSI-X SRIO MAC interrupt handler
461 * @irq: Linux interrupt number
462 * @ptr: Pointer to interrupt-specific data (mport structure)
463 *
464 * Handles Tsi721 interrupts from SRIO MAC.
465 */
466 static irqreturn_t tsi721_srio_msix(int irq, void *ptr)
467 {
468 struct tsi721_device *priv = ((struct rio_mport *)ptr)->priv;
469 u32 srio_int;
470
471 /* Service SRIO MAC interrupts */
472 srio_int = ioread32(priv->regs + TSI721_RIO_EM_INT_STAT);
473 if (srio_int & TSI721_RIO_EM_INT_STAT_PW_RX)
474 tsi721_pw_handler((struct rio_mport *)ptr);
475
476 return IRQ_HANDLED;
477 }
478
479 /**
480 * tsi721_sr2pc_ch_msix - Tsi721 MSI-X SR2PC Channel interrupt handler
481 * @irq: Linux interrupt number
482 * @ptr: Pointer to interrupt-specific data (mport structure)
483 *
484 * Handles Tsi721 interrupts from SR2PC Channel.
485 * NOTE: At this moment services only one SR2PC channel associated with inbound
486 * doorbells.
487 */
488 static irqreturn_t tsi721_sr2pc_ch_msix(int irq, void *ptr)
489 {
490 struct tsi721_device *priv = ((struct rio_mport *)ptr)->priv;
491 u32 sr_ch_int;
492
493 /* Service Inbound DB interrupt from SR2PC channel */
494 sr_ch_int = ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
495 if (sr_ch_int & TSI721_SR_CHINT_IDBQRCV)
496 tsi721_dbell_handler((struct rio_mport *)ptr);
497
498 /* Clear interrupts */
499 iowrite32(sr_ch_int, priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
500 /* Read back to ensure that interrupt was cleared */
501 sr_ch_int = ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
502
503 return IRQ_HANDLED;
504 }
505
506 /**
507 * tsi721_omsg_msix - MSI-X interrupt handler for outbound messaging
508 * @irq: Linux interrupt number
509 * @ptr: Pointer to interrupt-specific data (mport structure)
510 *
511 * Handles outbound messaging interrupts signaled using MSI-X.
512 */
513 static irqreturn_t tsi721_omsg_msix(int irq, void *ptr)
514 {
515 struct tsi721_device *priv = ((struct rio_mport *)ptr)->priv;
516 int mbox;
517
518 mbox = (irq - priv->msix[TSI721_VECT_OMB0_DONE].vector) % RIO_MAX_MBOX;
519 tsi721_omsg_handler(priv, mbox);
520 return IRQ_HANDLED;
521 }
522
523 /**
524 * tsi721_imsg_msix - MSI-X interrupt handler for inbound messaging
525 * @irq: Linux interrupt number
526 * @ptr: Pointer to interrupt-specific data (mport structure)
527 *
528 * Handles inbound messaging interrupts signaled using MSI-X.
529 */
530 static irqreturn_t tsi721_imsg_msix(int irq, void *ptr)
531 {
532 struct tsi721_device *priv = ((struct rio_mport *)ptr)->priv;
533 int mbox;
534
535 mbox = (irq - priv->msix[TSI721_VECT_IMB0_RCV].vector) % RIO_MAX_MBOX;
536 tsi721_imsg_handler(priv, mbox + 4);
537 return IRQ_HANDLED;
538 }
539
540 /**
541 * tsi721_irqhandler - Tsi721 interrupt handler
542 * @irq: Linux interrupt number
543 * @ptr: Pointer to interrupt-specific data (mport structure)
544 *
545 * Handles Tsi721 interrupts signaled using MSI and INTA. Checks reported
546 * interrupt events and calls an event-specific handler(s).
547 */
548 static irqreturn_t tsi721_irqhandler(int irq, void *ptr)
549 {
550 struct rio_mport *mport = (struct rio_mport *)ptr;
551 struct tsi721_device *priv = mport->priv;
552 u32 dev_int;
553 u32 dev_ch_int;
554 u32 intval;
555 u32 ch_inte;
556
557 dev_int = ioread32(priv->regs + TSI721_DEV_INT);
558 if (!dev_int)
559 return IRQ_NONE;
560
561 dev_ch_int = ioread32(priv->regs + TSI721_DEV_CHAN_INT);
562
563 if (dev_int & TSI721_DEV_INT_SR2PC_CH) {
564 /* Service SR2PC Channel interrupts */
565 if (dev_ch_int & TSI721_INT_SR2PC_CHAN(IDB_QUEUE)) {
566 /* Service Inbound Doorbell interrupt */
567 intval = ioread32(priv->regs +
568 TSI721_SR_CHINT(IDB_QUEUE));
569 if (intval & TSI721_SR_CHINT_IDBQRCV)
570 tsi721_dbell_handler(mport);
571 else
572 dev_info(&priv->pdev->dev,
573 "Unsupported SR_CH_INT %x\n", intval);
574
575 /* Clear interrupts */
576 iowrite32(intval,
577 priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
578 (void)ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
579 }
580 }
581
582 if (dev_int & TSI721_DEV_INT_SMSG_CH) {
583 int ch;
584
585 /*
586 * Service channel interrupts from Messaging Engine
587 */
588
589 if (dev_ch_int & TSI721_INT_IMSG_CHAN_M) { /* Inbound Msg */
590 /* Disable signaled OB MSG Channel interrupts */
591 ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
592 ch_inte &= ~(dev_ch_int & TSI721_INT_IMSG_CHAN_M);
593 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);
594
595 /*
596 * Process Inbound Message interrupt for each MBOX
597 */
598 for (ch = 4; ch < RIO_MAX_MBOX + 4; ch++) {
599 if (!(dev_ch_int & TSI721_INT_IMSG_CHAN(ch)))
600 continue;
601 tsi721_imsg_handler(priv, ch);
602 }
603 }
604
605 if (dev_ch_int & TSI721_INT_OMSG_CHAN_M) { /* Outbound Msg */
606 /* Disable signaled OB MSG Channel interrupts */
607 ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
608 ch_inte &= ~(dev_ch_int & TSI721_INT_OMSG_CHAN_M);
609 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);
610
611 /*
612 * Process Outbound Message interrupts for each MBOX
613 */
614
615 for (ch = 0; ch < RIO_MAX_MBOX; ch++) {
616 if (!(dev_ch_int & TSI721_INT_OMSG_CHAN(ch)))
617 continue;
618 tsi721_omsg_handler(priv, ch);
619 }
620 }
621 }
622
623 if (dev_int & TSI721_DEV_INT_SRIO) {
624 /* Service SRIO MAC interrupts */
625 intval = ioread32(priv->regs + TSI721_RIO_EM_INT_STAT);
626 if (intval & TSI721_RIO_EM_INT_STAT_PW_RX)
627 tsi721_pw_handler(mport);
628 }
629
630 return IRQ_HANDLED;
631 }
632
633 static void tsi721_interrupts_init(struct tsi721_device *priv)
634 {
635 u32 intr;
636
637 /* Enable IDB interrupts */
638 iowrite32(TSI721_SR_CHINT_ALL,
639 priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
640 iowrite32(TSI721_SR_CHINT_IDBQRCV,
641 priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
642 iowrite32(TSI721_INT_SR2PC_CHAN(IDB_QUEUE),
643 priv->regs + TSI721_DEV_CHAN_INTE);
644
645 /* Enable SRIO MAC interrupts */
646 iowrite32(TSI721_RIO_EM_DEV_INT_EN_INT,
647 priv->regs + TSI721_RIO_EM_DEV_INT_EN);
648
649 if (priv->flags & TSI721_USING_MSIX)
650 intr = TSI721_DEV_INT_SRIO;
651 else
652 intr = TSI721_DEV_INT_SR2PC_CH | TSI721_DEV_INT_SRIO |
653 TSI721_DEV_INT_SMSG_CH;
654
655 iowrite32(intr, priv->regs + TSI721_DEV_INTE);
656 (void)ioread32(priv->regs + TSI721_DEV_INTE);
657 }
658
659 /**
660 * tsi721_request_msix - register interrupt service for MSI-X mode.
661 * @mport: RapidIO master port structure
662 *
663 * Registers MSI-X interrupt service routines for interrupts that are active
664 * immediately after mport initialization. Messaging interrupt service routines
665 * should be registered during corresponding open requests.
666 */
667 static int tsi721_request_msix(struct rio_mport *mport)
668 {
669 struct tsi721_device *priv = mport->priv;
670 int err = 0;
671
672 err = request_irq(priv->msix[TSI721_VECT_IDB].vector,
673 tsi721_sr2pc_ch_msix, 0,
674 priv->msix[TSI721_VECT_IDB].irq_name, (void *)mport);
675 if (err)
676 goto out;
677
678 err = request_irq(priv->msix[TSI721_VECT_PWRX].vector,
679 tsi721_srio_msix, 0,
680 priv->msix[TSI721_VECT_PWRX].irq_name, (void *)mport);
681 out:
682 return err;
683 }
684
685 static int tsi721_request_irq(struct rio_mport *mport)
686 {
687 struct tsi721_device *priv = mport->priv;
688 int err;
689
690 if (priv->flags & TSI721_USING_MSIX)
691 err = tsi721_request_msix(mport);
692 else
693 err = request_irq(priv->pdev->irq, tsi721_irqhandler,
694 (priv->flags & TSI721_USING_MSI) ? 0 : IRQF_SHARED,
695 DRV_NAME, (void *)mport);
696
697 if (err)
698 dev_err(&priv->pdev->dev,
699 "Unable to allocate interrupt, Error: %d\n", err);
700
701 return err;
702 }
703
704 /**
705 * tsi721_enable_msix - Attempts to enable MSI-X support for Tsi721.
706 * @priv: pointer to tsi721 private data
707 *
708 * Configures MSI-X support for Tsi721. Supports only an exact number
709 * of requested vectors.
710 */
711 static int tsi721_enable_msix(struct tsi721_device *priv)
712 {
713 struct msix_entry entries[TSI721_VECT_MAX];
714 int err;
715 int i;
716
717 entries[TSI721_VECT_IDB].entry = TSI721_MSIX_SR2PC_IDBQ_RCV(IDB_QUEUE);
718 entries[TSI721_VECT_PWRX].entry = TSI721_MSIX_SRIO_MAC_INT;
719
720 /*
721 * Initialize MSI-X entries for Messaging Engine:
722 * this driver supports four RIO mailboxes (inbound and outbound)
723 * NOTE: Inbound message MBOX 0...4 use IB channels 4...7. Therefore
724 * offset +4 is added to IB MBOX number.
725 */
726 for (i = 0; i < RIO_MAX_MBOX; i++) {
727 entries[TSI721_VECT_IMB0_RCV + i].entry =
728 TSI721_MSIX_IMSG_DQ_RCV(i + 4);
729 entries[TSI721_VECT_IMB0_INT + i].entry =
730 TSI721_MSIX_IMSG_INT(i + 4);
731 entries[TSI721_VECT_OMB0_DONE + i].entry =
732 TSI721_MSIX_OMSG_DONE(i);
733 entries[TSI721_VECT_OMB0_INT + i].entry =
734 TSI721_MSIX_OMSG_INT(i);
735 }
736
737 err = pci_enable_msix(priv->pdev, entries, ARRAY_SIZE(entries));
738 if (err) {
739 if (err > 0)
740 dev_info(&priv->pdev->dev,
741 "Only %d MSI-X vectors available, "
742 "not using MSI-X\n", err);
743 return err;
744 }
745
746 /*
747 * Copy MSI-X vector information into tsi721 private structure
748 */
749 priv->msix[TSI721_VECT_IDB].vector = entries[TSI721_VECT_IDB].vector;
750 snprintf(priv->msix[TSI721_VECT_IDB].irq_name, IRQ_DEVICE_NAME_MAX,
751 DRV_NAME "-idb@pci:%s", pci_name(priv->pdev));
752 priv->msix[TSI721_VECT_PWRX].vector = entries[TSI721_VECT_PWRX].vector;
753 snprintf(priv->msix[TSI721_VECT_PWRX].irq_name, IRQ_DEVICE_NAME_MAX,
754 DRV_NAME "-pwrx@pci:%s", pci_name(priv->pdev));
755
756 for (i = 0; i < RIO_MAX_MBOX; i++) {
757 priv->msix[TSI721_VECT_IMB0_RCV + i].vector =
758 entries[TSI721_VECT_IMB0_RCV + i].vector;
759 snprintf(priv->msix[TSI721_VECT_IMB0_RCV + i].irq_name,
760 IRQ_DEVICE_NAME_MAX, DRV_NAME "-imbr%d@pci:%s",
761 i, pci_name(priv->pdev));
762
763 priv->msix[TSI721_VECT_IMB0_INT + i].vector =
764 entries[TSI721_VECT_IMB0_INT + i].vector;
765 snprintf(priv->msix[TSI721_VECT_IMB0_INT + i].irq_name,
766 IRQ_DEVICE_NAME_MAX, DRV_NAME "-imbi%d@pci:%s",
767 i, pci_name(priv->pdev));
768
769 priv->msix[TSI721_VECT_OMB0_DONE + i].vector =
770 entries[TSI721_VECT_OMB0_DONE + i].vector;
771 snprintf(priv->msix[TSI721_VECT_OMB0_DONE + i].irq_name,
772 IRQ_DEVICE_NAME_MAX, DRV_NAME "-ombd%d@pci:%s",
773 i, pci_name(priv->pdev));
774
775 priv->msix[TSI721_VECT_OMB0_INT + i].vector =
776 entries[TSI721_VECT_OMB0_INT + i].vector;
777 snprintf(priv->msix[TSI721_VECT_OMB0_INT + i].irq_name,
778 IRQ_DEVICE_NAME_MAX, DRV_NAME "-ombi%d@pci:%s",
779 i, pci_name(priv->pdev));
780 }
781
782 return 0;
783 }
784
785 /**
786 * tsi721_init_pc2sr_mapping - initializes outbound (PCIe->SRIO)
787 * translation regions.
788 * @priv: pointer to tsi721 private data
789 *
790 * Disables SREP translation regions.
791 */
792 static void tsi721_init_pc2sr_mapping(struct tsi721_device *priv)
793 {
794 int i;
795
796 /* Disable all PC2SR translation windows */
797 for (i = 0; i < TSI721_OBWIN_NUM; i++)
798 iowrite32(0, priv->regs + TSI721_OBWINLB(i));
799 }
800
801 /**
802 * tsi721_init_sr2pc_mapping - initializes inbound (SRIO->PCIe)
803 * translation regions.
804 * @priv: pointer to tsi721 private data
805 *
806 * Disables inbound windows.
807 */
808 static void tsi721_init_sr2pc_mapping(struct tsi721_device *priv)
809 {
810 int i;
811
812 /* Disable all SR2PC inbound windows */
813 for (i = 0; i < TSI721_IBWIN_NUM; i++)
814 iowrite32(0, priv->regs + TSI721_IBWINLB(i));
815 }
816
817 /**
818 * tsi721_port_write_init - Inbound port write interface init
819 * @priv: pointer to tsi721 private data
820 *
821 * Initializes inbound port write handler.
822 * Returns %0 on success or %-ENOMEM on failure.
823 */
824 static int tsi721_port_write_init(struct tsi721_device *priv)
825 {
826 priv->pw_discard_count = 0;
827 INIT_WORK(&priv->pw_work, tsi721_pw_dpc);
828 spin_lock_init(&priv->pw_fifo_lock);
829 if (kfifo_alloc(&priv->pw_fifo,
830 TSI721_RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
831 dev_err(&priv->pdev->dev, "PW FIFO allocation failed\n");
832 return -ENOMEM;
833 }
834
835 /* Use reliable port-write capture mode */
836 iowrite32(TSI721_RIO_PW_CTL_PWC_REL, priv->regs + TSI721_RIO_PW_CTL);
837 return 0;
838 }
839
840 static int tsi721_doorbell_init(struct tsi721_device *priv)
841 {
842 /* Outbound Doorbells do not require any setup.
843 * Tsi721 uses dedicated PCI BAR1 to generate doorbells.
844 * That BAR1 was mapped during the probe routine.
845 */
846
847 /* Initialize Inbound Doorbell processing DPC and queue */
848 priv->db_discard_count = 0;
849 INIT_WORK(&priv->idb_work, tsi721_db_dpc);
850
851 /* Allocate buffer for inbound doorbells queue */
852 priv->idb_base = dma_alloc_coherent(&priv->pdev->dev,
853 IDB_QSIZE * TSI721_IDB_ENTRY_SIZE,
854 &priv->idb_dma, GFP_KERNEL);
855 if (!priv->idb_base)
856 return -ENOMEM;
857
858 memset(priv->idb_base, 0, IDB_QSIZE * TSI721_IDB_ENTRY_SIZE);
859
860 dev_dbg(&priv->pdev->dev, "Allocated IDB buffer @ %p (phys = %llx)\n",
861 priv->idb_base, (unsigned long long)priv->idb_dma);
862
863 iowrite32(TSI721_IDQ_SIZE_VAL(IDB_QSIZE),
864 priv->regs + TSI721_IDQ_SIZE(IDB_QUEUE));
865 iowrite32(((u64)priv->idb_dma >> 32),
866 priv->regs + TSI721_IDQ_BASEU(IDB_QUEUE));
867 iowrite32(((u64)priv->idb_dma & TSI721_IDQ_BASEL_ADDR),
868 priv->regs + TSI721_IDQ_BASEL(IDB_QUEUE));
869 /* Enable accepting all inbound doorbells */
870 iowrite32(0, priv->regs + TSI721_IDQ_MASK(IDB_QUEUE));
871
872 iowrite32(TSI721_IDQ_INIT, priv->regs + TSI721_IDQ_CTL(IDB_QUEUE));
873
874 iowrite32(0, priv->regs + TSI721_IDQ_RP(IDB_QUEUE));
875
876 return 0;
877 }
878
879 static void tsi721_doorbell_free(struct tsi721_device *priv)
880 {
881 if (priv->idb_base == NULL)
882 return;
883
884 /* Free buffer allocated for inbound doorbell queue */
885 dma_free_coherent(&priv->pdev->dev, IDB_QSIZE * TSI721_IDB_ENTRY_SIZE,
886 priv->idb_base, priv->idb_dma);
887 priv->idb_base = NULL;
888 }
889
890 static int tsi721_bdma_ch_init(struct tsi721_device *priv, int chnum)
891 {
892 struct tsi721_dma_desc *bd_ptr;
893 u64 *sts_ptr;
894 dma_addr_t bd_phys, sts_phys;
895 int sts_size;
896 int bd_num = priv->bdma[chnum].bd_num;
897
898 dev_dbg(&priv->pdev->dev, "Init Block DMA Engine, CH%d\n", chnum);
899
900 /*
901 * Initialize DMA channel for maintenance requests
902 */
903
904 /* Allocate space for DMA descriptors */
905 bd_ptr = dma_alloc_coherent(&priv->pdev->dev,
906 bd_num * sizeof(struct tsi721_dma_desc),
907 &bd_phys, GFP_KERNEL);
908 if (!bd_ptr)
909 return -ENOMEM;
910
911 priv->bdma[chnum].bd_phys = bd_phys;
912 priv->bdma[chnum].bd_base = bd_ptr;
913
914 memset(bd_ptr, 0, bd_num * sizeof(struct tsi721_dma_desc));
915
916 dev_dbg(&priv->pdev->dev, "DMA descriptors @ %p (phys = %llx)\n",
917 bd_ptr, (unsigned long long)bd_phys);
918
919 /* Allocate space for descriptor status FIFO */
920 sts_size = (bd_num >= TSI721_DMA_MINSTSSZ) ?
921 bd_num : TSI721_DMA_MINSTSSZ;
922 sts_size = roundup_pow_of_two(sts_size);
923 sts_ptr = dma_alloc_coherent(&priv->pdev->dev,
924 sts_size * sizeof(struct tsi721_dma_sts),
925 &sts_phys, GFP_KERNEL);
926 if (!sts_ptr) {
927 /* Free space allocated for DMA descriptors */
928 dma_free_coherent(&priv->pdev->dev,
929 bd_num * sizeof(struct tsi721_dma_desc),
930 bd_ptr, bd_phys);
931 priv->bdma[chnum].bd_base = NULL;
932 return -ENOMEM;
933 }
934
935 priv->bdma[chnum].sts_phys = sts_phys;
936 priv->bdma[chnum].sts_base = sts_ptr;
937 priv->bdma[chnum].sts_size = sts_size;
938
939 memset(sts_ptr, 0, sts_size);
940
941 dev_dbg(&priv->pdev->dev,
942 "desc status FIFO @ %p (phys = %llx) size=0x%x\n",
943 sts_ptr, (unsigned long long)sts_phys, sts_size);
944
945 /* Initialize DMA descriptors ring */
946 bd_ptr[bd_num - 1].type_id = cpu_to_le32(DTYPE3 << 29);
947 bd_ptr[bd_num - 1].next_lo = cpu_to_le32((u64)bd_phys &
948 TSI721_DMAC_DPTRL_MASK);
949 bd_ptr[bd_num - 1].next_hi = cpu_to_le32((u64)bd_phys >> 32);
950
951 /* Setup DMA descriptor pointers */
952 iowrite32(((u64)bd_phys >> 32),
953 priv->regs + TSI721_DMAC_DPTRH(chnum));
954 iowrite32(((u64)bd_phys & TSI721_DMAC_DPTRL_MASK),
955 priv->regs + TSI721_DMAC_DPTRL(chnum));
956
957 /* Setup descriptor status FIFO */
958 iowrite32(((u64)sts_phys >> 32),
959 priv->regs + TSI721_DMAC_DSBH(chnum));
960 iowrite32(((u64)sts_phys & TSI721_DMAC_DSBL_MASK),
961 priv->regs + TSI721_DMAC_DSBL(chnum));
962 iowrite32(TSI721_DMAC_DSSZ_SIZE(sts_size),
963 priv->regs + TSI721_DMAC_DSSZ(chnum));
964
965 /* Clear interrupt bits */
966 iowrite32(TSI721_DMAC_INT_ALL,
967 priv->regs + TSI721_DMAC_INT(chnum));
968
969 (void)ioread32(priv->regs + TSI721_DMAC_INT(chnum));
970
971 /* Toggle DMA channel initialization */
972 iowrite32(TSI721_DMAC_CTL_INIT, priv->regs + TSI721_DMAC_CTL(chnum));
973 (void)ioread32(priv->regs + TSI721_DMAC_CTL(chnum));
974 udelay(10);
975
976 return 0;
977 }
978
979 static int tsi721_bdma_ch_free(struct tsi721_device *priv, int chnum)
980 {
981 u32 ch_stat;
982
983 if (priv->bdma[chnum].bd_base == NULL)
984 return 0;
985
986 /* Check if DMA channel still running */
987 ch_stat = ioread32(priv->regs + TSI721_DMAC_STS(chnum));
988 if (ch_stat & TSI721_DMAC_STS_RUN)
989 return -EFAULT;
990
991 /* Put DMA channel into init state */
992 iowrite32(TSI721_DMAC_CTL_INIT,
993 priv->regs + TSI721_DMAC_CTL(chnum));
994
995 /* Free space allocated for DMA descriptors */
996 dma_free_coherent(&priv->pdev->dev,
997 priv->bdma[chnum].bd_num * sizeof(struct tsi721_dma_desc),
998 priv->bdma[chnum].bd_base, priv->bdma[chnum].bd_phys);
999 priv->bdma[chnum].bd_base = NULL;
1000
1001 /* Free space allocated for status FIFO */
1002 dma_free_coherent(&priv->pdev->dev,
1003 priv->bdma[chnum].sts_size * sizeof(struct tsi721_dma_sts),
1004 priv->bdma[chnum].sts_base, priv->bdma[chnum].sts_phys);
1005 priv->bdma[chnum].sts_base = NULL;
1006 return 0;
1007 }
1008
1009 static int tsi721_bdma_init(struct tsi721_device *priv)
1010 {
1011 /* Initialize BDMA channel allocated for RapidIO maintenance read/write
1012 * request generation
1013 */
1014 priv->bdma[TSI721_DMACH_MAINT].bd_num = 2;
1015 if (tsi721_bdma_ch_init(priv, TSI721_DMACH_MAINT)) {
1016 dev_err(&priv->pdev->dev, "Unable to initialize maintenance DMA"
1017 " channel %d, aborting\n", TSI721_DMACH_MAINT);
1018 return -ENOMEM;
1019 }
1020
1021 return 0;
1022 }
1023
1024 static void tsi721_bdma_free(struct tsi721_device *priv)
1025 {
1026 tsi721_bdma_ch_free(priv, TSI721_DMACH_MAINT);
1027 }
1028
1029 /* Enable Inbound Messaging Interrupts */
1030 static void
1031 tsi721_imsg_interrupt_enable(struct tsi721_device *priv, int ch,
1032 u32 inte_mask)
1033 {
1034 u32 rval;
1035
1036 if (!inte_mask)
1037 return;
1038
1039 /* Clear pending Inbound Messaging interrupts */
1040 iowrite32(inte_mask, priv->regs + TSI721_IBDMAC_INT(ch));
1041
1042 /* Enable Inbound Messaging interrupts */
1043 rval = ioread32(priv->regs + TSI721_IBDMAC_INTE(ch));
1044 iowrite32(rval | inte_mask, priv->regs + TSI721_IBDMAC_INTE(ch));
1045
1046 if (priv->flags & TSI721_USING_MSIX)
1047 return; /* Finished if we are in MSI-X mode */
1048
1049 /*
1050 * For MSI and INTA interrupt signalling we need to enable next levels
1051 */
1052
1053 /* Enable Device Channel Interrupt */
1054 rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1055 iowrite32(rval | TSI721_INT_IMSG_CHAN(ch),
1056 priv->regs + TSI721_DEV_CHAN_INTE);
1057 }
1058
1059 /* Disable Inbound Messaging Interrupts */
1060 static void
1061 tsi721_imsg_interrupt_disable(struct tsi721_device *priv, int ch,
1062 u32 inte_mask)
1063 {
1064 u32 rval;
1065
1066 if (!inte_mask)
1067 return;
1068
1069 /* Clear pending Inbound Messaging interrupts */
1070 iowrite32(inte_mask, priv->regs + TSI721_IBDMAC_INT(ch));
1071
1072 /* Disable Inbound Messaging interrupts */
1073 rval = ioread32(priv->regs + TSI721_IBDMAC_INTE(ch));
1074 rval &= ~inte_mask;
1075 iowrite32(rval, priv->regs + TSI721_IBDMAC_INTE(ch));
1076
1077 if (priv->flags & TSI721_USING_MSIX)
1078 return; /* Finished if we are in MSI-X mode */
1079
1080 /*
1081 * For MSI and INTA interrupt signalling we need to disable next levels
1082 */
1083
1084 /* Disable Device Channel Interrupt */
1085 rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1086 rval &= ~TSI721_INT_IMSG_CHAN(ch);
1087 iowrite32(rval, priv->regs + TSI721_DEV_CHAN_INTE);
1088 }
1089
1090 /* Enable Outbound Messaging interrupts */
1091 static void
1092 tsi721_omsg_interrupt_enable(struct tsi721_device *priv, int ch,
1093 u32 inte_mask)
1094 {
1095 u32 rval;
1096
1097 if (!inte_mask)
1098 return;
1099
1100 /* Clear pending Outbound Messaging interrupts */
1101 iowrite32(inte_mask, priv->regs + TSI721_OBDMAC_INT(ch));
1102
1103 /* Enable Outbound Messaging channel interrupts */
1104 rval = ioread32(priv->regs + TSI721_OBDMAC_INTE(ch));
1105 iowrite32(rval | inte_mask, priv->regs + TSI721_OBDMAC_INTE(ch));
1106
1107 if (priv->flags & TSI721_USING_MSIX)
1108 return; /* Finished if we are in MSI-X mode */
1109
1110 /*
1111 * For MSI and INTA interrupt signalling we need to enable next levels
1112 */
1113
1114 /* Enable Device Channel Interrupt */
1115 rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1116 iowrite32(rval | TSI721_INT_OMSG_CHAN(ch),
1117 priv->regs + TSI721_DEV_CHAN_INTE);
1118 }
1119
1120 /* Disable Outbound Messaging interrupts */
1121 static void
1122 tsi721_omsg_interrupt_disable(struct tsi721_device *priv, int ch,
1123 u32 inte_mask)
1124 {
1125 u32 rval;
1126
1127 if (!inte_mask)
1128 return;
1129
1130 /* Clear pending Outbound Messaging interrupts */
1131 iowrite32(inte_mask, priv->regs + TSI721_OBDMAC_INT(ch));
1132
1133 /* Disable Outbound Messaging interrupts */
1134 rval = ioread32(priv->regs + TSI721_OBDMAC_INTE(ch));
1135 rval &= ~inte_mask;
1136 iowrite32(rval, priv->regs + TSI721_OBDMAC_INTE(ch));
1137
1138 if (priv->flags & TSI721_USING_MSIX)
1139 return; /* Finished if we are in MSI-X mode */
1140
1141 /*
1142 * For MSI and INTA interrupt signalling we need to disable next levels
1143 */
1144
1145 /* Disable Device Channel Interrupt */
1146 rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1147 rval &= ~TSI721_INT_OMSG_CHAN(ch);
1148 iowrite32(rval, priv->regs + TSI721_DEV_CHAN_INTE);
1149 }
1150
1151 /**
1152 * tsi721_add_outb_message - Add message to the Tsi721 outbound message queue
1153 * @mport: Master port with outbound message queue
1154 * @rdev: Target of outbound message
1155 * @mbox: Outbound mailbox
1156 * @buffer: Message to add to outbound queue
1157 * @len: Length of message
1158 */
1159 static int
1160 tsi721_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
1161 void *buffer, size_t len)
1162 {
1163 struct tsi721_device *priv = mport->priv;
1164 struct tsi721_omsg_desc *desc;
1165 u32 tx_slot;
1166
1167 if (!priv->omsg_init[mbox] ||
1168 len > TSI721_MSG_MAX_SIZE || len < 8)
1169 return -EINVAL;
1170
1171 tx_slot = priv->omsg_ring[mbox].tx_slot;
1172
1173 /* Copy copy message into transfer buffer */
1174 memcpy(priv->omsg_ring[mbox].omq_base[tx_slot], buffer, len);
1175
1176 if (len & 0x7)
1177 len += 8;
1178
1179 /* Build descriptor associated with buffer */
1180 desc = priv->omsg_ring[mbox].omd_base;
1181 desc[tx_slot].type_id = cpu_to_le32((DTYPE4 << 29) | rdev->destid);
1182 if (tx_slot % 4 == 0)
1183 desc[tx_slot].type_id |= cpu_to_le32(TSI721_OMD_IOF);
1184
1185 desc[tx_slot].msg_info =
1186 cpu_to_le32((mport->sys_size << 26) | (mbox << 22) |
1187 (0xe << 12) | (len & 0xff8));
1188 desc[tx_slot].bufptr_lo =
1189 cpu_to_le32((u64)priv->omsg_ring[mbox].omq_phys[tx_slot] &
1190 0xffffffff);
1191 desc[tx_slot].bufptr_hi =
1192 cpu_to_le32((u64)priv->omsg_ring[mbox].omq_phys[tx_slot] >> 32);
1193
1194 priv->omsg_ring[mbox].wr_count++;
1195
1196 /* Go to next descriptor */
1197 if (++priv->omsg_ring[mbox].tx_slot == priv->omsg_ring[mbox].size) {
1198 priv->omsg_ring[mbox].tx_slot = 0;
1199 /* Move through the ring link descriptor at the end */
1200 priv->omsg_ring[mbox].wr_count++;
1201 }
1202
1203 mb();
1204
1205 /* Set new write count value */
1206 iowrite32(priv->omsg_ring[mbox].wr_count,
1207 priv->regs + TSI721_OBDMAC_DWRCNT(mbox));
1208 (void)ioread32(priv->regs + TSI721_OBDMAC_DWRCNT(mbox));
1209
1210 return 0;
1211 }
1212
1213 /**
1214 * tsi721_omsg_handler - Outbound Message Interrupt Handler
1215 * @priv: pointer to tsi721 private data
1216 * @ch: number of OB MSG channel to service
1217 *
1218 * Services channel interrupts from outbound messaging engine.
1219 */
1220 static void tsi721_omsg_handler(struct tsi721_device *priv, int ch)
1221 {
1222 u32 omsg_int;
1223
1224 spin_lock(&priv->omsg_ring[ch].lock);
1225
1226 omsg_int = ioread32(priv->regs + TSI721_OBDMAC_INT(ch));
1227
1228 if (omsg_int & TSI721_OBDMAC_INT_ST_FULL)
1229 dev_info(&priv->pdev->dev,
1230 "OB MBOX%d: Status FIFO is full\n", ch);
1231
1232 if (omsg_int & (TSI721_OBDMAC_INT_DONE | TSI721_OBDMAC_INT_IOF_DONE)) {
1233 u32 srd_ptr;
1234 u64 *sts_ptr, last_ptr = 0, prev_ptr = 0;
1235 int i, j;
1236 u32 tx_slot;
1237
1238 /*
1239 * Find last successfully processed descriptor
1240 */
1241
1242 /* Check and clear descriptor status FIFO entries */
1243 srd_ptr = priv->omsg_ring[ch].sts_rdptr;
1244 sts_ptr = priv->omsg_ring[ch].sts_base;
1245 j = srd_ptr * 8;
1246 while (sts_ptr[j]) {
1247 for (i = 0; i < 8 && sts_ptr[j]; i++, j++) {
1248 prev_ptr = last_ptr;
1249 last_ptr = sts_ptr[j];
1250 sts_ptr[j] = 0;
1251 }
1252
1253 ++srd_ptr;
1254 srd_ptr %= priv->omsg_ring[ch].sts_size;
1255 j = srd_ptr * 8;
1256 }
1257
1258 if (last_ptr == 0)
1259 goto no_sts_update;
1260
1261 priv->omsg_ring[ch].sts_rdptr = srd_ptr;
1262 iowrite32(srd_ptr, priv->regs + TSI721_OBDMAC_DSRP(ch));
1263
1264 if (!priv->mport->outb_msg[ch].mcback)
1265 goto no_sts_update;
1266
1267 /* Inform upper layer about transfer completion */
1268
1269 tx_slot = (last_ptr - (u64)priv->omsg_ring[ch].omd_phys)/
1270 sizeof(struct tsi721_omsg_desc);
1271
1272 /*
1273 * Check if this is a Link Descriptor (LD).
1274 * If yes, ignore LD and use descriptor processed
1275 * before LD.
1276 */
1277 if (tx_slot == priv->omsg_ring[ch].size) {
1278 if (prev_ptr)
1279 tx_slot = (prev_ptr -
1280 (u64)priv->omsg_ring[ch].omd_phys)/
1281 sizeof(struct tsi721_omsg_desc);
1282 else
1283 goto no_sts_update;
1284 }
1285
1286 /* Move slot index to the next message to be sent */
1287 ++tx_slot;
1288 if (tx_slot == priv->omsg_ring[ch].size)
1289 tx_slot = 0;
1290 BUG_ON(tx_slot >= priv->omsg_ring[ch].size);
1291 priv->mport->outb_msg[ch].mcback(priv->mport,
1292 priv->omsg_ring[ch].dev_id, ch,
1293 tx_slot);
1294 }
1295
1296 no_sts_update:
1297
1298 if (omsg_int & TSI721_OBDMAC_INT_ERROR) {
1299 /*
1300 * Outbound message operation aborted due to error,
1301 * reinitialize OB MSG channel
1302 */
1303
1304 dev_dbg(&priv->pdev->dev, "OB MSG ABORT ch_stat=%x\n",
1305 ioread32(priv->regs + TSI721_OBDMAC_STS(ch)));
1306
1307 iowrite32(TSI721_OBDMAC_INT_ERROR,
1308 priv->regs + TSI721_OBDMAC_INT(ch));
1309 iowrite32(TSI721_OBDMAC_CTL_INIT,
1310 priv->regs + TSI721_OBDMAC_CTL(ch));
1311 (void)ioread32(priv->regs + TSI721_OBDMAC_CTL(ch));
1312
1313 /* Inform upper level to clear all pending tx slots */
1314 if (priv->mport->outb_msg[ch].mcback)
1315 priv->mport->outb_msg[ch].mcback(priv->mport,
1316 priv->omsg_ring[ch].dev_id, ch,
1317 priv->omsg_ring[ch].tx_slot);
1318 /* Synch tx_slot tracking */
1319 iowrite32(priv->omsg_ring[ch].tx_slot,
1320 priv->regs + TSI721_OBDMAC_DRDCNT(ch));
1321 (void)ioread32(priv->regs + TSI721_OBDMAC_DRDCNT(ch));
1322 priv->omsg_ring[ch].wr_count = priv->omsg_ring[ch].tx_slot;
1323 priv->omsg_ring[ch].sts_rdptr = 0;
1324 }
1325
1326 /* Clear channel interrupts */
1327 iowrite32(omsg_int, priv->regs + TSI721_OBDMAC_INT(ch));
1328
1329 if (!(priv->flags & TSI721_USING_MSIX)) {
1330 u32 ch_inte;
1331
1332 /* Re-enable channel interrupts */
1333 ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1334 ch_inte |= TSI721_INT_OMSG_CHAN(ch);
1335 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);
1336 }
1337
1338 spin_unlock(&priv->omsg_ring[ch].lock);
1339 }
1340
1341 /**
1342 * tsi721_open_outb_mbox - Initialize Tsi721 outbound mailbox
1343 * @mport: Master port implementing Outbound Messaging Engine
1344 * @dev_id: Device specific pointer to pass on event
1345 * @mbox: Mailbox to open
1346 * @entries: Number of entries in the outbound mailbox ring
1347 */
1348 static int tsi721_open_outb_mbox(struct rio_mport *mport, void *dev_id,
1349 int mbox, int entries)
1350 {
1351 struct tsi721_device *priv = mport->priv;
1352 struct tsi721_omsg_desc *bd_ptr;
1353 int i, rc = 0;
1354
1355 if ((entries < TSI721_OMSGD_MIN_RING_SIZE) ||
1356 (entries > (TSI721_OMSGD_RING_SIZE)) ||
1357 (!is_power_of_2(entries)) || mbox >= RIO_MAX_MBOX) {
1358 rc = -EINVAL;
1359 goto out;
1360 }
1361
1362 priv->omsg_ring[mbox].dev_id = dev_id;
1363 priv->omsg_ring[mbox].size = entries;
1364 priv->omsg_ring[mbox].sts_rdptr = 0;
1365 spin_lock_init(&priv->omsg_ring[mbox].lock);
1366
1367 /* Outbound Msg Buffer allocation based on
1368 the number of maximum descriptor entries */
1369 for (i = 0; i < entries; i++) {
1370 priv->omsg_ring[mbox].omq_base[i] =
1371 dma_alloc_coherent(
1372 &priv->pdev->dev, TSI721_MSG_BUFFER_SIZE,
1373 &priv->omsg_ring[mbox].omq_phys[i],
1374 GFP_KERNEL);
1375 if (priv->omsg_ring[mbox].omq_base[i] == NULL) {
1376 dev_dbg(&priv->pdev->dev,
1377 "Unable to allocate OB MSG data buffer for"
1378 " MBOX%d\n", mbox);
1379 rc = -ENOMEM;
1380 goto out_buf;
1381 }
1382 }
1383
1384 /* Outbound message descriptor allocation */
1385 priv->omsg_ring[mbox].omd_base = dma_alloc_coherent(
1386 &priv->pdev->dev,
1387 (entries + 1) * sizeof(struct tsi721_omsg_desc),
1388 &priv->omsg_ring[mbox].omd_phys, GFP_KERNEL);
1389 if (priv->omsg_ring[mbox].omd_base == NULL) {
1390 dev_dbg(&priv->pdev->dev,
1391 "Unable to allocate OB MSG descriptor memory "
1392 "for MBOX%d\n", mbox);
1393 rc = -ENOMEM;
1394 goto out_buf;
1395 }
1396
1397 memset(priv->omsg_ring[mbox].omd_base, 0,
1398 (entries + 1) * sizeof(struct tsi721_omsg_desc));
1399 priv->omsg_ring[mbox].tx_slot = 0;
1400
1401 /* Outbound message descriptor status FIFO allocation */
1402 priv->omsg_ring[mbox].sts_size = roundup_pow_of_two(entries + 1);
1403 priv->omsg_ring[mbox].sts_base = dma_alloc_coherent(&priv->pdev->dev,
1404 priv->omsg_ring[mbox].sts_size *
1405 sizeof(struct tsi721_dma_sts),
1406 &priv->omsg_ring[mbox].sts_phys, GFP_KERNEL);
1407 if (priv->omsg_ring[mbox].sts_base == NULL) {
1408 dev_dbg(&priv->pdev->dev,
1409 "Unable to allocate OB MSG descriptor status FIFO "
1410 "for MBOX%d\n", mbox);
1411 rc = -ENOMEM;
1412 goto out_desc;
1413 }
1414
1415 memset(priv->omsg_ring[mbox].sts_base, 0,
1416 entries * sizeof(struct tsi721_dma_sts));
1417
1418 /*
1419 * Configure Outbound Messaging Engine
1420 */
1421
1422 /* Setup Outbound Message descriptor pointer */
1423 iowrite32(((u64)priv->omsg_ring[mbox].omd_phys >> 32),
1424 priv->regs + TSI721_OBDMAC_DPTRH(mbox));
1425 iowrite32(((u64)priv->omsg_ring[mbox].omd_phys &
1426 TSI721_OBDMAC_DPTRL_MASK),
1427 priv->regs + TSI721_OBDMAC_DPTRL(mbox));
1428
1429 /* Setup Outbound Message descriptor status FIFO */
1430 iowrite32(((u64)priv->omsg_ring[mbox].sts_phys >> 32),
1431 priv->regs + TSI721_OBDMAC_DSBH(mbox));
1432 iowrite32(((u64)priv->omsg_ring[mbox].sts_phys &
1433 TSI721_OBDMAC_DSBL_MASK),
1434 priv->regs + TSI721_OBDMAC_DSBL(mbox));
1435 iowrite32(TSI721_DMAC_DSSZ_SIZE(priv->omsg_ring[mbox].sts_size),
1436 priv->regs + (u32)TSI721_OBDMAC_DSSZ(mbox));
1437
1438 /* Enable interrupts */
1439
1440 if (priv->flags & TSI721_USING_MSIX) {
1441 /* Request interrupt service if we are in MSI-X mode */
1442 rc = request_irq(
1443 priv->msix[TSI721_VECT_OMB0_DONE + mbox].vector,
1444 tsi721_omsg_msix, 0,
1445 priv->msix[TSI721_VECT_OMB0_DONE + mbox].irq_name,
1446 (void *)mport);
1447
1448 if (rc) {
1449 dev_dbg(&priv->pdev->dev,
1450 "Unable to allocate MSI-X interrupt for "
1451 "OBOX%d-DONE\n", mbox);
1452 goto out_stat;
1453 }
1454
1455 rc = request_irq(priv->msix[TSI721_VECT_OMB0_INT + mbox].vector,
1456 tsi721_omsg_msix, 0,
1457 priv->msix[TSI721_VECT_OMB0_INT + mbox].irq_name,
1458 (void *)mport);
1459
1460 if (rc) {
1461 dev_dbg(&priv->pdev->dev,
1462 "Unable to allocate MSI-X interrupt for "
1463 "MBOX%d-INT\n", mbox);
1464 free_irq(
1465 priv->msix[TSI721_VECT_OMB0_DONE + mbox].vector,
1466 (void *)mport);
1467 goto out_stat;
1468 }
1469 }
1470
1471 tsi721_omsg_interrupt_enable(priv, mbox, TSI721_OBDMAC_INT_ALL);
1472
1473 /* Initialize Outbound Message descriptors ring */
1474 bd_ptr = priv->omsg_ring[mbox].omd_base;
1475 bd_ptr[entries].type_id = cpu_to_le32(DTYPE5 << 29);
1476 bd_ptr[entries].next_lo =
1477 cpu_to_le32((u64)priv->omsg_ring[mbox].omd_phys &
1478 TSI721_OBDMAC_DPTRL_MASK);
1479 bd_ptr[entries].next_hi =
1480 cpu_to_le32((u64)priv->omsg_ring[mbox].omd_phys >> 32);
1481 priv->omsg_ring[mbox].wr_count = 0;
1482 mb();
1483
1484 /* Initialize Outbound Message engine */
1485 iowrite32(TSI721_OBDMAC_CTL_INIT, priv->regs + TSI721_OBDMAC_CTL(mbox));
1486 (void)ioread32(priv->regs + TSI721_OBDMAC_DWRCNT(mbox));
1487 udelay(10);
1488
1489 priv->omsg_init[mbox] = 1;
1490
1491 return 0;
1492
1493 out_stat:
1494 dma_free_coherent(&priv->pdev->dev,
1495 priv->omsg_ring[mbox].sts_size * sizeof(struct tsi721_dma_sts),
1496 priv->omsg_ring[mbox].sts_base,
1497 priv->omsg_ring[mbox].sts_phys);
1498
1499 priv->omsg_ring[mbox].sts_base = NULL;
1500
1501 out_desc:
1502 dma_free_coherent(&priv->pdev->dev,
1503 (entries + 1) * sizeof(struct tsi721_omsg_desc),
1504 priv->omsg_ring[mbox].omd_base,
1505 priv->omsg_ring[mbox].omd_phys);
1506
1507 priv->omsg_ring[mbox].omd_base = NULL;
1508
1509 out_buf:
1510 for (i = 0; i < priv->omsg_ring[mbox].size; i++) {
1511 if (priv->omsg_ring[mbox].omq_base[i]) {
1512 dma_free_coherent(&priv->pdev->dev,
1513 TSI721_MSG_BUFFER_SIZE,
1514 priv->omsg_ring[mbox].omq_base[i],
1515 priv->omsg_ring[mbox].omq_phys[i]);
1516
1517 priv->omsg_ring[mbox].omq_base[i] = NULL;
1518 }
1519 }
1520
1521 out:
1522 return rc;
1523 }
1524
1525 /**
1526 * tsi721_close_outb_mbox - Close Tsi721 outbound mailbox
1527 * @mport: Master port implementing the outbound message unit
1528 * @mbox: Mailbox to close
1529 */
1530 static void tsi721_close_outb_mbox(struct rio_mport *mport, int mbox)
1531 {
1532 struct tsi721_device *priv = mport->priv;
1533 u32 i;
1534
1535 if (!priv->omsg_init[mbox])
1536 return;
1537 priv->omsg_init[mbox] = 0;
1538
1539 /* Disable Interrupts */
1540
1541 tsi721_omsg_interrupt_disable(priv, mbox, TSI721_OBDMAC_INT_ALL);
1542
1543 if (priv->flags & TSI721_USING_MSIX) {
1544 free_irq(priv->msix[TSI721_VECT_OMB0_DONE + mbox].vector,
1545 (void *)mport);
1546 free_irq(priv->msix[TSI721_VECT_OMB0_INT + mbox].vector,
1547 (void *)mport);
1548 }
1549
1550 /* Free OMSG Descriptor Status FIFO */
1551 dma_free_coherent(&priv->pdev->dev,
1552 priv->omsg_ring[mbox].sts_size * sizeof(struct tsi721_dma_sts),
1553 priv->omsg_ring[mbox].sts_base,
1554 priv->omsg_ring[mbox].sts_phys);
1555
1556 priv->omsg_ring[mbox].sts_base = NULL;
1557
1558 /* Free OMSG descriptors */
1559 dma_free_coherent(&priv->pdev->dev,
1560 (priv->omsg_ring[mbox].size + 1) *
1561 sizeof(struct tsi721_omsg_desc),
1562 priv->omsg_ring[mbox].omd_base,
1563 priv->omsg_ring[mbox].omd_phys);
1564
1565 priv->omsg_ring[mbox].omd_base = NULL;
1566
1567 /* Free message buffers */
1568 for (i = 0; i < priv->omsg_ring[mbox].size; i++) {
1569 if (priv->omsg_ring[mbox].omq_base[i]) {
1570 dma_free_coherent(&priv->pdev->dev,
1571 TSI721_MSG_BUFFER_SIZE,
1572 priv->omsg_ring[mbox].omq_base[i],
1573 priv->omsg_ring[mbox].omq_phys[i]);
1574
1575 priv->omsg_ring[mbox].omq_base[i] = NULL;
1576 }
1577 }
1578 }
1579
1580 /**
1581 * tsi721_imsg_handler - Inbound Message Interrupt Handler
1582 * @priv: pointer to tsi721 private data
1583 * @ch: inbound message channel number to service
1584 *
1585 * Services channel interrupts from inbound messaging engine.
1586 */
1587 static void tsi721_imsg_handler(struct tsi721_device *priv, int ch)
1588 {
1589 u32 mbox = ch - 4;
1590 u32 imsg_int;
1591
1592 imsg_int = ioread32(priv->regs + TSI721_IBDMAC_INT(ch));
1593
1594 if (imsg_int & TSI721_IBDMAC_INT_SRTO)
1595 dev_info(&priv->pdev->dev, "IB MBOX%d SRIO timeout\n",
1596 mbox);
1597
1598 if (imsg_int & TSI721_IBDMAC_INT_PC_ERROR)
1599 dev_info(&priv->pdev->dev, "IB MBOX%d PCIe error\n",
1600 mbox);
1601
1602 if (imsg_int & TSI721_IBDMAC_INT_FQ_LOW)
1603 dev_info(&priv->pdev->dev,
1604 "IB MBOX%d IB free queue low\n", mbox);
1605
1606 /* Clear IB channel interrupts */
1607 iowrite32(imsg_int, priv->regs + TSI721_IBDMAC_INT(ch));
1608
1609 /* If an IB Msg is received notify the upper layer */
1610 if (imsg_int & TSI721_IBDMAC_INT_DQ_RCV &&
1611 priv->mport->inb_msg[mbox].mcback)
1612 priv->mport->inb_msg[mbox].mcback(priv->mport,
1613 priv->imsg_ring[mbox].dev_id, mbox, -1);
1614
1615 if (!(priv->flags & TSI721_USING_MSIX)) {
1616 u32 ch_inte;
1617
1618 /* Re-enable channel interrupts */
1619 ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1620 ch_inte |= TSI721_INT_IMSG_CHAN(ch);
1621 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);
1622 }
1623 }
1624
1625 /**
1626 * tsi721_open_inb_mbox - Initialize Tsi721 inbound mailbox
1627 * @mport: Master port implementing the Inbound Messaging Engine
1628 * @dev_id: Device specific pointer to pass on event
1629 * @mbox: Mailbox to open
1630 * @entries: Number of entries in the inbound mailbox ring
1631 */
1632 static int tsi721_open_inb_mbox(struct rio_mport *mport, void *dev_id,
1633 int mbox, int entries)
1634 {
1635 struct tsi721_device *priv = mport->priv;
1636 int ch = mbox + 4;
1637 int i;
1638 u64 *free_ptr;
1639 int rc = 0;
1640
1641 if ((entries < TSI721_IMSGD_MIN_RING_SIZE) ||
1642 (entries > TSI721_IMSGD_RING_SIZE) ||
1643 (!is_power_of_2(entries)) || mbox >= RIO_MAX_MBOX) {
1644 rc = -EINVAL;
1645 goto out;
1646 }
1647
1648 /* Initialize IB Messaging Ring */
1649 priv->imsg_ring[mbox].dev_id = dev_id;
1650 priv->imsg_ring[mbox].size = entries;
1651 priv->imsg_ring[mbox].rx_slot = 0;
1652 priv->imsg_ring[mbox].desc_rdptr = 0;
1653 priv->imsg_ring[mbox].fq_wrptr = 0;
1654 for (i = 0; i < priv->imsg_ring[mbox].size; i++)
1655 priv->imsg_ring[mbox].imq_base[i] = NULL;
1656
1657 /* Allocate buffers for incoming messages */
1658 priv->imsg_ring[mbox].buf_base =
1659 dma_alloc_coherent(&priv->pdev->dev,
1660 entries * TSI721_MSG_BUFFER_SIZE,
1661 &priv->imsg_ring[mbox].buf_phys,
1662 GFP_KERNEL);
1663
1664 if (priv->imsg_ring[mbox].buf_base == NULL) {
1665 dev_err(&priv->pdev->dev,
1666 "Failed to allocate buffers for IB MBOX%d\n", mbox);
1667 rc = -ENOMEM;
1668 goto out;
1669 }
1670
1671 /* Allocate memory for circular free list */
1672 priv->imsg_ring[mbox].imfq_base =
1673 dma_alloc_coherent(&priv->pdev->dev,
1674 entries * 8,
1675 &priv->imsg_ring[mbox].imfq_phys,
1676 GFP_KERNEL);
1677
1678 if (priv->imsg_ring[mbox].imfq_base == NULL) {
1679 dev_err(&priv->pdev->dev,
1680 "Failed to allocate free queue for IB MBOX%d\n", mbox);
1681 rc = -ENOMEM;
1682 goto out_buf;
1683 }
1684
1685 /* Allocate memory for Inbound message descriptors */
1686 priv->imsg_ring[mbox].imd_base =
1687 dma_alloc_coherent(&priv->pdev->dev,
1688 entries * sizeof(struct tsi721_imsg_desc),
1689 &priv->imsg_ring[mbox].imd_phys, GFP_KERNEL);
1690
1691 if (priv->imsg_ring[mbox].imd_base == NULL) {
1692 dev_err(&priv->pdev->dev,
1693 "Failed to allocate descriptor memory for IB MBOX%d\n",
1694 mbox);
1695 rc = -ENOMEM;
1696 goto out_dma;
1697 }
1698
1699 /* Fill free buffer pointer list */
1700 free_ptr = priv->imsg_ring[mbox].imfq_base;
1701 for (i = 0; i < entries; i++)
1702 free_ptr[i] = cpu_to_le64(
1703 (u64)(priv->imsg_ring[mbox].buf_phys) +
1704 i * 0x1000);
1705
1706 mb();
1707
1708 /*
1709 * For mapping of inbound SRIO Messages into appropriate queues we need
1710 * to set Inbound Device ID register in the messaging engine. We do it
1711 * once when first inbound mailbox is requested.
1712 */
1713 if (!(priv->flags & TSI721_IMSGID_SET)) {
1714 iowrite32((u32)priv->mport->host_deviceid,
1715 priv->regs + TSI721_IB_DEVID);
1716 priv->flags |= TSI721_IMSGID_SET;
1717 }
1718
1719 /*
1720 * Configure Inbound Messaging channel (ch = mbox + 4)
1721 */
1722
1723 /* Setup Inbound Message free queue */
1724 iowrite32(((u64)priv->imsg_ring[mbox].imfq_phys >> 32),
1725 priv->regs + TSI721_IBDMAC_FQBH(ch));
1726 iowrite32(((u64)priv->imsg_ring[mbox].imfq_phys &
1727 TSI721_IBDMAC_FQBL_MASK),
1728 priv->regs+TSI721_IBDMAC_FQBL(ch));
1729 iowrite32(TSI721_DMAC_DSSZ_SIZE(entries),
1730 priv->regs + TSI721_IBDMAC_FQSZ(ch));
1731
1732 /* Setup Inbound Message descriptor queue */
1733 iowrite32(((u64)priv->imsg_ring[mbox].imd_phys >> 32),
1734 priv->regs + TSI721_IBDMAC_DQBH(ch));
1735 iowrite32(((u32)priv->imsg_ring[mbox].imd_phys &
1736 (u32)TSI721_IBDMAC_DQBL_MASK),
1737 priv->regs+TSI721_IBDMAC_DQBL(ch));
1738 iowrite32(TSI721_DMAC_DSSZ_SIZE(entries),
1739 priv->regs + TSI721_IBDMAC_DQSZ(ch));
1740
1741 /* Enable interrupts */
1742
1743 if (priv->flags & TSI721_USING_MSIX) {
1744 /* Request interrupt service if we are in MSI-X mode */
1745 rc = request_irq(priv->msix[TSI721_VECT_IMB0_RCV + mbox].vector,
1746 tsi721_imsg_msix, 0,
1747 priv->msix[TSI721_VECT_IMB0_RCV + mbox].irq_name,
1748 (void *)mport);
1749
1750 if (rc) {
1751 dev_dbg(&priv->pdev->dev,
1752 "Unable to allocate MSI-X interrupt for "
1753 "IBOX%d-DONE\n", mbox);
1754 goto out_desc;
1755 }
1756
1757 rc = request_irq(priv->msix[TSI721_VECT_IMB0_INT + mbox].vector,
1758 tsi721_imsg_msix, 0,
1759 priv->msix[TSI721_VECT_IMB0_INT + mbox].irq_name,
1760 (void *)mport);
1761
1762 if (rc) {
1763 dev_dbg(&priv->pdev->dev,
1764 "Unable to allocate MSI-X interrupt for "
1765 "IBOX%d-INT\n", mbox);
1766 goto out_desc;
1767 }
1768 }
1769
1770 tsi721_imsg_interrupt_enable(priv, ch, TSI721_IBDMAC_INT_ALL);
1771
1772 /* Initialize Inbound Message Engine */
1773 iowrite32(TSI721_IBDMAC_CTL_INIT, priv->regs + TSI721_IBDMAC_CTL(ch));
1774 (void)ioread32(priv->regs + TSI721_IBDMAC_CTL(ch));
1775 udelay(10);
1776 priv->imsg_ring[mbox].fq_wrptr = entries - 1;
1777 iowrite32(entries - 1, priv->regs + TSI721_IBDMAC_FQWP(ch));
1778
1779 priv->imsg_init[mbox] = 1;
1780 return 0;
1781
1782 out_desc:
1783 dma_free_coherent(&priv->pdev->dev,
1784 priv->imsg_ring[mbox].size * sizeof(struct tsi721_imsg_desc),
1785 priv->imsg_ring[mbox].imd_base,
1786 priv->imsg_ring[mbox].imd_phys);
1787
1788 priv->imsg_ring[mbox].imd_base = NULL;
1789
1790 out_dma:
1791 dma_free_coherent(&priv->pdev->dev,
1792 priv->imsg_ring[mbox].size * 8,
1793 priv->imsg_ring[mbox].imfq_base,
1794 priv->imsg_ring[mbox].imfq_phys);
1795
1796 priv->imsg_ring[mbox].imfq_base = NULL;
1797
1798 out_buf:
1799 dma_free_coherent(&priv->pdev->dev,
1800 priv->imsg_ring[mbox].size * TSI721_MSG_BUFFER_SIZE,
1801 priv->imsg_ring[mbox].buf_base,
1802 priv->imsg_ring[mbox].buf_phys);
1803
1804 priv->imsg_ring[mbox].buf_base = NULL;
1805
1806 out:
1807 return rc;
1808 }
1809
1810 /**
1811 * tsi721_close_inb_mbox - Shut down Tsi721 inbound mailbox
1812 * @mport: Master port implementing the Inbound Messaging Engine
1813 * @mbox: Mailbox to close
1814 */
1815 static void tsi721_close_inb_mbox(struct rio_mport *mport, int mbox)
1816 {
1817 struct tsi721_device *priv = mport->priv;
1818 u32 rx_slot;
1819 int ch = mbox + 4;
1820
1821 if (!priv->imsg_init[mbox]) /* mbox isn't initialized yet */
1822 return;
1823 priv->imsg_init[mbox] = 0;
1824
1825 /* Disable Inbound Messaging Engine */
1826
1827 /* Disable Interrupts */
1828 tsi721_imsg_interrupt_disable(priv, ch, TSI721_OBDMAC_INT_MASK);
1829
1830 if (priv->flags & TSI721_USING_MSIX) {
1831 free_irq(priv->msix[TSI721_VECT_IMB0_RCV + mbox].vector,
1832 (void *)mport);
1833 free_irq(priv->msix[TSI721_VECT_IMB0_INT + mbox].vector,
1834 (void *)mport);
1835 }
1836
1837 /* Clear Inbound Buffer Queue */
1838 for (rx_slot = 0; rx_slot < priv->imsg_ring[mbox].size; rx_slot++)
1839 priv->imsg_ring[mbox].imq_base[rx_slot] = NULL;
1840
1841 /* Free memory allocated for message buffers */
1842 dma_free_coherent(&priv->pdev->dev,
1843 priv->imsg_ring[mbox].size * TSI721_MSG_BUFFER_SIZE,
1844 priv->imsg_ring[mbox].buf_base,
1845 priv->imsg_ring[mbox].buf_phys);
1846
1847 priv->imsg_ring[mbox].buf_base = NULL;
1848
1849 /* Free memory allocated for free pointr list */
1850 dma_free_coherent(&priv->pdev->dev,
1851 priv->imsg_ring[mbox].size * 8,
1852 priv->imsg_ring[mbox].imfq_base,
1853 priv->imsg_ring[mbox].imfq_phys);
1854
1855 priv->imsg_ring[mbox].imfq_base = NULL;
1856
1857 /* Free memory allocated for RX descriptors */
1858 dma_free_coherent(&priv->pdev->dev,
1859 priv->imsg_ring[mbox].size * sizeof(struct tsi721_imsg_desc),
1860 priv->imsg_ring[mbox].imd_base,
1861 priv->imsg_ring[mbox].imd_phys);
1862
1863 priv->imsg_ring[mbox].imd_base = NULL;
1864 }
1865
1866 /**
1867 * tsi721_add_inb_buffer - Add buffer to the Tsi721 inbound message queue
1868 * @mport: Master port implementing the Inbound Messaging Engine
1869 * @mbox: Inbound mailbox number
1870 * @buf: Buffer to add to inbound queue
1871 */
1872 static int tsi721_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
1873 {
1874 struct tsi721_device *priv = mport->priv;
1875 u32 rx_slot;
1876 int rc = 0;
1877
1878 rx_slot = priv->imsg_ring[mbox].rx_slot;
1879 if (priv->imsg_ring[mbox].imq_base[rx_slot]) {
1880 dev_err(&priv->pdev->dev,
1881 "Error adding inbound buffer %d, buffer exists\n",
1882 rx_slot);
1883 rc = -EINVAL;
1884 goto out;
1885 }
1886
1887 priv->imsg_ring[mbox].imq_base[rx_slot] = buf;
1888
1889 if (++priv->imsg_ring[mbox].rx_slot == priv->imsg_ring[mbox].size)
1890 priv->imsg_ring[mbox].rx_slot = 0;
1891
1892 out:
1893 return rc;
1894 }
1895
1896 /**
1897 * tsi721_get_inb_message - Fetch inbound message from the Tsi721 MSG Queue
1898 * @mport: Master port implementing the Inbound Messaging Engine
1899 * @mbox: Inbound mailbox number
1900 *
1901 * Returns pointer to the message on success or NULL on failure.
1902 */
1903 static void *tsi721_get_inb_message(struct rio_mport *mport, int mbox)
1904 {
1905 struct tsi721_device *priv = mport->priv;
1906 struct tsi721_imsg_desc *desc;
1907 u32 rx_slot;
1908 void *rx_virt = NULL;
1909 u64 rx_phys;
1910 void *buf = NULL;
1911 u64 *free_ptr;
1912 int ch = mbox + 4;
1913 int msg_size;
1914
1915 if (!priv->imsg_init[mbox])
1916 return NULL;
1917
1918 desc = priv->imsg_ring[mbox].imd_base;
1919 desc += priv->imsg_ring[mbox].desc_rdptr;
1920
1921 if (!(le32_to_cpu(desc->msg_info) & TSI721_IMD_HO))
1922 goto out;
1923
1924 rx_slot = priv->imsg_ring[mbox].rx_slot;
1925 while (priv->imsg_ring[mbox].imq_base[rx_slot] == NULL) {
1926 if (++rx_slot == priv->imsg_ring[mbox].size)
1927 rx_slot = 0;
1928 }
1929
1930 rx_phys = ((u64)le32_to_cpu(desc->bufptr_hi) << 32) |
1931 le32_to_cpu(desc->bufptr_lo);
1932
1933 rx_virt = priv->imsg_ring[mbox].buf_base +
1934 (rx_phys - (u64)priv->imsg_ring[mbox].buf_phys);
1935
1936 buf = priv->imsg_ring[mbox].imq_base[rx_slot];
1937 msg_size = le32_to_cpu(desc->msg_info) & TSI721_IMD_BCOUNT;
1938 if (msg_size == 0)
1939 msg_size = RIO_MAX_MSG_SIZE;
1940
1941 memcpy(buf, rx_virt, msg_size);
1942 priv->imsg_ring[mbox].imq_base[rx_slot] = NULL;
1943
1944 desc->msg_info &= cpu_to_le32(~TSI721_IMD_HO);
1945 if (++priv->imsg_ring[mbox].desc_rdptr == priv->imsg_ring[mbox].size)
1946 priv->imsg_ring[mbox].desc_rdptr = 0;
1947
1948 iowrite32(priv->imsg_ring[mbox].desc_rdptr,
1949 priv->regs + TSI721_IBDMAC_DQRP(ch));
1950
1951 /* Return free buffer into the pointer list */
1952 free_ptr = priv->imsg_ring[mbox].imfq_base;
1953 free_ptr[priv->imsg_ring[mbox].fq_wrptr] = cpu_to_le64(rx_phys);
1954
1955 if (++priv->imsg_ring[mbox].fq_wrptr == priv->imsg_ring[mbox].size)
1956 priv->imsg_ring[mbox].fq_wrptr = 0;
1957
1958 iowrite32(priv->imsg_ring[mbox].fq_wrptr,
1959 priv->regs + TSI721_IBDMAC_FQWP(ch));
1960 out:
1961 return buf;
1962 }
1963
1964 /**
1965 * tsi721_messages_init - Initialization of Messaging Engine
1966 * @priv: pointer to tsi721 private data
1967 *
1968 * Configures Tsi721 messaging engine.
1969 */
1970 static int tsi721_messages_init(struct tsi721_device *priv)
1971 {
1972 int ch;
1973
1974 iowrite32(0, priv->regs + TSI721_SMSG_ECC_LOG);
1975 iowrite32(0, priv->regs + TSI721_RETRY_GEN_CNT);
1976 iowrite32(0, priv->regs + TSI721_RETRY_RX_CNT);
1977
1978 /* Set SRIO Message Request/Response Timeout */
1979 iowrite32(TSI721_RQRPTO_VAL, priv->regs + TSI721_RQRPTO);
1980
1981 /* Initialize Inbound Messaging Engine Registers */
1982 for (ch = 0; ch < TSI721_IMSG_CHNUM; ch++) {
1983 /* Clear interrupt bits */
1984 iowrite32(TSI721_IBDMAC_INT_MASK,
1985 priv->regs + TSI721_IBDMAC_INT(ch));
1986 /* Clear Status */
1987 iowrite32(0, priv->regs + TSI721_IBDMAC_STS(ch));
1988
1989 iowrite32(TSI721_SMSG_ECC_COR_LOG_MASK,
1990 priv->regs + TSI721_SMSG_ECC_COR_LOG(ch));
1991 iowrite32(TSI721_SMSG_ECC_NCOR_MASK,
1992 priv->regs + TSI721_SMSG_ECC_NCOR(ch));
1993 }
1994
1995 return 0;
1996 }
1997
1998 /**
1999 * tsi721_disable_ints - disables all device interrupts
2000 * @priv: pointer to tsi721 private data
2001 */
2002 static void tsi721_disable_ints(struct tsi721_device *priv)
2003 {
2004 int ch;
2005
2006 /* Disable all device level interrupts */
2007 iowrite32(0, priv->regs + TSI721_DEV_INTE);
2008
2009 /* Disable all Device Channel interrupts */
2010 iowrite32(0, priv->regs + TSI721_DEV_CHAN_INTE);
2011
2012 /* Disable all Inbound Msg Channel interrupts */
2013 for (ch = 0; ch < TSI721_IMSG_CHNUM; ch++)
2014 iowrite32(0, priv->regs + TSI721_IBDMAC_INTE(ch));
2015
2016 /* Disable all Outbound Msg Channel interrupts */
2017 for (ch = 0; ch < TSI721_OMSG_CHNUM; ch++)
2018 iowrite32(0, priv->regs + TSI721_OBDMAC_INTE(ch));
2019
2020 /* Disable all general messaging interrupts */
2021 iowrite32(0, priv->regs + TSI721_SMSG_INTE);
2022
2023 /* Disable all BDMA Channel interrupts */
2024 for (ch = 0; ch < TSI721_DMA_MAXCH; ch++)
2025 iowrite32(0, priv->regs + TSI721_DMAC_INTE(ch));
2026
2027 /* Disable all general BDMA interrupts */
2028 iowrite32(0, priv->regs + TSI721_BDMA_INTE);
2029
2030 /* Disable all SRIO Channel interrupts */
2031 for (ch = 0; ch < TSI721_SRIO_MAXCH; ch++)
2032 iowrite32(0, priv->regs + TSI721_SR_CHINTE(ch));
2033
2034 /* Disable all general SR2PC interrupts */
2035 iowrite32(0, priv->regs + TSI721_SR2PC_GEN_INTE);
2036
2037 /* Disable all PC2SR interrupts */
2038 iowrite32(0, priv->regs + TSI721_PC2SR_INTE);
2039
2040 /* Disable all I2C interrupts */
2041 iowrite32(0, priv->regs + TSI721_I2C_INT_ENABLE);
2042
2043 /* Disable SRIO MAC interrupts */
2044 iowrite32(0, priv->regs + TSI721_RIO_EM_INT_ENABLE);
2045 iowrite32(0, priv->regs + TSI721_RIO_EM_DEV_INT_EN);
2046 }
2047
2048 /**
2049 * tsi721_setup_mport - Setup Tsi721 as RapidIO subsystem master port
2050 * @priv: pointer to tsi721 private data
2051 *
2052 * Configures Tsi721 as RapidIO master port.
2053 */
2054 static int __devinit tsi721_setup_mport(struct tsi721_device *priv)
2055 {
2056 struct pci_dev *pdev = priv->pdev;
2057 int err = 0;
2058 struct rio_ops *ops;
2059
2060 struct rio_mport *mport;
2061
2062 ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
2063 if (!ops) {
2064 dev_dbg(&pdev->dev, "Unable to allocate memory for rio_ops\n");
2065 return -ENOMEM;
2066 }
2067
2068 ops->lcread = tsi721_lcread;
2069 ops->lcwrite = tsi721_lcwrite;
2070 ops->cread = tsi721_cread_dma;
2071 ops->cwrite = tsi721_cwrite_dma;
2072 ops->dsend = tsi721_dsend;
2073 ops->open_inb_mbox = tsi721_open_inb_mbox;
2074 ops->close_inb_mbox = tsi721_close_inb_mbox;
2075 ops->open_outb_mbox = tsi721_open_outb_mbox;
2076 ops->close_outb_mbox = tsi721_close_outb_mbox;
2077 ops->add_outb_message = tsi721_add_outb_message;
2078 ops->add_inb_buffer = tsi721_add_inb_buffer;
2079 ops->get_inb_message = tsi721_get_inb_message;
2080
2081 mport = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
2082 if (!mport) {
2083 kfree(ops);
2084 dev_dbg(&pdev->dev, "Unable to allocate memory for mport\n");
2085 return -ENOMEM;
2086 }
2087
2088 mport->ops = ops;
2089 mport->index = 0;
2090 mport->sys_size = 0; /* small system */
2091 mport->phy_type = RIO_PHY_SERIAL;
2092 mport->priv = (void *)priv;
2093 mport->phys_efptr = 0x100;
2094
2095 INIT_LIST_HEAD(&mport->dbells);
2096
2097 rio_init_dbell_res(&mport->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
2098 rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
2099 rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
2100 strcpy(mport->name, "Tsi721 mport");
2101
2102 /* Hook up interrupt handler */
2103
2104 if (!tsi721_enable_msix(priv))
2105 priv->flags |= TSI721_USING_MSIX;
2106 else if (!pci_enable_msi(pdev))
2107 priv->flags |= TSI721_USING_MSI;
2108 else
2109 dev_info(&pdev->dev,
2110 "MSI/MSI-X is not available. Using legacy INTx.\n");
2111
2112 err = tsi721_request_irq(mport);
2113
2114 if (!err) {
2115 tsi721_interrupts_init(priv);
2116 ops->pwenable = tsi721_pw_enable;
2117 } else
2118 dev_err(&pdev->dev, "Unable to get assigned PCI IRQ "
2119 "vector %02X err=0x%x\n", pdev->irq, err);
2120
2121 /* Enable SRIO link */
2122 iowrite32(ioread32(priv->regs + TSI721_DEVCTL) |
2123 TSI721_DEVCTL_SRBOOT_CMPL,
2124 priv->regs + TSI721_DEVCTL);
2125
2126 rio_register_mport(mport);
2127 priv->mport = mport;
2128
2129 if (mport->host_deviceid >= 0)
2130 iowrite32(RIO_PORT_GEN_HOST | RIO_PORT_GEN_MASTER |
2131 RIO_PORT_GEN_DISCOVERED,
2132 priv->regs + (0x100 + RIO_PORT_GEN_CTL_CSR));
2133 else
2134 iowrite32(0, priv->regs + (0x100 + RIO_PORT_GEN_CTL_CSR));
2135
2136 return 0;
2137 }
2138
2139 static int __devinit tsi721_probe(struct pci_dev *pdev,
2140 const struct pci_device_id *id)
2141 {
2142 struct tsi721_device *priv;
2143 int i;
2144 int err;
2145 u32 regval;
2146
2147 priv = kzalloc(sizeof(struct tsi721_device), GFP_KERNEL);
2148 if (priv == NULL) {
2149 dev_err(&pdev->dev, "Failed to allocate memory for device\n");
2150 err = -ENOMEM;
2151 goto err_exit;
2152 }
2153
2154 err = pci_enable_device(pdev);
2155 if (err) {
2156 dev_err(&pdev->dev, "Failed to enable PCI device\n");
2157 goto err_clean;
2158 }
2159
2160 priv->pdev = pdev;
2161
2162 #ifdef DEBUG
2163 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
2164 dev_dbg(&pdev->dev, "res[%d] @ 0x%llx (0x%lx, 0x%lx)\n",
2165 i, (unsigned long long)pci_resource_start(pdev, i),
2166 (unsigned long)pci_resource_len(pdev, i),
2167 pci_resource_flags(pdev, i));
2168 }
2169 #endif
2170 /*
2171 * Verify BAR configuration
2172 */
2173
2174 /* BAR_0 (registers) must be 512KB+ in 32-bit address space */
2175 if (!(pci_resource_flags(pdev, BAR_0) & IORESOURCE_MEM) ||
2176 pci_resource_flags(pdev, BAR_0) & IORESOURCE_MEM_64 ||
2177 pci_resource_len(pdev, BAR_0) < TSI721_REG_SPACE_SIZE) {
2178 dev_err(&pdev->dev,
2179 "Missing or misconfigured CSR BAR0, aborting.\n");
2180 err = -ENODEV;
2181 goto err_disable_pdev;
2182 }
2183
2184 /* BAR_1 (outbound doorbells) must be 16MB+ in 32-bit address space */
2185 if (!(pci_resource_flags(pdev, BAR_1) & IORESOURCE_MEM) ||
2186 pci_resource_flags(pdev, BAR_1) & IORESOURCE_MEM_64 ||
2187 pci_resource_len(pdev, BAR_1) < TSI721_DB_WIN_SIZE) {
2188 dev_err(&pdev->dev,
2189 "Missing or misconfigured Doorbell BAR1, aborting.\n");
2190 err = -ENODEV;
2191 goto err_disable_pdev;
2192 }
2193
2194 /*
2195 * BAR_2 and BAR_4 (outbound translation) must be in 64-bit PCIe address
2196 * space.
2197 * NOTE: BAR_2 and BAR_4 are not used by this version of driver.
2198 * It may be a good idea to keep them disabled using HW configuration
2199 * to save PCI memory space.
2200 */
2201 if ((pci_resource_flags(pdev, BAR_2) & IORESOURCE_MEM) &&
2202 (pci_resource_flags(pdev, BAR_2) & IORESOURCE_MEM_64)) {
2203 dev_info(&pdev->dev, "Outbound BAR2 is not used but enabled.\n");
2204 }
2205
2206 if ((pci_resource_flags(pdev, BAR_4) & IORESOURCE_MEM) &&
2207 (pci_resource_flags(pdev, BAR_4) & IORESOURCE_MEM_64)) {
2208 dev_info(&pdev->dev, "Outbound BAR4 is not used but enabled.\n");
2209 }
2210
2211 err = pci_request_regions(pdev, DRV_NAME);
2212 if (err) {
2213 dev_err(&pdev->dev, "Cannot obtain PCI resources, "
2214 "aborting.\n");
2215 goto err_disable_pdev;
2216 }
2217
2218 pci_set_master(pdev);
2219
2220 priv->regs = pci_ioremap_bar(pdev, BAR_0);
2221 if (!priv->regs) {
2222 dev_err(&pdev->dev,
2223 "Unable to map device registers space, aborting\n");
2224 err = -ENOMEM;
2225 goto err_free_res;
2226 }
2227
2228 priv->odb_base = pci_ioremap_bar(pdev, BAR_1);
2229 if (!priv->odb_base) {
2230 dev_err(&pdev->dev,
2231 "Unable to map outbound doorbells space, aborting\n");
2232 err = -ENOMEM;
2233 goto err_unmap_bars;
2234 }
2235
2236 /* Configure DMA attributes. */
2237 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2238 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
2239 dev_info(&pdev->dev, "Unable to set DMA mask\n");
2240 goto err_unmap_bars;
2241 }
2242
2243 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2244 dev_info(&pdev->dev, "Unable to set consistent DMA mask\n");
2245 } else {
2246 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2247 if (err)
2248 dev_info(&pdev->dev, "Unable to set consistent DMA mask\n");
2249 }
2250
2251 /* Clear "no snoop" and "relaxed ordering" bits. */
2252 pci_read_config_dword(pdev, 0x40 + PCI_EXP_DEVCTL, &regval);
2253 regval &= ~(PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN);
2254 pci_write_config_dword(pdev, 0x40 + PCI_EXP_DEVCTL, regval);
2255
2256 /*
2257 * FIXUP: correct offsets of MSI-X tables in the MSI-X Capability Block
2258 */
2259 pci_write_config_dword(pdev, TSI721_PCIECFG_EPCTL, 0x01);
2260 pci_write_config_dword(pdev, TSI721_PCIECFG_MSIXTBL,
2261 TSI721_MSIXTBL_OFFSET);
2262 pci_write_config_dword(pdev, TSI721_PCIECFG_MSIXPBA,
2263 TSI721_MSIXPBA_OFFSET);
2264 pci_write_config_dword(pdev, TSI721_PCIECFG_EPCTL, 0);
2265 /* End of FIXUP */
2266
2267 tsi721_disable_ints(priv);
2268
2269 tsi721_init_pc2sr_mapping(priv);
2270 tsi721_init_sr2pc_mapping(priv);
2271
2272 if (tsi721_bdma_init(priv)) {
2273 dev_err(&pdev->dev, "BDMA initialization failed, aborting\n");
2274 err = -ENOMEM;
2275 goto err_unmap_bars;
2276 }
2277
2278 err = tsi721_doorbell_init(priv);
2279 if (err)
2280 goto err_free_bdma;
2281
2282 tsi721_port_write_init(priv);
2283
2284 err = tsi721_messages_init(priv);
2285 if (err)
2286 goto err_free_consistent;
2287
2288 err = tsi721_setup_mport(priv);
2289 if (err)
2290 goto err_free_consistent;
2291
2292 return 0;
2293
2294 err_free_consistent:
2295 tsi721_doorbell_free(priv);
2296 err_free_bdma:
2297 tsi721_bdma_free(priv);
2298 err_unmap_bars:
2299 if (priv->regs)
2300 iounmap(priv->regs);
2301 if (priv->odb_base)
2302 iounmap(priv->odb_base);
2303 err_free_res:
2304 pci_release_regions(pdev);
2305 pci_clear_master(pdev);
2306 err_disable_pdev:
2307 pci_disable_device(pdev);
2308 err_clean:
2309 kfree(priv);
2310 err_exit:
2311 return err;
2312 }
2313
2314 static DEFINE_PCI_DEVICE_TABLE(tsi721_pci_tbl) = {
2315 { PCI_DEVICE(PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_TSI721) },
2316 { 0, } /* terminate list */
2317 };
2318
2319 MODULE_DEVICE_TABLE(pci, tsi721_pci_tbl);
2320
2321 static struct pci_driver tsi721_driver = {
2322 .name = "tsi721",
2323 .id_table = tsi721_pci_tbl,
2324 .probe = tsi721_probe,
2325 };
2326
2327 static int __init tsi721_init(void)
2328 {
2329 return pci_register_driver(&tsi721_driver);
2330 }
2331
2332 static void __exit tsi721_exit(void)
2333 {
2334 pci_unregister_driver(&tsi721_driver);
2335 }
2336
2337 device_initcall(tsi721_init);
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