drivers/pci/msi.c

   1 /*
   2  * File:        msi.c
   3  * Purpose:     PCI Message Signaled Interrupt (MSI)
   4  *
   5  * Copyright (C) 2003-2004 Intel
   6  * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
   7  */
   8
   9 #include <linux/err.h>
  10 #include <linux/mm.h>
  11 #include <linux/irq.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/init.h>
  14 #include <linux/ioport.h>
  15 #include <linux/pci.h>
  16 #include <linux/proc_fs.h>
  17 #include <linux/msi.h>
  18 #include <linux/smp.h>
  19 #include <linux/errno.h>
  20 #include <linux/io.h>
  21 #include <linux/slab.h>
  22
  23 #include "pci.h"
  24 #include "msi.h"
  25
  26 static int pci_msi_enable = 1;
  27
  28 /* Arch hooks */
  29
  30 #ifndef arch_msi_check_device
  31 int arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
  32 {
  33         return 0;
  34 }
  35 #endif
  36
  37 #ifndef arch_setup_msi_irqs
  38 # define arch_setup_msi_irqs default_setup_msi_irqs
  39 # define HAVE_DEFAULT_MSI_SETUP_IRQS
  40 #endif
  41
  42 #ifdef HAVE_DEFAULT_MSI_SETUP_IRQS
  43 int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
  44 {
  45         struct msi_desc *entry;
  46         int ret;
  47
  48         /*
  49          * If an architecture wants to support multiple MSI, it needs to
  50          * override arch_setup_msi_irqs()
  51          */
  52         if (type == PCI_CAP_ID_MSI && nvec > 1)
  53                 return 1;
  54
  55         list_for_each_entry(entry, &dev->msi_list, list) {
  56                 ret = arch_setup_msi_irq(dev, entry);
  57                 if (ret < 0)
  58                         return ret;
  59                 if (ret > 0)
  60                         return -ENOSPC;
  61         }
  62
  63         return 0;
  64 }
  65 #endif
  66
  67 #ifndef arch_teardown_msi_irqs
  68 # define arch_teardown_msi_irqs default_teardown_msi_irqs
  69 # define HAVE_DEFAULT_MSI_TEARDOWN_IRQS
  70 #endif
  71
  72 #ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS
  73 void default_teardown_msi_irqs(struct pci_dev *dev)
  74 {
  75         struct msi_desc *entry;
  76
  77         list_for_each_entry(entry, &dev->msi_list, list) {
  78                 int i, nvec;
  79                 if (entry->irq == 0)
  80                         continue;
  81                 nvec = 1 << entry->msi_attrib.multiple;
  82                 for (i = 0; i < nvec; i++)
  83                         arch_teardown_msi_irq(entry->irq + i);
  84         }
  85 }
  86 #endif
  87
  88 static void msi_set_enable(struct pci_dev *dev, int pos, int enable)
  89 {
  90         u16 control;
  91
  92         BUG_ON(!pos);
  93
  94         pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
  95         control &= ~PCI_MSI_FLAGS_ENABLE;
  96         if (enable)
  97                 control |= PCI_MSI_FLAGS_ENABLE;
  98         pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
  99 }
 100
 101 static void msix_set_enable(struct pci_dev *dev, int enable)
 102 {
 103         int pos;
 104         u16 control;
 105
 106         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 107         if (pos) {
 108                 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
 109                 control &= ~PCI_MSIX_FLAGS_ENABLE;
 110                 if (enable)
 111                         control |= PCI_MSIX_FLAGS_ENABLE;
 112                 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 113         }
 114 }
 115
 116 static inline __attribute_const__ u32 msi_mask(unsigned x)
 117 {
 118         /* Don't shift by >= width of type */
 119         if (x >= 5)
 120                 return 0xffffffff;
 121         return (1 << (1 << x)) - 1;
 122 }
 123
 124 static inline __attribute_const__ u32 msi_capable_mask(u16 control)
 125 {
 126         return msi_mask((control >> 1) & 7);
 127 }
 128
 129 static inline __attribute_const__ u32 msi_enabled_mask(u16 control)
 130 {
 131         return msi_mask((control >> 4) & 7);
 132 }
 133
 134 /*
 135  * PCI 2.3 does not specify mask bits for each MSI interrupt.  Attempting to
 136  * mask all MSI interrupts by clearing the MSI enable bit does not work
 137  * reliably as devices without an INTx disable bit will then generate a
 138  * level IRQ which will never be cleared.
 139  */
 140 static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
 141 {
 142         u32 mask_bits = desc->masked;
 143
 144         if (!desc->msi_attrib.maskbit)
 145                 return 0;
 146
 147         mask_bits &= ~mask;
 148         mask_bits |= flag;
 149         pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
 150
 151         return mask_bits;
 152 }
 153
 154 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
 155 {
 156         desc->masked = __msi_mask_irq(desc, mask, flag);
 157 }
 158
 159 /*
 160  * This internal function does not flush PCI writes to the device.
 161  * All users must ensure that they read from the device before either
 162  * assuming that the device state is up to date, or returning out of this
 163  * file.  This saves a few milliseconds when initialising devices with lots
 164  * of MSI-X interrupts.
 165  */
 166 static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag)
 167 {
 168         u32 mask_bits = desc->masked;
 169         unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
 170                                                 PCI_MSIX_ENTRY_VECTOR_CTRL;
 171         mask_bits &= ~1;
 172         mask_bits |= flag;
 173         writel(mask_bits, desc->mask_base + offset);
 174
 175         return mask_bits;
 176 }
 177
 178 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
 179 {
 180         desc->masked = __msix_mask_irq(desc, flag);
 181 }
 182
 183 static void msi_set_mask_bit(struct irq_data *data, u32 flag)
 184 {
 185         struct msi_desc *desc = irq_data_get_msi(data);
 186
 187         if (desc->msi_attrib.is_msix) {
 188                 msix_mask_irq(desc, flag);
 189                 readl(desc->mask_base);         /* Flush write to device */
 190         } else {
 191                 unsigned offset = data->irq - desc->dev->irq;
 192                 msi_mask_irq(desc, 1 << offset, flag << offset);
 193         }
 194 }
 195
 196 void mask_msi_irq(struct irq_data *data)
 197 {
 198         msi_set_mask_bit(data, 1);
 199 }
 200
 201 void unmask_msi_irq(struct irq_data *data)
 202 {
 203         msi_set_mask_bit(data, 0);
 204 }
 205
 206 void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
 207 {
 208         BUG_ON(entry->dev->current_state != PCI_D0);
 209
 210         if (entry->msi_attrib.is_msix) {
 211                 void __iomem *base = entry->mask_base +
 212                         entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
 213
 214                 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
 215                 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
 216                 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
 217         } else {
 218                 struct pci_dev *dev = entry->dev;
 219                 int pos = entry->msi_attrib.pos;
 220                 u16 data;
 221
 222                 pci_read_config_dword(dev, msi_lower_address_reg(pos),
 223                                         &msg->address_lo);
 224                 if (entry->msi_attrib.is_64) {
 225                         pci_read_config_dword(dev, msi_upper_address_reg(pos),
 226                                                 &msg->address_hi);
 227                         pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
 228                 } else {
 229                         msg->address_hi = 0;
 230                         pci_read_config_word(dev, msi_data_reg(pos, 0), &data);
 231                 }
 232                 msg->data = data;
 233         }
 234 }
 235
 236 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
 237 {
 238         struct msi_desc *entry = get_irq_msi(irq);
 239
 240         __read_msi_msg(entry, msg);
 241 }
 242
 243 void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
 244 {
 245         /* Assert that the cache is valid, assuming that
 246          * valid messages are not all-zeroes. */
 247         BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo |
 248                  entry->msg.data));
 249
 250         *msg = entry->msg;
 251 }
 252
 253 void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
 254 {
 255         struct msi_desc *entry = get_irq_msi(irq);
 256
 257         __get_cached_msi_msg(entry, msg);
 258 }
 259
 260 void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
 261 {
 262         if (entry->dev->current_state != PCI_D0) {
 263                 /* Don't touch the hardware now */
 264         } else if (entry->msi_attrib.is_msix) {
 265                 void __iomem *base;
 266                 base = entry->mask_base +
 267                         entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
 268
 269                 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
 270                 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
 271                 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
 272         } else {
 273                 struct pci_dev *dev = entry->dev;
 274                 int pos = entry->msi_attrib.pos;
 275                 u16 msgctl;
 276
 277                 pci_read_config_word(dev, msi_control_reg(pos), &msgctl);
 278                 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
 279                 msgctl |= entry->msi_attrib.multiple << 4;
 280                 pci_write_config_word(dev, msi_control_reg(pos), msgctl);
 281
 282                 pci_write_config_dword(dev, msi_lower_address_reg(pos),
 283                                         msg->address_lo);
 284                 if (entry->msi_attrib.is_64) {
 285                         pci_write_config_dword(dev, msi_upper_address_reg(pos),
 286                                                 msg->address_hi);
 287                         pci_write_config_word(dev, msi_data_reg(pos, 1),
 288                                                 msg->data);
 289                 } else {
 290                         pci_write_config_word(dev, msi_data_reg(pos, 0),
 291                                                 msg->data);
 292                 }
 293         }
 294         entry->msg = *msg;
 295 }
 296
 297 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
 298 {
 299         struct msi_desc *entry = get_irq_msi(irq);
 300
 301         __write_msi_msg(entry, msg);
 302 }
 303
 304 static void free_msi_irqs(struct pci_dev *dev)
 305 {
 306         struct msi_desc *entry, *tmp;
 307
 308         list_for_each_entry(entry, &dev->msi_list, list) {
 309                 int i, nvec;
 310                 if (!entry->irq)
 311                         continue;
 312                 nvec = 1 << entry->msi_attrib.multiple;
 313                 for (i = 0; i < nvec; i++)
 314                         BUG_ON(irq_has_action(entry->irq + i));
 315         }
 316
 317         arch_teardown_msi_irqs(dev);
 318
 319         list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
 320                 if (entry->msi_attrib.is_msix) {
 321                         if (list_is_last(&entry->list, &dev->msi_list))
 322                                 iounmap(entry->mask_base);
 323                 }
 324                 list_del(&entry->list);
 325                 kfree(entry);
 326         }
 327 }
 328
 329 static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
 330 {
 331         struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
 332         if (!desc)
 333                 return NULL;
 334
 335         INIT_LIST_HEAD(&desc->list);
 336         desc->dev = dev;
 337
 338         return desc;
 339 }
 340
 341 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
 342 {
 343         if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
 344                 pci_intx(dev, enable);
 345 }
 346
 347 static void __pci_restore_msi_state(struct pci_dev *dev)
 348 {
 349         int pos;
 350         u16 control;
 351         struct msi_desc *entry;
 352
 353         if (!dev->msi_enabled)
 354                 return;
 355
 356         entry = get_irq_msi(dev->irq);
 357         pos = entry->msi_attrib.pos;
 358
 359         pci_intx_for_msi(dev, 0);
 360         msi_set_enable(dev, pos, 0);
 361         write_msi_msg(dev->irq, &entry->msg);
 362
 363         pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
 364         msi_mask_irq(entry, msi_capable_mask(control), entry->masked);
 365         control &= ~PCI_MSI_FLAGS_QSIZE;
 366         control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
 367         pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
 368 }
 369
 370 static void __pci_restore_msix_state(struct pci_dev *dev)
 371 {
 372         int pos;
 373         struct msi_desc *entry;
 374         u16 control;
 375
 376         if (!dev->msix_enabled)
 377                 return;
 378         BUG_ON(list_empty(&dev->msi_list));
 379         entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
 380         pos = entry->msi_attrib.pos;
 381         pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
 382
 383         /* route the table */
 384         pci_intx_for_msi(dev, 0);
 385         control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL;
 386         pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 387
 388         list_for_each_entry(entry, &dev->msi_list, list) {
 389                 write_msi_msg(entry->irq, &entry->msg);
 390                 msix_mask_irq(entry, entry->masked);
 391         }
 392
 393         control &= ~PCI_MSIX_FLAGS_MASKALL;
 394         pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 395 }
 396
 397 void pci_restore_msi_state(struct pci_dev *dev)
 398 {
 399         __pci_restore_msi_state(dev);
 400         __pci_restore_msix_state(dev);
 401 }
 402 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
 403
 404 /**
 405  * msi_capability_init - configure device's MSI capability structure
 406  * @dev: pointer to the pci_dev data structure of MSI device function
 407  * @nvec: number of interrupts to allocate
 408  *
 409  * Setup the MSI capability structure of the device with the requested
 410  * number of interrupts.  A return value of zero indicates the successful
 411  * setup of an entry with the new MSI irq.  A negative return value indicates
 412  * an error, and a positive return value indicates the number of interrupts
 413  * which could have been allocated.
 414  */
 415 static int msi_capability_init(struct pci_dev *dev, int nvec)
 416 {
 417         struct msi_desc *entry;
 418         int pos, ret;
 419         u16 control;
 420         unsigned mask;
 421
 422         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 423         msi_set_enable(dev, pos, 0);    /* Disable MSI during set up */
 424
 425         pci_read_config_word(dev, msi_control_reg(pos), &control);
 426         /* MSI Entry Initialization */
 427         entry = alloc_msi_entry(dev);
 428         if (!entry)
 429                 return -ENOMEM;
 430
 431         entry->msi_attrib.is_msix       = 0;
 432         entry->msi_attrib.is_64         = is_64bit_address(control);
 433         entry->msi_attrib.entry_nr      = 0;
 434         entry->msi_attrib.maskbit       = is_mask_bit_support(control);
 435         entry->msi_attrib.default_irq   = dev->irq;     /* Save IOAPIC IRQ */
 436         entry->msi_attrib.pos           = pos;
 437
 438         entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64);
 439         /* All MSIs are unmasked by default, Mask them all */
 440         if (entry->msi_attrib.maskbit)
 441                 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
 442         mask = msi_capable_mask(control);
 443         msi_mask_irq(entry, mask, mask);
 444
 445         list_add_tail(&entry->list, &dev->msi_list);
 446
 447         /* Configure MSI capability structure */
 448         ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
 449         if (ret) {
 450                 msi_mask_irq(entry, mask, ~mask);
 451                 free_msi_irqs(dev);
 452                 return ret;
 453         }
 454
 455         /* Set MSI enabled bits  */
 456         pci_intx_for_msi(dev, 0);
 457         msi_set_enable(dev, pos, 1);
 458         dev->msi_enabled = 1;
 459
 460         dev->irq = entry->irq;
 461         return 0;
 462 }
 463
 464 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned pos,
 465                                                         unsigned nr_entries)
 466 {
 467         resource_size_t phys_addr;
 468         u32 table_offset;
 469         u8 bir;
 470
 471         pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
 472         bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
 473         table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
 474         phys_addr = pci_resource_start(dev, bir) + table_offset;
 475
 476         return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
 477 }
 478
 479 static int msix_setup_entries(struct pci_dev *dev, unsigned pos,
 480                                 void __iomem *base, struct msix_entry *entries,
 481                                 int nvec)
 482 {
 483         struct msi_desc *entry;
 484         int i;
 485
 486         for (i = 0; i < nvec; i++) {
 487                 entry = alloc_msi_entry(dev);
 488                 if (!entry) {
 489                         if (!i)
 490                                 iounmap(base);
 491                         else
 492                                 free_msi_irqs(dev);
 493                         /* No enough memory. Don't try again */
 494                         return -ENOMEM;
 495                 }
 496
 497                 entry->msi_attrib.is_msix       = 1;
 498                 entry->msi_attrib.is_64         = 1;
 499                 entry->msi_attrib.entry_nr      = entries[i].entry;
 500                 entry->msi_attrib.default_irq   = dev->irq;
 501                 entry->msi_attrib.pos           = pos;
 502                 entry->mask_base                = base;
 503
 504                 list_add_tail(&entry->list, &dev->msi_list);
 505         }
 506
 507         return 0;
 508 }
 509
 510 static void msix_program_entries(struct pci_dev *dev,
 511                                         struct msix_entry *entries)
 512 {
 513         struct msi_desc *entry;
 514         int i = 0;
 515
 516         list_for_each_entry(entry, &dev->msi_list, list) {
 517                 int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
 518                                                 PCI_MSIX_ENTRY_VECTOR_CTRL;
 519
 520                 entries[i].vector = entry->irq;
 521                 set_irq_msi(entry->irq, entry);
 522                 entry->masked = readl(entry->mask_base + offset);
 523                 msix_mask_irq(entry, 1);
 524                 i++;
 525         }
 526 }
 527
 528 /**
 529  * msix_capability_init - configure device's MSI-X capability
 530  * @dev: pointer to the pci_dev data structure of MSI-X device function
 531  * @entries: pointer to an array of struct msix_entry entries
 532  * @nvec: number of @entries
 533  *
 534  * Setup the MSI-X capability structure of device function with a
 535  * single MSI-X irq. A return of zero indicates the successful setup of
 536  * requested MSI-X entries with allocated irqs or non-zero for otherwise.
 537  **/
 538 static int msix_capability_init(struct pci_dev *dev,
 539                                 struct msix_entry *entries, int nvec)
 540 {
 541         int pos, ret;
 542         u16 control;
 543         void __iomem *base;
 544
 545         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 546         pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
 547
 548         /* Ensure MSI-X is disabled while it is set up */
 549         control &= ~PCI_MSIX_FLAGS_ENABLE;
 550         pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 551
 552         /* Request & Map MSI-X table region */
 553         base = msix_map_region(dev, pos, multi_msix_capable(control));
 554         if (!base)
 555                 return -ENOMEM;
 556
 557         ret = msix_setup_entries(dev, pos, base, entries, nvec);
 558         if (ret)
 559                 return ret;
 560
 561         ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
 562         if (ret)
 563                 goto error;
 564
 565         /*
 566          * Some devices require MSI-X to be enabled before we can touch the
 567          * MSI-X registers.  We need to mask all the vectors to prevent
 568          * interrupts coming in before they're fully set up.
 569          */
 570         control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE;
 571         pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 572
 573         msix_program_entries(dev, entries);
 574
 575         /* Set MSI-X enabled bits and unmask the function */
 576         pci_intx_for_msi(dev, 0);
 577         dev->msix_enabled = 1;
 578
 579         control &= ~PCI_MSIX_FLAGS_MASKALL;
 580         pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 581
 582         return 0;
 583
 584 error:
 585         if (ret < 0) {
 586                 /*
 587                  * If we had some success, report the number of irqs
 588                  * we succeeded in setting up.
 589                  */
 590                 struct msi_desc *entry;
 591                 int avail = 0;
 592
 593                 list_for_each_entry(entry, &dev->msi_list, list) {
 594                         if (entry->irq != 0)
 595                                 avail++;
 596                 }
 597                 if (avail != 0)
 598                         ret = avail;
 599         }
 600
 601         free_msi_irqs(dev);
 602
 603         return ret;
 604 }
 605
 606 /**
 607  * pci_msi_check_device - check whether MSI may be enabled on a device
 608  * @dev: pointer to the pci_dev data structure of MSI device function
 609  * @nvec: how many MSIs have been requested ?
 610  * @type: are we checking for MSI or MSI-X ?
 611  *
 612  * Look at global flags, the device itself, and its parent busses
 613  * to determine if MSI/-X are supported for the device. If MSI/-X is
 614  * supported return 0, else return an error code.
 615  **/
 616 static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type)
 617 {
 618         struct pci_bus *bus;
 619         int ret;
 620
 621         /* MSI must be globally enabled and supported by the device */
 622         if (!pci_msi_enable || !dev || dev->no_msi)
 623                 return -EINVAL;
 624
 625         /*
 626          * You can't ask to have 0 or less MSIs configured.
 627          *  a) it's stupid ..
 628          *  b) the list manipulation code assumes nvec >= 1.
 629          */
 630         if (nvec < 1)
 631                 return -ERANGE;
 632
 633         /*
 634          * Any bridge which does NOT route MSI transactions from its
 635          * secondary bus to its primary bus must set NO_MSI flag on
 636          * the secondary pci_bus.
 637          * We expect only arch-specific PCI host bus controller driver
 638          * or quirks for specific PCI bridges to be setting NO_MSI.
 639          */
 640         for (bus = dev->bus; bus; bus = bus->parent)
 641                 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
 642                         return -EINVAL;
 643
 644         ret = arch_msi_check_device(dev, nvec, type);
 645         if (ret)
 646                 return ret;
 647
 648         if (!pci_find_capability(dev, type))
 649                 return -EINVAL;
 650
 651         return 0;
 652 }
 653
 654 /**
 655  * pci_enable_msi_block - configure device's MSI capability structure
 656  * @dev: device to configure
 657  * @nvec: number of interrupts to configure
 658  *
 659  * Allocate IRQs for a device with the MSI capability.
 660  * This function returns a negative errno if an error occurs.  If it
 661  * is unable to allocate the number of interrupts requested, it returns
 662  * the number of interrupts it might be able to allocate.  If it successfully
 663  * allocates at least the number of interrupts requested, it returns 0 and
 664  * updates the @dev's irq member to the lowest new interrupt number; the
 665  * other interrupt numbers allocated to this device are consecutive.
 666  */
 667 int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
 668 {
 669         int status, pos, maxvec;
 670         u16 msgctl;
 671
 672         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 673         if (!pos)
 674                 return -EINVAL;
 675         pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
 676         maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
 677         if (nvec > maxvec)
 678                 return maxvec;
 679
 680         status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI);
 681         if (status)
 682                 return status;
 683
 684         WARN_ON(!!dev->msi_enabled);
 685
 686         /* Check whether driver already requested MSI-X irqs */
 687         if (dev->msix_enabled) {
 688                 dev_info(&dev->dev, "can't enable MSI "
 689                          "(MSI-X already enabled)\n");
 690                 return -EINVAL;
 691         }
 692
 693         status = msi_capability_init(dev, nvec);
 694         return status;
 695 }
 696 EXPORT_SYMBOL(pci_enable_msi_block);
 697
 698 void pci_msi_shutdown(struct pci_dev *dev)
 699 {
 700         struct msi_desc *desc;
 701         u32 mask;
 702         u16 ctrl;
 703         unsigned pos;
 704
 705         if (!pci_msi_enable || !dev || !dev->msi_enabled)
 706                 return;
 707
 708         BUG_ON(list_empty(&dev->msi_list));
 709         desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
 710         pos = desc->msi_attrib.pos;
 711
 712         msi_set_enable(dev, pos, 0);
 713         pci_intx_for_msi(dev, 1);
 714         dev->msi_enabled = 0;
 715
 716         /* Return the device with MSI unmasked as initial states */
 717         pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl);
 718         mask = msi_capable_mask(ctrl);
 719         /* Keep cached state to be restored */
 720         __msi_mask_irq(desc, mask, ~mask);
 721
 722         /* Restore dev->irq to its default pin-assertion irq */
 723         dev->irq = desc->msi_attrib.default_irq;
 724 }
 725
 726 void pci_disable_msi(struct pci_dev *dev)
 727 {
 728         if (!pci_msi_enable || !dev || !dev->msi_enabled)
 729                 return;
 730
 731         pci_msi_shutdown(dev);
 732         free_msi_irqs(dev);
 733 }
 734 EXPORT_SYMBOL(pci_disable_msi);
 735
 736 /**
 737  * pci_msix_table_size - return the number of device's MSI-X table entries
 738  * @dev: pointer to the pci_dev data structure of MSI-X device function
 739  */
 740 int pci_msix_table_size(struct pci_dev *dev)
 741 {
 742         int pos;
 743         u16 control;
 744
 745         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 746         if (!pos)
 747                 return 0;
 748
 749         pci_read_config_word(dev, msi_control_reg(pos), &control);
 750         return multi_msix_capable(control);
 751 }
 752
 753 /**
 754  * pci_enable_msix - configure device's MSI-X capability structure
 755  * @dev: pointer to the pci_dev data structure of MSI-X device function
 756  * @entries: pointer to an array of MSI-X entries
 757  * @nvec: number of MSI-X irqs requested for allocation by device driver
 758  *
 759  * Setup the MSI-X capability structure of device function with the number
 760  * of requested irqs upon its software driver call to request for
 761  * MSI-X mode enabled on its hardware device function. A return of zero
 762  * indicates the successful configuration of MSI-X capability structure
 763  * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
 764  * Or a return of > 0 indicates that driver request is exceeding the number
 765  * of irqs or MSI-X vectors available. Driver should use the returned value to
 766  * re-send its request.
 767  **/
 768 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
 769 {
 770         int status, nr_entries;
 771         int i, j;
 772
 773         if (!entries)
 774                 return -EINVAL;
 775
 776         status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX);
 777         if (status)
 778                 return status;
 779
 780         nr_entries = pci_msix_table_size(dev);
 781         if (nvec > nr_entries)
 782                 return nr_entries;
 783
 784         /* Check for any invalid entries */
 785         for (i = 0; i < nvec; i++) {
 786                 if (entries[i].entry >= nr_entries)
 787                         return -EINVAL;         /* invalid entry */
 788                 for (j = i + 1; j < nvec; j++) {
 789                         if (entries[i].entry == entries[j].entry)
 790                                 return -EINVAL; /* duplicate entry */
 791                 }
 792         }
 793         WARN_ON(!!dev->msix_enabled);
 794
 795         /* Check whether driver already requested for MSI irq */
 796         if (dev->msi_enabled) {
 797                 dev_info(&dev->dev, "can't enable MSI-X "
 798                        "(MSI IRQ already assigned)\n");
 799                 return -EINVAL;
 800         }
 801         status = msix_capability_init(dev, entries, nvec);
 802         return status;
 803 }
 804 EXPORT_SYMBOL(pci_enable_msix);
 805
 806 void pci_msix_shutdown(struct pci_dev *dev)
 807 {
 808         struct msi_desc *entry;
 809
 810         if (!pci_msi_enable || !dev || !dev->msix_enabled)
 811                 return;
 812
 813         /* Return the device with MSI-X masked as initial states */
 814         list_for_each_entry(entry, &dev->msi_list, list) {
 815                 /* Keep cached states to be restored */
 816                 __msix_mask_irq(entry, 1);
 817         }
 818
 819         msix_set_enable(dev, 0);
 820         pci_intx_for_msi(dev, 1);
 821         dev->msix_enabled = 0;
 822 }
 823
 824 void pci_disable_msix(struct pci_dev *dev)
 825 {
 826         if (!pci_msi_enable || !dev || !dev->msix_enabled)
 827                 return;
 828
 829         pci_msix_shutdown(dev);
 830         free_msi_irqs(dev);
 831 }
 832 EXPORT_SYMBOL(pci_disable_msix);
 833
 834 /**
 835  * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
 836  * @dev: pointer to the pci_dev data structure of MSI(X) device function
 837  *
 838  * Being called during hotplug remove, from which the device function
 839  * is hot-removed. All previous assigned MSI/MSI-X irqs, if
 840  * allocated for this device function, are reclaimed to unused state,
 841  * which may be used later on.
 842  **/
 843 void msi_remove_pci_irq_vectors(struct pci_dev *dev)
 844 {
 845         if (!pci_msi_enable || !dev)
 846                 return;
 847
 848         if (dev->msi_enabled || dev->msix_enabled)
 849                 free_msi_irqs(dev);
 850 }
 851
 852 void pci_no_msi(void)
 853 {
 854         pci_msi_enable = 0;
 855 }
 856
 857 /**
 858  * pci_msi_enabled - is MSI enabled?
 859  *
 860  * Returns true if MSI has not been disabled by the command-line option
 861  * pci=nomsi.
 862  **/
 863 int pci_msi_enabled(void)
 864 {
 865         return pci_msi_enable;
 866 }
 867 EXPORT_SYMBOL(pci_msi_enabled);
 868
 869 void pci_msi_init_pci_dev(struct pci_dev *dev)
 870 {
 871         INIT_LIST_HEAD(&dev->msi_list);
 872 }