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PCI: add an option to allow ASPM enabled forcibly
[linux-2.6/next.git] / drivers / char / synclink.c
blobef6706f09061ebcc056667b37d94f974f96917fb
1 /*
2 * linux/drivers/char/synclink.c
3 *
4 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
5 *
6 * Device driver for Microgate SyncLink ISA and PCI
7 * high speed multiprotocol serial adapters.
8 *
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
11 *
12 * Microgate and SyncLink are trademarks of Microgate Corporation
13 *
14 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
15 *
16 * Original release 01/11/99
17 *
18 * This code is released under the GNU General Public License (GPL)
19 *
20 * This driver is primarily intended for use in synchronous
21 * HDLC mode. Asynchronous mode is also provided.
22 *
23 * When operating in synchronous mode, each call to mgsl_write()
24 * contains exactly one complete HDLC frame. Calling mgsl_put_char
25 * will start assembling an HDLC frame that will not be sent until
26 * mgsl_flush_chars or mgsl_write is called.
27 *
28 * Synchronous receive data is reported as complete frames. To accomplish
29 * this, the TTY flip buffer is bypassed (too small to hold largest
30 * frame and may fragment frames) and the line discipline
31 * receive entry point is called directly.
32 *
33 * This driver has been tested with a slightly modified ppp.c driver
34 * for synchronous PPP.
35 *
36 * 2000/02/16
37 * Added interface for syncppp.c driver (an alternate synchronous PPP
38 * implementation that also supports Cisco HDLC). Each device instance
39 * registers as a tty device AND a network device (if dosyncppp option
40 * is set for the device). The functionality is determined by which
41 * device interface is opened.
42 *
43 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
46 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
51 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
53 * OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55
56 #if defined(__i386__)
57 # define BREAKPOINT() asm(" int $3");
58 #else
59 # define BREAKPOINT() { }
60 #endif
61
62 #define MAX_ISA_DEVICES 10
63 #define MAX_PCI_DEVICES 10
64 #define MAX_TOTAL_DEVICES 20
65
66 #include <linux/module.h>
67 #include <linux/errno.h>
68 #include <linux/signal.h>
69 #include <linux/sched.h>
70 #include <linux/timer.h>
71 #include <linux/interrupt.h>
72 #include <linux/pci.h>
73 #include <linux/tty.h>
74 #include <linux/tty_flip.h>
75 #include <linux/serial.h>
76 #include <linux/major.h>
77 #include <linux/string.h>
78 #include <linux/fcntl.h>
79 #include <linux/ptrace.h>
80 #include <linux/ioport.h>
81 #include <linux/mm.h>
82 #include <linux/slab.h>
83 #include <linux/delay.h>
84 #include <linux/netdevice.h>
85 #include <linux/vmalloc.h>
86 #include <linux/init.h>
87 #include <linux/ioctl.h>
88 #include <linux/synclink.h>
89
90 #include <asm/system.h>
91 #include <asm/io.h>
92 #include <asm/irq.h>
93 #include <asm/dma.h>
94 #include <linux/bitops.h>
95 #include <asm/types.h>
96 #include <linux/termios.h>
97 #include <linux/workqueue.h>
98 #include <linux/hdlc.h>
99 #include <linux/dma-mapping.h>
100
101 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
102 #define SYNCLINK_GENERIC_HDLC 1
103 #else
104 #define SYNCLINK_GENERIC_HDLC 0
105 #endif
106
107 #define GET_USER(error,value,addr) error = get_user(value,addr)
108 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
109 #define PUT_USER(error,value,addr) error = put_user(value,addr)
110 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
111
112 #include <asm/uaccess.h>
113
114 #define RCLRVALUE 0xffff
115
116 static MGSL_PARAMS default_params = {
117 MGSL_MODE_HDLC, /* unsigned long mode */
118 0, /* unsigned char loopback; */
119 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
120 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
121 0, /* unsigned long clock_speed; */
122 0xff, /* unsigned char addr_filter; */
123 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
124 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
125 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
126 9600, /* unsigned long data_rate; */
127 8, /* unsigned char data_bits; */
128 1, /* unsigned char stop_bits; */
129 ASYNC_PARITY_NONE /* unsigned char parity; */
130 };
131
132 #define SHARED_MEM_ADDRESS_SIZE 0x40000
133 #define BUFFERLISTSIZE 4096
134 #define DMABUFFERSIZE 4096
135 #define MAXRXFRAMES 7
136
137 typedef struct _DMABUFFERENTRY
138 {
139 u32 phys_addr; /* 32-bit flat physical address of data buffer */
140 volatile u16 count; /* buffer size/data count */
141 volatile u16 status; /* Control/status field */
142 volatile u16 rcc; /* character count field */
143 u16 reserved; /* padding required by 16C32 */
144 u32 link; /* 32-bit flat link to next buffer entry */
145 char *virt_addr; /* virtual address of data buffer */
146 u32 phys_entry; /* physical address of this buffer entry */
147 dma_addr_t dma_addr;
148 } DMABUFFERENTRY, *DMAPBUFFERENTRY;
149
150 /* The queue of BH actions to be performed */
151
152 #define BH_RECEIVE 1
153 #define BH_TRANSMIT 2
154 #define BH_STATUS 4
155
156 #define IO_PIN_SHUTDOWN_LIMIT 100
157
158 struct _input_signal_events {
159 int ri_up;
160 int ri_down;
161 int dsr_up;
162 int dsr_down;
163 int dcd_up;
164 int dcd_down;
165 int cts_up;
166 int cts_down;
167 };
168
169 /* transmit holding buffer definitions*/
170 #define MAX_TX_HOLDING_BUFFERS 5
171 struct tx_holding_buffer {
172 int buffer_size;
173 unsigned char * buffer;
174 };
175
176
177 /*
178 * Device instance data structure
179 */
180
181 struct mgsl_struct {
182 int magic;
183 struct tty_port port;
184 int line;
185 int hw_version;
186
187 struct mgsl_icount icount;
188
189 int timeout;
190 int x_char; /* xon/xoff character */
191 u16 read_status_mask;
192 u16 ignore_status_mask;
193 unsigned char *xmit_buf;
194 int xmit_head;
195 int xmit_tail;
196 int xmit_cnt;
197
198 wait_queue_head_t status_event_wait_q;
199 wait_queue_head_t event_wait_q;
200 struct timer_list tx_timer; /* HDLC transmit timeout timer */
201 struct mgsl_struct *next_device; /* device list link */
202
203 spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
204 struct work_struct task; /* task structure for scheduling bh */
205
206 u32 EventMask; /* event trigger mask */
207 u32 RecordedEvents; /* pending events */
208
209 u32 max_frame_size; /* as set by device config */
210
211 u32 pending_bh;
212
213 bool bh_running; /* Protection from multiple */
214 int isr_overflow;
215 bool bh_requested;
216
217 int dcd_chkcount; /* check counts to prevent */
218 int cts_chkcount; /* too many IRQs if a signal */
219 int dsr_chkcount; /* is floating */
220 int ri_chkcount;
221
222 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
223 u32 buffer_list_phys;
224 dma_addr_t buffer_list_dma_addr;
225
226 unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
227 DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
228 unsigned int current_rx_buffer;
229
230 int num_tx_dma_buffers; /* number of tx dma frames required */
231 int tx_dma_buffers_used;
232 unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
233 DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
234 int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */
235 int current_tx_buffer; /* next tx dma buffer to be loaded */
236
237 unsigned char *intermediate_rxbuffer;
238
239 int num_tx_holding_buffers; /* number of tx holding buffer allocated */
240 int get_tx_holding_index; /* next tx holding buffer for adapter to load */
241 int put_tx_holding_index; /* next tx holding buffer to store user request */
242 int tx_holding_count; /* number of tx holding buffers waiting */
243 struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
244
245 bool rx_enabled;
246 bool rx_overflow;
247 bool rx_rcc_underrun;
248
249 bool tx_enabled;
250 bool tx_active;
251 u32 idle_mode;
252
253 u16 cmr_value;
254 u16 tcsr_value;
255
256 char device_name[25]; /* device instance name */
257
258 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
259 unsigned char bus; /* expansion bus number (zero based) */
260 unsigned char function; /* PCI device number */
261
262 unsigned int io_base; /* base I/O address of adapter */
263 unsigned int io_addr_size; /* size of the I/O address range */
264 bool io_addr_requested; /* true if I/O address requested */
265
266 unsigned int irq_level; /* interrupt level */
267 unsigned long irq_flags;
268 bool irq_requested; /* true if IRQ requested */
269
270 unsigned int dma_level; /* DMA channel */
271 bool dma_requested; /* true if dma channel requested */
272
273 u16 mbre_bit;
274 u16 loopback_bits;
275 u16 usc_idle_mode;
276
277 MGSL_PARAMS params; /* communications parameters */
278
279 unsigned char serial_signals; /* current serial signal states */
280
281 bool irq_occurred; /* for diagnostics use */
282 unsigned int init_error; /* Initialization startup error (DIAGS) */
283 int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
284
285 u32 last_mem_alloc;
286 unsigned char* memory_base; /* shared memory address (PCI only) */
287 u32 phys_memory_base;
288 bool shared_mem_requested;
289
290 unsigned char* lcr_base; /* local config registers (PCI only) */
291 u32 phys_lcr_base;
292 u32 lcr_offset;
293 bool lcr_mem_requested;
294
295 u32 misc_ctrl_value;
296 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
297 char char_buf[MAX_ASYNC_BUFFER_SIZE];
298 bool drop_rts_on_tx_done;
299
300 bool loopmode_insert_requested;
301 bool loopmode_send_done_requested;
302
303 struct _input_signal_events input_signal_events;
304
305 /* generic HDLC device parts */
306 int netcount;
307 int dosyncppp;
308 spinlock_t netlock;
309
310 #if SYNCLINK_GENERIC_HDLC
311 struct net_device *netdev;
312 #endif
313 };
314
315 #define MGSL_MAGIC 0x5401
316
317 /*
318 * The size of the serial xmit buffer is 1 page, or 4096 bytes
319 */
320 #ifndef SERIAL_XMIT_SIZE
321 #define SERIAL_XMIT_SIZE 4096
322 #endif
323
324 /*
325 * These macros define the offsets used in calculating the
326 * I/O address of the specified USC registers.
327 */
328
329
330 #define DCPIN 2 /* Bit 1 of I/O address */
331 #define SDPIN 4 /* Bit 2 of I/O address */
332
333 #define DCAR 0 /* DMA command/address register */
334 #define CCAR SDPIN /* channel command/address register */
335 #define DATAREG DCPIN + SDPIN /* serial data register */
336 #define MSBONLY 0x41
337 #define LSBONLY 0x40
338
339 /*
340 * These macros define the register address (ordinal number)
341 * used for writing address/value pairs to the USC.
342 */
343
344 #define CMR 0x02 /* Channel mode Register */
345 #define CCSR 0x04 /* Channel Command/status Register */
346 #define CCR 0x06 /* Channel Control Register */
347 #define PSR 0x08 /* Port status Register */
348 #define PCR 0x0a /* Port Control Register */
349 #define TMDR 0x0c /* Test mode Data Register */
350 #define TMCR 0x0e /* Test mode Control Register */
351 #define CMCR 0x10 /* Clock mode Control Register */
352 #define HCR 0x12 /* Hardware Configuration Register */
353 #define IVR 0x14 /* Interrupt Vector Register */
354 #define IOCR 0x16 /* Input/Output Control Register */
355 #define ICR 0x18 /* Interrupt Control Register */
356 #define DCCR 0x1a /* Daisy Chain Control Register */
357 #define MISR 0x1c /* Misc Interrupt status Register */
358 #define SICR 0x1e /* status Interrupt Control Register */
359 #define RDR 0x20 /* Receive Data Register */
360 #define RMR 0x22 /* Receive mode Register */
361 #define RCSR 0x24 /* Receive Command/status Register */
362 #define RICR 0x26 /* Receive Interrupt Control Register */
363 #define RSR 0x28 /* Receive Sync Register */
364 #define RCLR 0x2a /* Receive count Limit Register */
365 #define RCCR 0x2c /* Receive Character count Register */
366 #define TC0R 0x2e /* Time Constant 0 Register */
367 #define TDR 0x30 /* Transmit Data Register */
368 #define TMR 0x32 /* Transmit mode Register */
369 #define TCSR 0x34 /* Transmit Command/status Register */
370 #define TICR 0x36 /* Transmit Interrupt Control Register */
371 #define TSR 0x38 /* Transmit Sync Register */
372 #define TCLR 0x3a /* Transmit count Limit Register */
373 #define TCCR 0x3c /* Transmit Character count Register */
374 #define TC1R 0x3e /* Time Constant 1 Register */
375
376
377 /*
378 * MACRO DEFINITIONS FOR DMA REGISTERS
379 */
380
381 #define DCR 0x06 /* DMA Control Register (shared) */
382 #define DACR 0x08 /* DMA Array count Register (shared) */
383 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
384 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
385 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
386 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
387 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
388
389 #define TDMR 0x02 /* Transmit DMA mode Register */
390 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
391 #define TBCR 0x2a /* Transmit Byte count Register */
392 #define TARL 0x2c /* Transmit Address Register (low) */
393 #define TARU 0x2e /* Transmit Address Register (high) */
394 #define NTBCR 0x3a /* Next Transmit Byte count Register */
395 #define NTARL 0x3c /* Next Transmit Address Register (low) */
396 #define NTARU 0x3e /* Next Transmit Address Register (high) */
397
398 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
399 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
400 #define RBCR 0xaa /* Receive Byte count Register */
401 #define RARL 0xac /* Receive Address Register (low) */
402 #define RARU 0xae /* Receive Address Register (high) */
403 #define NRBCR 0xba /* Next Receive Byte count Register */
404 #define NRARL 0xbc /* Next Receive Address Register (low) */
405 #define NRARU 0xbe /* Next Receive Address Register (high) */
406
407
408 /*
409 * MACRO DEFINITIONS FOR MODEM STATUS BITS
410 */
411
412 #define MODEMSTATUS_DTR 0x80
413 #define MODEMSTATUS_DSR 0x40
414 #define MODEMSTATUS_RTS 0x20
415 #define MODEMSTATUS_CTS 0x10
416 #define MODEMSTATUS_RI 0x04
417 #define MODEMSTATUS_DCD 0x01
418
419
420 /*
421 * Channel Command/Address Register (CCAR) Command Codes
422 */
423
424 #define RTCmd_Null 0x0000
425 #define RTCmd_ResetHighestIus 0x1000
426 #define RTCmd_TriggerChannelLoadDma 0x2000
427 #define RTCmd_TriggerRxDma 0x2800
428 #define RTCmd_TriggerTxDma 0x3000
429 #define RTCmd_TriggerRxAndTxDma 0x3800
430 #define RTCmd_PurgeRxFifo 0x4800
431 #define RTCmd_PurgeTxFifo 0x5000
432 #define RTCmd_PurgeRxAndTxFifo 0x5800
433 #define RTCmd_LoadRcc 0x6800
434 #define RTCmd_LoadTcc 0x7000
435 #define RTCmd_LoadRccAndTcc 0x7800
436 #define RTCmd_LoadTC0 0x8800
437 #define RTCmd_LoadTC1 0x9000
438 #define RTCmd_LoadTC0AndTC1 0x9800
439 #define RTCmd_SerialDataLSBFirst 0xa000
440 #define RTCmd_SerialDataMSBFirst 0xa800
441 #define RTCmd_SelectBigEndian 0xb000
442 #define RTCmd_SelectLittleEndian 0xb800
443
444
445 /*
446 * DMA Command/Address Register (DCAR) Command Codes
447 */
448
449 #define DmaCmd_Null 0x0000
450 #define DmaCmd_ResetTxChannel 0x1000
451 #define DmaCmd_ResetRxChannel 0x1200
452 #define DmaCmd_StartTxChannel 0x2000
453 #define DmaCmd_StartRxChannel 0x2200
454 #define DmaCmd_ContinueTxChannel 0x3000
455 #define DmaCmd_ContinueRxChannel 0x3200
456 #define DmaCmd_PauseTxChannel 0x4000
457 #define DmaCmd_PauseRxChannel 0x4200
458 #define DmaCmd_AbortTxChannel 0x5000
459 #define DmaCmd_AbortRxChannel 0x5200
460 #define DmaCmd_InitTxChannel 0x7000
461 #define DmaCmd_InitRxChannel 0x7200
462 #define DmaCmd_ResetHighestDmaIus 0x8000
463 #define DmaCmd_ResetAllChannels 0x9000
464 #define DmaCmd_StartAllChannels 0xa000
465 #define DmaCmd_ContinueAllChannels 0xb000
466 #define DmaCmd_PauseAllChannels 0xc000
467 #define DmaCmd_AbortAllChannels 0xd000
468 #define DmaCmd_InitAllChannels 0xf000
469
470 #define TCmd_Null 0x0000
471 #define TCmd_ClearTxCRC 0x2000
472 #define TCmd_SelectTicrTtsaData 0x4000
473 #define TCmd_SelectTicrTxFifostatus 0x5000
474 #define TCmd_SelectTicrIntLevel 0x6000
475 #define TCmd_SelectTicrdma_level 0x7000
476 #define TCmd_SendFrame 0x8000
477 #define TCmd_SendAbort 0x9000
478 #define TCmd_EnableDleInsertion 0xc000
479 #define TCmd_DisableDleInsertion 0xd000
480 #define TCmd_ClearEofEom 0xe000
481 #define TCmd_SetEofEom 0xf000
482
483 #define RCmd_Null 0x0000
484 #define RCmd_ClearRxCRC 0x2000
485 #define RCmd_EnterHuntmode 0x3000
486 #define RCmd_SelectRicrRtsaData 0x4000
487 #define RCmd_SelectRicrRxFifostatus 0x5000
488 #define RCmd_SelectRicrIntLevel 0x6000
489 #define RCmd_SelectRicrdma_level 0x7000
490
491 /*
492 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
493 */
494
495 #define RECEIVE_STATUS BIT5
496 #define RECEIVE_DATA BIT4
497 #define TRANSMIT_STATUS BIT3
498 #define TRANSMIT_DATA BIT2
499 #define IO_PIN BIT1
500 #define MISC BIT0
501
502
503 /*
504 * Receive status Bits in Receive Command/status Register RCSR
505 */
506
507 #define RXSTATUS_SHORT_FRAME BIT8
508 #define RXSTATUS_CODE_VIOLATION BIT8
509 #define RXSTATUS_EXITED_HUNT BIT7
510 #define RXSTATUS_IDLE_RECEIVED BIT6
511 #define RXSTATUS_BREAK_RECEIVED BIT5
512 #define RXSTATUS_ABORT_RECEIVED BIT5
513 #define RXSTATUS_RXBOUND BIT4
514 #define RXSTATUS_CRC_ERROR BIT3
515 #define RXSTATUS_FRAMING_ERROR BIT3
516 #define RXSTATUS_ABORT BIT2
517 #define RXSTATUS_PARITY_ERROR BIT2
518 #define RXSTATUS_OVERRUN BIT1
519 #define RXSTATUS_DATA_AVAILABLE BIT0
520 #define RXSTATUS_ALL 0x01f6
521 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
522
523 /*
524 * Values for setting transmit idle mode in
525 * Transmit Control/status Register (TCSR)
526 */
527 #define IDLEMODE_FLAGS 0x0000
528 #define IDLEMODE_ALT_ONE_ZERO 0x0100
529 #define IDLEMODE_ZERO 0x0200
530 #define IDLEMODE_ONE 0x0300
531 #define IDLEMODE_ALT_MARK_SPACE 0x0500
532 #define IDLEMODE_SPACE 0x0600
533 #define IDLEMODE_MARK 0x0700
534 #define IDLEMODE_MASK 0x0700
535
536 /*
537 * IUSC revision identifiers
538 */
539 #define IUSC_SL1660 0x4d44
540 #define IUSC_PRE_SL1660 0x4553
541
542 /*
543 * Transmit status Bits in Transmit Command/status Register (TCSR)
544 */
545
546 #define TCSR_PRESERVE 0x0F00
547
548 #define TCSR_UNDERWAIT BIT11
549 #define TXSTATUS_PREAMBLE_SENT BIT7
550 #define TXSTATUS_IDLE_SENT BIT6
551 #define TXSTATUS_ABORT_SENT BIT5
552 #define TXSTATUS_EOF_SENT BIT4
553 #define TXSTATUS_EOM_SENT BIT4
554 #define TXSTATUS_CRC_SENT BIT3
555 #define TXSTATUS_ALL_SENT BIT2
556 #define TXSTATUS_UNDERRUN BIT1
557 #define TXSTATUS_FIFO_EMPTY BIT0
558 #define TXSTATUS_ALL 0x00fa
559 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
560
561
562 #define MISCSTATUS_RXC_LATCHED BIT15
563 #define MISCSTATUS_RXC BIT14
564 #define MISCSTATUS_TXC_LATCHED BIT13
565 #define MISCSTATUS_TXC BIT12
566 #define MISCSTATUS_RI_LATCHED BIT11
567 #define MISCSTATUS_RI BIT10
568 #define MISCSTATUS_DSR_LATCHED BIT9
569 #define MISCSTATUS_DSR BIT8
570 #define MISCSTATUS_DCD_LATCHED BIT7
571 #define MISCSTATUS_DCD BIT6
572 #define MISCSTATUS_CTS_LATCHED BIT5
573 #define MISCSTATUS_CTS BIT4
574 #define MISCSTATUS_RCC_UNDERRUN BIT3
575 #define MISCSTATUS_DPLL_NO_SYNC BIT2
576 #define MISCSTATUS_BRG1_ZERO BIT1
577 #define MISCSTATUS_BRG0_ZERO BIT0
578
579 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
580 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
581
582 #define SICR_RXC_ACTIVE BIT15
583 #define SICR_RXC_INACTIVE BIT14
584 #define SICR_RXC (BIT15+BIT14)
585 #define SICR_TXC_ACTIVE BIT13
586 #define SICR_TXC_INACTIVE BIT12
587 #define SICR_TXC (BIT13+BIT12)
588 #define SICR_RI_ACTIVE BIT11
589 #define SICR_RI_INACTIVE BIT10
590 #define SICR_RI (BIT11+BIT10)
591 #define SICR_DSR_ACTIVE BIT9
592 #define SICR_DSR_INACTIVE BIT8
593 #define SICR_DSR (BIT9+BIT8)
594 #define SICR_DCD_ACTIVE BIT7
595 #define SICR_DCD_INACTIVE BIT6
596 #define SICR_DCD (BIT7+BIT6)
597 #define SICR_CTS_ACTIVE BIT5
598 #define SICR_CTS_INACTIVE BIT4
599 #define SICR_CTS (BIT5+BIT4)
600 #define SICR_RCC_UNDERFLOW BIT3
601 #define SICR_DPLL_NO_SYNC BIT2
602 #define SICR_BRG1_ZERO BIT1
603 #define SICR_BRG0_ZERO BIT0
604
605 void usc_DisableMasterIrqBit( struct mgsl_struct *info );
606 void usc_EnableMasterIrqBit( struct mgsl_struct *info );
607 void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
608 void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
609 void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
610
611 #define usc_EnableInterrupts( a, b ) \
612 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
613
614 #define usc_DisableInterrupts( a, b ) \
615 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
616
617 #define usc_EnableMasterIrqBit(a) \
618 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
619
620 #define usc_DisableMasterIrqBit(a) \
621 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
622
623 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
624
625 /*
626 * Transmit status Bits in Transmit Control status Register (TCSR)
627 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
628 */
629
630 #define TXSTATUS_PREAMBLE_SENT BIT7
631 #define TXSTATUS_IDLE_SENT BIT6
632 #define TXSTATUS_ABORT_SENT BIT5
633 #define TXSTATUS_EOF BIT4
634 #define TXSTATUS_CRC_SENT BIT3
635 #define TXSTATUS_ALL_SENT BIT2
636 #define TXSTATUS_UNDERRUN BIT1
637 #define TXSTATUS_FIFO_EMPTY BIT0
638
639 #define DICR_MASTER BIT15
640 #define DICR_TRANSMIT BIT0
641 #define DICR_RECEIVE BIT1
642
643 #define usc_EnableDmaInterrupts(a,b) \
644 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
645
646 #define usc_DisableDmaInterrupts(a,b) \
647 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
648
649 #define usc_EnableStatusIrqs(a,b) \
650 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
651
652 #define usc_DisablestatusIrqs(a,b) \
653 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
654
655 /* Transmit status Bits in Transmit Control status Register (TCSR) */
656 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
657
658
659 #define DISABLE_UNCONDITIONAL 0
660 #define DISABLE_END_OF_FRAME 1
661 #define ENABLE_UNCONDITIONAL 2
662 #define ENABLE_AUTO_CTS 3
663 #define ENABLE_AUTO_DCD 3
664 #define usc_EnableTransmitter(a,b) \
665 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
666 #define usc_EnableReceiver(a,b) \
667 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
668
669 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
670 static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
671 static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
672
673 static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
674 static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
675 static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
676 void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
677 void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
678
679 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
680 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
681
682 #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
683
684 static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
685 static void usc_start_receiver( struct mgsl_struct *info );
686 static void usc_stop_receiver( struct mgsl_struct *info );
687
688 static void usc_start_transmitter( struct mgsl_struct *info );
689 static void usc_stop_transmitter( struct mgsl_struct *info );
690 static void usc_set_txidle( struct mgsl_struct *info );
691 static void usc_load_txfifo( struct mgsl_struct *info );
692
693 static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
694 static void usc_enable_loopback( struct mgsl_struct *info, int enable );
695
696 static void usc_get_serial_signals( struct mgsl_struct *info );
697 static void usc_set_serial_signals( struct mgsl_struct *info );
698
699 static void usc_reset( struct mgsl_struct *info );
700
701 static void usc_set_sync_mode( struct mgsl_struct *info );
702 static void usc_set_sdlc_mode( struct mgsl_struct *info );
703 static void usc_set_async_mode( struct mgsl_struct *info );
704 static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
705
706 static void usc_loopback_frame( struct mgsl_struct *info );
707
708 static void mgsl_tx_timeout(unsigned long context);
709
710
711 static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
712 static void usc_loopmode_insert_request( struct mgsl_struct * info );
713 static int usc_loopmode_active( struct mgsl_struct * info);
714 static void usc_loopmode_send_done( struct mgsl_struct * info );
715
716 static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
717
718 #if SYNCLINK_GENERIC_HDLC
719 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
720 static void hdlcdev_tx_done(struct mgsl_struct *info);
721 static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
722 static int hdlcdev_init(struct mgsl_struct *info);
723 static void hdlcdev_exit(struct mgsl_struct *info);
724 #endif
725
726 /*
727 * Defines a BUS descriptor value for the PCI adapter
728 * local bus address ranges.
729 */
730
731 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
732 (0x00400020 + \
733 ((WrHold) << 30) + \
734 ((WrDly) << 28) + \
735 ((RdDly) << 26) + \
736 ((Nwdd) << 20) + \
737 ((Nwad) << 15) + \
738 ((Nxda) << 13) + \
739 ((Nrdd) << 11) + \
740 ((Nrad) << 6) )
741
742 static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
743
744 /*
745 * Adapter diagnostic routines
746 */
747 static bool mgsl_register_test( struct mgsl_struct *info );
748 static bool mgsl_irq_test( struct mgsl_struct *info );
749 static bool mgsl_dma_test( struct mgsl_struct *info );
750 static bool mgsl_memory_test( struct mgsl_struct *info );
751 static int mgsl_adapter_test( struct mgsl_struct *info );
752
753 /*
754 * device and resource management routines
755 */
756 static int mgsl_claim_resources(struct mgsl_struct *info);
757 static void mgsl_release_resources(struct mgsl_struct *info);
758 static void mgsl_add_device(struct mgsl_struct *info);
759 static struct mgsl_struct* mgsl_allocate_device(void);
760
761 /*
762 * DMA buffer manupulation functions.
763 */
764 static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
765 static bool mgsl_get_rx_frame( struct mgsl_struct *info );
766 static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info );
767 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
768 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
769 static int num_free_tx_dma_buffers(struct mgsl_struct *info);
770 static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
771 static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
772
773 /*
774 * DMA and Shared Memory buffer allocation and formatting
775 */
776 static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
777 static void mgsl_free_dma_buffers(struct mgsl_struct *info);
778 static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
779 static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
780 static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
781 static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
782 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
783 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
784 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
785 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
786 static bool load_next_tx_holding_buffer(struct mgsl_struct *info);
787 static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
788
789 /*
790 * Bottom half interrupt handlers
791 */
792 static void mgsl_bh_handler(struct work_struct *work);
793 static void mgsl_bh_receive(struct mgsl_struct *info);
794 static void mgsl_bh_transmit(struct mgsl_struct *info);
795 static void mgsl_bh_status(struct mgsl_struct *info);
796
797 /*
798 * Interrupt handler routines and dispatch table.
799 */
800 static void mgsl_isr_null( struct mgsl_struct *info );
801 static void mgsl_isr_transmit_data( struct mgsl_struct *info );
802 static void mgsl_isr_receive_data( struct mgsl_struct *info );
803 static void mgsl_isr_receive_status( struct mgsl_struct *info );
804 static void mgsl_isr_transmit_status( struct mgsl_struct *info );
805 static void mgsl_isr_io_pin( struct mgsl_struct *info );
806 static void mgsl_isr_misc( struct mgsl_struct *info );
807 static void mgsl_isr_receive_dma( struct mgsl_struct *info );
808 static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
809
810 typedef void (*isr_dispatch_func)(struct mgsl_struct *);
811
812 static isr_dispatch_func UscIsrTable[7] =
813 {
814 mgsl_isr_null,
815 mgsl_isr_misc,
816 mgsl_isr_io_pin,
817 mgsl_isr_transmit_data,
818 mgsl_isr_transmit_status,
819 mgsl_isr_receive_data,
820 mgsl_isr_receive_status
821 };
822
823 /*
824 * ioctl call handlers
825 */
826 static int tiocmget(struct tty_struct *tty, struct file *file);
827 static int tiocmset(struct tty_struct *tty, struct file *file,
828 unsigned int set, unsigned int clear);
829 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
830 __user *user_icount);
831 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
832 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
833 static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
834 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
835 static int mgsl_txenable(struct mgsl_struct * info, int enable);
836 static int mgsl_txabort(struct mgsl_struct * info);
837 static int mgsl_rxenable(struct mgsl_struct * info, int enable);
838 static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
839 static int mgsl_loopmode_send_done( struct mgsl_struct * info );
840
841 /* set non-zero on successful registration with PCI subsystem */
842 static bool pci_registered;
843
844 /*
845 * Global linked list of SyncLink devices
846 */
847 static struct mgsl_struct *mgsl_device_list;
848 static int mgsl_device_count;
849
850 /*
851 * Set this param to non-zero to load eax with the
852 * .text section address and breakpoint on module load.
853 * This is useful for use with gdb and add-symbol-file command.
854 */
855 static int break_on_load;
856
857 /*
858 * Driver major number, defaults to zero to get auto
859 * assigned major number. May be forced as module parameter.
860 */
861 static int ttymajor;
862
863 /*
864 * Array of user specified options for ISA adapters.
865 */
866 static int io[MAX_ISA_DEVICES];
867 static int irq[MAX_ISA_DEVICES];
868 static int dma[MAX_ISA_DEVICES];
869 static int debug_level;
870 static int maxframe[MAX_TOTAL_DEVICES];
871 static int dosyncppp[MAX_TOTAL_DEVICES];
872 static int txdmabufs[MAX_TOTAL_DEVICES];
873 static int txholdbufs[MAX_TOTAL_DEVICES];
874
875 module_param(break_on_load, bool, 0);
876 module_param(ttymajor, int, 0);
877 module_param_array(io, int, NULL, 0);
878 module_param_array(irq, int, NULL, 0);
879 module_param_array(dma, int, NULL, 0);
880 module_param(debug_level, int, 0);
881 module_param_array(maxframe, int, NULL, 0);
882 module_param_array(dosyncppp, int, NULL, 0);
883 module_param_array(txdmabufs, int, NULL, 0);
884 module_param_array(txholdbufs, int, NULL, 0);
885
886 static char *driver_name = "SyncLink serial driver";
887 static char *driver_version = "$Revision: 4.38 $";
888
889 static int synclink_init_one (struct pci_dev *dev,
890 const struct pci_device_id *ent);
891 static void synclink_remove_one (struct pci_dev *dev);
892
893 static struct pci_device_id synclink_pci_tbl[] = {
894 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
895 { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
896 { 0, }, /* terminate list */
897 };
898 MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
899
900 MODULE_LICENSE("GPL");
901
902 static struct pci_driver synclink_pci_driver = {
903 .name = "synclink",
904 .id_table = synclink_pci_tbl,
905 .probe = synclink_init_one,
906 .remove = __devexit_p(synclink_remove_one),
907 };
908
909 static struct tty_driver *serial_driver;
910
911 /* number of characters left in xmit buffer before we ask for more */
912 #define WAKEUP_CHARS 256
913
914
915 static void mgsl_change_params(struct mgsl_struct *info);
916 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
917
918 /*
919 * 1st function defined in .text section. Calling this function in
920 * init_module() followed by a breakpoint allows a remote debugger
921 * (gdb) to get the .text address for the add-symbol-file command.
922 * This allows remote debugging of dynamically loadable modules.
923 */
924 static void* mgsl_get_text_ptr(void)
925 {
926 return mgsl_get_text_ptr;
927 }
928
929 static inline int mgsl_paranoia_check(struct mgsl_struct *info,
930 char *name, const char *routine)
931 {
932 #ifdef MGSL_PARANOIA_CHECK
933 static const char *badmagic =
934 "Warning: bad magic number for mgsl struct (%s) in %s\n";
935 static const char *badinfo =
936 "Warning: null mgsl_struct for (%s) in %s\n";
937
938 if (!info) {
939 printk(badinfo, name, routine);
940 return 1;
941 }
942 if (info->magic != MGSL_MAGIC) {
943 printk(badmagic, name, routine);
944 return 1;
945 }
946 #else
947 if (!info)
948 return 1;
949 #endif
950 return 0;
951 }
952
953 /**
954 * line discipline callback wrappers
955 *
956 * The wrappers maintain line discipline references
957 * while calling into the line discipline.
958 *
959 * ldisc_receive_buf - pass receive data to line discipline
960 */
961
962 static void ldisc_receive_buf(struct tty_struct *tty,
963 const __u8 *data, char *flags, int count)
964 {
965 struct tty_ldisc *ld;
966 if (!tty)
967 return;
968 ld = tty_ldisc_ref(tty);
969 if (ld) {
970 if (ld->ops->receive_buf)
971 ld->ops->receive_buf(tty, data, flags, count);
972 tty_ldisc_deref(ld);
973 }
974 }
975
976 /* mgsl_stop() throttle (stop) transmitter
977 *
978 * Arguments: tty pointer to tty info structure
979 * Return Value: None
980 */
981 static void mgsl_stop(struct tty_struct *tty)
982 {
983 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
984 unsigned long flags;
985
986 if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
987 return;
988
989 if ( debug_level >= DEBUG_LEVEL_INFO )
990 printk("mgsl_stop(%s)\n",info->device_name);
991
992 spin_lock_irqsave(&info->irq_spinlock,flags);
993 if (info->tx_enabled)
994 usc_stop_transmitter(info);
995 spin_unlock_irqrestore(&info->irq_spinlock,flags);
996
997 } /* end of mgsl_stop() */
998
999 /* mgsl_start() release (start) transmitter
1000 *
1001 * Arguments: tty pointer to tty info structure
1002 * Return Value: None
1003 */
1004 static void mgsl_start(struct tty_struct *tty)
1005 {
1006 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
1007 unsigned long flags;
1008
1009 if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1010 return;
1011
1012 if ( debug_level >= DEBUG_LEVEL_INFO )
1013 printk("mgsl_start(%s)\n",info->device_name);
1014
1015 spin_lock_irqsave(&info->irq_spinlock,flags);
1016 if (!info->tx_enabled)
1017 usc_start_transmitter(info);
1018 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1019
1020 } /* end of mgsl_start() */
1021
1022 /*
1023 * Bottom half work queue access functions
1024 */
1025
1026 /* mgsl_bh_action() Return next bottom half action to perform.
1027 * Return Value: BH action code or 0 if nothing to do.
1028 */
1029 static int mgsl_bh_action(struct mgsl_struct *info)
1030 {
1031 unsigned long flags;
1032 int rc = 0;
1033
1034 spin_lock_irqsave(&info->irq_spinlock,flags);
1035
1036 if (info->pending_bh & BH_RECEIVE) {
1037 info->pending_bh &= ~BH_RECEIVE;
1038 rc = BH_RECEIVE;
1039 } else if (info->pending_bh & BH_TRANSMIT) {
1040 info->pending_bh &= ~BH_TRANSMIT;
1041 rc = BH_TRANSMIT;
1042 } else if (info->pending_bh & BH_STATUS) {
1043 info->pending_bh &= ~BH_STATUS;
1044 rc = BH_STATUS;
1045 }
1046
1047 if (!rc) {
1048 /* Mark BH routine as complete */
1049 info->bh_running = false;
1050 info->bh_requested = false;
1051 }
1052
1053 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1054
1055 return rc;
1056 }
1057
1058 /*
1059 * Perform bottom half processing of work items queued by ISR.
1060 */
1061 static void mgsl_bh_handler(struct work_struct *work)
1062 {
1063 struct mgsl_struct *info =
1064 container_of(work, struct mgsl_struct, task);
1065 int action;
1066
1067 if (!info)
1068 return;
1069
1070 if ( debug_level >= DEBUG_LEVEL_BH )
1071 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1072 __FILE__,__LINE__,info->device_name);
1073
1074 info->bh_running = true;
1075
1076 while((action = mgsl_bh_action(info)) != 0) {
1077
1078 /* Process work item */
1079 if ( debug_level >= DEBUG_LEVEL_BH )
1080 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1081 __FILE__,__LINE__,action);
1082
1083 switch (action) {
1084
1085 case BH_RECEIVE:
1086 mgsl_bh_receive(info);
1087 break;
1088 case BH_TRANSMIT:
1089 mgsl_bh_transmit(info);
1090 break;
1091 case BH_STATUS:
1092 mgsl_bh_status(info);
1093 break;
1094 default:
1095 /* unknown work item ID */
1096 printk("Unknown work item ID=%08X!\n", action);
1097 break;
1098 }
1099 }
1100
1101 if ( debug_level >= DEBUG_LEVEL_BH )
1102 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1103 __FILE__,__LINE__,info->device_name);
1104 }
1105
1106 static void mgsl_bh_receive(struct mgsl_struct *info)
1107 {
1108 bool (*get_rx_frame)(struct mgsl_struct *info) =
1109 (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1110
1111 if ( debug_level >= DEBUG_LEVEL_BH )
1112 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1113 __FILE__,__LINE__,info->device_name);
1114
1115 do
1116 {
1117 if (info->rx_rcc_underrun) {
1118 unsigned long flags;
1119 spin_lock_irqsave(&info->irq_spinlock,flags);
1120 usc_start_receiver(info);
1121 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1122 return;
1123 }
1124 } while(get_rx_frame(info));
1125 }
1126
1127 static void mgsl_bh_transmit(struct mgsl_struct *info)
1128 {
1129 struct tty_struct *tty = info->port.tty;
1130 unsigned long flags;
1131
1132 if ( debug_level >= DEBUG_LEVEL_BH )
1133 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1134 __FILE__,__LINE__,info->device_name);
1135
1136 if (tty)
1137 tty_wakeup(tty);
1138
1139 /* if transmitter idle and loopmode_send_done_requested
1140 * then start echoing RxD to TxD
1141 */
1142 spin_lock_irqsave(&info->irq_spinlock,flags);
1143 if ( !info->tx_active && info->loopmode_send_done_requested )
1144 usc_loopmode_send_done( info );
1145 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1146 }
1147
1148 static void mgsl_bh_status(struct mgsl_struct *info)
1149 {
1150 if ( debug_level >= DEBUG_LEVEL_BH )
1151 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1152 __FILE__,__LINE__,info->device_name);
1153
1154 info->ri_chkcount = 0;
1155 info->dsr_chkcount = 0;
1156 info->dcd_chkcount = 0;
1157 info->cts_chkcount = 0;
1158 }
1159
1160 /* mgsl_isr_receive_status()
1161 *
1162 * Service a receive status interrupt. The type of status
1163 * interrupt is indicated by the state of the RCSR.
1164 * This is only used for HDLC mode.
1165 *
1166 * Arguments: info pointer to device instance data
1167 * Return Value: None
1168 */
1169 static void mgsl_isr_receive_status( struct mgsl_struct *info )
1170 {
1171 u16 status = usc_InReg( info, RCSR );
1172
1173 if ( debug_level >= DEBUG_LEVEL_ISR )
1174 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1175 __FILE__,__LINE__,status);
1176
1177 if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1178 info->loopmode_insert_requested &&
1179 usc_loopmode_active(info) )
1180 {
1181 ++info->icount.rxabort;
1182 info->loopmode_insert_requested = false;
1183
1184 /* clear CMR:13 to start echoing RxD to TxD */
1185 info->cmr_value &= ~BIT13;
1186 usc_OutReg(info, CMR, info->cmr_value);
1187
1188 /* disable received abort irq (no longer required) */
1189 usc_OutReg(info, RICR,
1190 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1191 }
1192
1193 if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
1194 if (status & RXSTATUS_EXITED_HUNT)
1195 info->icount.exithunt++;
1196 if (status & RXSTATUS_IDLE_RECEIVED)
1197 info->icount.rxidle++;
1198 wake_up_interruptible(&info->event_wait_q);
1199 }
1200
1201 if (status & RXSTATUS_OVERRUN){
1202 info->icount.rxover++;
1203 usc_process_rxoverrun_sync( info );
1204 }
1205
1206 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1207 usc_UnlatchRxstatusBits( info, status );
1208
1209 } /* end of mgsl_isr_receive_status() */
1210
1211 /* mgsl_isr_transmit_status()
1212 *
1213 * Service a transmit status interrupt
1214 * HDLC mode :end of transmit frame
1215 * Async mode:all data is sent
1216 * transmit status is indicated by bits in the TCSR.
1217 *
1218 * Arguments: info pointer to device instance data
1219 * Return Value: None
1220 */
1221 static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1222 {
1223 u16 status = usc_InReg( info, TCSR );
1224
1225 if ( debug_level >= DEBUG_LEVEL_ISR )
1226 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1227 __FILE__,__LINE__,status);
1228
1229 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1230 usc_UnlatchTxstatusBits( info, status );
1231
1232 if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1233 {
1234 /* finished sending HDLC abort. This may leave */
1235 /* the TxFifo with data from the aborted frame */
1236 /* so purge the TxFifo. Also shutdown the DMA */
1237 /* channel in case there is data remaining in */
1238 /* the DMA buffer */
1239 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1240 usc_RTCmd( info, RTCmd_PurgeTxFifo );
1241 }
1242
1243 if ( status & TXSTATUS_EOF_SENT )
1244 info->icount.txok++;
1245 else if ( status & TXSTATUS_UNDERRUN )
1246 info->icount.txunder++;
1247 else if ( status & TXSTATUS_ABORT_SENT )
1248 info->icount.txabort++;
1249 else
1250 info->icount.txunder++;
1251
1252 info->tx_active = false;
1253 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1254 del_timer(&info->tx_timer);
1255
1256 if ( info->drop_rts_on_tx_done ) {
1257 usc_get_serial_signals( info );
1258 if ( info->serial_signals & SerialSignal_RTS ) {
1259 info->serial_signals &= ~SerialSignal_RTS;
1260 usc_set_serial_signals( info );
1261 }
1262 info->drop_rts_on_tx_done = false;
1263 }
1264
1265 #if SYNCLINK_GENERIC_HDLC
1266 if (info->netcount)
1267 hdlcdev_tx_done(info);
1268 else
1269 #endif
1270 {
1271 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1272 usc_stop_transmitter(info);
1273 return;
1274 }
1275 info->pending_bh |= BH_TRANSMIT;
1276 }
1277
1278 } /* end of mgsl_isr_transmit_status() */
1279
1280 /* mgsl_isr_io_pin()
1281 *
1282 * Service an Input/Output pin interrupt. The type of
1283 * interrupt is indicated by bits in the MISR
1284 *
1285 * Arguments: info pointer to device instance data
1286 * Return Value: None
1287 */
1288 static void mgsl_isr_io_pin( struct mgsl_struct *info )
1289 {
1290 struct mgsl_icount *icount;
1291 u16 status = usc_InReg( info, MISR );
1292
1293 if ( debug_level >= DEBUG_LEVEL_ISR )
1294 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1295 __FILE__,__LINE__,status);
1296
1297 usc_ClearIrqPendingBits( info, IO_PIN );
1298 usc_UnlatchIostatusBits( info, status );
1299
1300 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1301 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1302 icount = &info->icount;
1303 /* update input line counters */
1304 if (status & MISCSTATUS_RI_LATCHED) {
1305 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1306 usc_DisablestatusIrqs(info,SICR_RI);
1307 icount->rng++;
1308 if ( status & MISCSTATUS_RI )
1309 info->input_signal_events.ri_up++;
1310 else
1311 info->input_signal_events.ri_down++;
1312 }
1313 if (status & MISCSTATUS_DSR_LATCHED) {
1314 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1315 usc_DisablestatusIrqs(info,SICR_DSR);
1316 icount->dsr++;
1317 if ( status & MISCSTATUS_DSR )
1318 info->input_signal_events.dsr_up++;
1319 else
1320 info->input_signal_events.dsr_down++;
1321 }
1322 if (status & MISCSTATUS_DCD_LATCHED) {
1323 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1324 usc_DisablestatusIrqs(info,SICR_DCD);
1325 icount->dcd++;
1326 if (status & MISCSTATUS_DCD) {
1327 info->input_signal_events.dcd_up++;
1328 } else
1329 info->input_signal_events.dcd_down++;
1330 #if SYNCLINK_GENERIC_HDLC
1331 if (info->netcount) {
1332 if (status & MISCSTATUS_DCD)
1333 netif_carrier_on(info->netdev);
1334 else
1335 netif_carrier_off(info->netdev);
1336 }
1337 #endif
1338 }
1339 if (status & MISCSTATUS_CTS_LATCHED)
1340 {
1341 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1342 usc_DisablestatusIrqs(info,SICR_CTS);
1343 icount->cts++;
1344 if ( status & MISCSTATUS_CTS )
1345 info->input_signal_events.cts_up++;
1346 else
1347 info->input_signal_events.cts_down++;
1348 }
1349 wake_up_interruptible(&info->status_event_wait_q);
1350 wake_up_interruptible(&info->event_wait_q);
1351
1352 if ( (info->port.flags & ASYNC_CHECK_CD) &&
1353 (status & MISCSTATUS_DCD_LATCHED) ) {
1354 if ( debug_level >= DEBUG_LEVEL_ISR )
1355 printk("%s CD now %s...", info->device_name,
1356 (status & MISCSTATUS_DCD) ? "on" : "off");
1357 if (status & MISCSTATUS_DCD)
1358 wake_up_interruptible(&info->port.open_wait);
1359 else {
1360 if ( debug_level >= DEBUG_LEVEL_ISR )
1361 printk("doing serial hangup...");
1362 if (info->port.tty)
1363 tty_hangup(info->port.tty);
1364 }
1365 }
1366
1367 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
1368 (status & MISCSTATUS_CTS_LATCHED) ) {
1369 if (info->port.tty->hw_stopped) {
1370 if (status & MISCSTATUS_CTS) {
1371 if ( debug_level >= DEBUG_LEVEL_ISR )
1372 printk("CTS tx start...");
1373 if (info->port.tty)
1374 info->port.tty->hw_stopped = 0;
1375 usc_start_transmitter(info);
1376 info->pending_bh |= BH_TRANSMIT;
1377 return;
1378 }
1379 } else {
1380 if (!(status & MISCSTATUS_CTS)) {
1381 if ( debug_level >= DEBUG_LEVEL_ISR )
1382 printk("CTS tx stop...");
1383 if (info->port.tty)
1384 info->port.tty->hw_stopped = 1;
1385 usc_stop_transmitter(info);
1386 }
1387 }
1388 }
1389 }
1390
1391 info->pending_bh |= BH_STATUS;
1392
1393 /* for diagnostics set IRQ flag */
1394 if ( status & MISCSTATUS_TXC_LATCHED ){
1395 usc_OutReg( info, SICR,
1396 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1397 usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1398 info->irq_occurred = true;
1399 }
1400
1401 } /* end of mgsl_isr_io_pin() */
1402
1403 /* mgsl_isr_transmit_data()
1404 *
1405 * Service a transmit data interrupt (async mode only).
1406 *
1407 * Arguments: info pointer to device instance data
1408 * Return Value: None
1409 */
1410 static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1411 {
1412 if ( debug_level >= DEBUG_LEVEL_ISR )
1413 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1414 __FILE__,__LINE__,info->xmit_cnt);
1415
1416 usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1417
1418 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1419 usc_stop_transmitter(info);
1420 return;
1421 }
1422
1423 if ( info->xmit_cnt )
1424 usc_load_txfifo( info );
1425 else
1426 info->tx_active = false;
1427
1428 if (info->xmit_cnt < WAKEUP_CHARS)
1429 info->pending_bh |= BH_TRANSMIT;
1430
1431 } /* end of mgsl_isr_transmit_data() */
1432
1433 /* mgsl_isr_receive_data()
1434 *
1435 * Service a receive data interrupt. This occurs
1436 * when operating in asynchronous interrupt transfer mode.
1437 * The receive data FIFO is flushed to the receive data buffers.
1438 *
1439 * Arguments: info pointer to device instance data
1440 * Return Value: None
1441 */
1442 static void mgsl_isr_receive_data( struct mgsl_struct *info )
1443 {
1444 int Fifocount;
1445 u16 status;
1446 int work = 0;
1447 unsigned char DataByte;
1448 struct tty_struct *tty = info->port.tty;
1449 struct mgsl_icount *icount = &info->icount;
1450
1451 if ( debug_level >= DEBUG_LEVEL_ISR )
1452 printk("%s(%d):mgsl_isr_receive_data\n",
1453 __FILE__,__LINE__);
1454
1455 usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1456
1457 /* select FIFO status for RICR readback */
1458 usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1459
1460 /* clear the Wordstatus bit so that status readback */
1461 /* only reflects the status of this byte */
1462 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1463
1464 /* flush the receive FIFO */
1465
1466 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1467 int flag;
1468
1469 /* read one byte from RxFIFO */
1470 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1471 info->io_base + CCAR );
1472 DataByte = inb( info->io_base + CCAR );
1473
1474 /* get the status of the received byte */
1475 status = usc_InReg(info, RCSR);
1476 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1477 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
1478 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1479
1480 icount->rx++;
1481
1482 flag = 0;
1483 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1484 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
1485 printk("rxerr=%04X\n",status);
1486 /* update error statistics */
1487 if ( status & RXSTATUS_BREAK_RECEIVED ) {
1488 status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
1489 icount->brk++;
1490 } else if (status & RXSTATUS_PARITY_ERROR)
1491 icount->parity++;
1492 else if (status & RXSTATUS_FRAMING_ERROR)
1493 icount->frame++;
1494 else if (status & RXSTATUS_OVERRUN) {
1495 /* must issue purge fifo cmd before */
1496 /* 16C32 accepts more receive chars */
1497 usc_RTCmd(info,RTCmd_PurgeRxFifo);
1498 icount->overrun++;
1499 }
1500
1501 /* discard char if tty control flags say so */
1502 if (status & info->ignore_status_mask)
1503 continue;
1504
1505 status &= info->read_status_mask;
1506
1507 if (status & RXSTATUS_BREAK_RECEIVED) {
1508 flag = TTY_BREAK;
1509 if (info->port.flags & ASYNC_SAK)
1510 do_SAK(tty);
1511 } else if (status & RXSTATUS_PARITY_ERROR)
1512 flag = TTY_PARITY;
1513 else if (status & RXSTATUS_FRAMING_ERROR)
1514 flag = TTY_FRAME;
1515 } /* end of if (error) */
1516 tty_insert_flip_char(tty, DataByte, flag);
1517 if (status & RXSTATUS_OVERRUN) {
1518 /* Overrun is special, since it's
1519 * reported immediately, and doesn't
1520 * affect the current character
1521 */
1522 work += tty_insert_flip_char(tty, 0, TTY_OVERRUN);
1523 }
1524 }
1525
1526 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1527 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1528 __FILE__,__LINE__,icount->rx,icount->brk,
1529 icount->parity,icount->frame,icount->overrun);
1530 }
1531
1532 if(work)
1533 tty_flip_buffer_push(tty);
1534 }
1535
1536 /* mgsl_isr_misc()
1537 *
1538 * Service a miscellaneous interrupt source.
1539 *
1540 * Arguments: info pointer to device extension (instance data)
1541 * Return Value: None
1542 */
1543 static void mgsl_isr_misc( struct mgsl_struct *info )
1544 {
1545 u16 status = usc_InReg( info, MISR );
1546
1547 if ( debug_level >= DEBUG_LEVEL_ISR )
1548 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1549 __FILE__,__LINE__,status);
1550
1551 if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1552 (info->params.mode == MGSL_MODE_HDLC)) {
1553
1554 /* turn off receiver and rx DMA */
1555 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1556 usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1557 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
1558 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
1559 usc_DisableInterrupts(info, RECEIVE_DATA + RECEIVE_STATUS);
1560
1561 /* schedule BH handler to restart receiver */
1562 info->pending_bh |= BH_RECEIVE;
1563 info->rx_rcc_underrun = true;
1564 }
1565
1566 usc_ClearIrqPendingBits( info, MISC );
1567 usc_UnlatchMiscstatusBits( info, status );
1568
1569 } /* end of mgsl_isr_misc() */
1570
1571 /* mgsl_isr_null()
1572 *
1573 * Services undefined interrupt vectors from the
1574 * USC. (hence this function SHOULD never be called)
1575 *
1576 * Arguments: info pointer to device extension (instance data)
1577 * Return Value: None
1578 */
1579 static void mgsl_isr_null( struct mgsl_struct *info )
1580 {
1581
1582 } /* end of mgsl_isr_null() */
1583
1584 /* mgsl_isr_receive_dma()
1585 *
1586 * Service a receive DMA channel interrupt.
1587 * For this driver there are two sources of receive DMA interrupts
1588 * as identified in the Receive DMA mode Register (RDMR):
1589 *
1590 * BIT3 EOA/EOL End of List, all receive buffers in receive
1591 * buffer list have been filled (no more free buffers
1592 * available). The DMA controller has shut down.
1593 *
1594 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1595 * DMA buffer is terminated in response to completion
1596 * of a good frame or a frame with errors. The status
1597 * of the frame is stored in the buffer entry in the
1598 * list of receive buffer entries.
1599 *
1600 * Arguments: info pointer to device instance data
1601 * Return Value: None
1602 */
1603 static void mgsl_isr_receive_dma( struct mgsl_struct *info )
1604 {
1605 u16 status;
1606
1607 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1608 usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
1609
1610 /* Read the receive DMA status to identify interrupt type. */
1611 /* This also clears the status bits. */
1612 status = usc_InDmaReg( info, RDMR );
1613
1614 if ( debug_level >= DEBUG_LEVEL_ISR )
1615 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1616 __FILE__,__LINE__,info->device_name,status);
1617
1618 info->pending_bh |= BH_RECEIVE;
1619
1620 if ( status & BIT3 ) {
1621 info->rx_overflow = true;
1622 info->icount.buf_overrun++;
1623 }
1624
1625 } /* end of mgsl_isr_receive_dma() */
1626
1627 /* mgsl_isr_transmit_dma()
1628 *
1629 * This function services a transmit DMA channel interrupt.
1630 *
1631 * For this driver there is one source of transmit DMA interrupts
1632 * as identified in the Transmit DMA Mode Register (TDMR):
1633 *
1634 * BIT2 EOB End of Buffer. This interrupt occurs when a
1635 * transmit DMA buffer has been emptied.
1636 *
1637 * The driver maintains enough transmit DMA buffers to hold at least
1638 * one max frame size transmit frame. When operating in a buffered
1639 * transmit mode, there may be enough transmit DMA buffers to hold at
1640 * least two or more max frame size frames. On an EOB condition,
1641 * determine if there are any queued transmit buffers and copy into
1642 * transmit DMA buffers if we have room.
1643 *
1644 * Arguments: info pointer to device instance data
1645 * Return Value: None
1646 */
1647 static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1648 {
1649 u16 status;
1650
1651 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1652 usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
1653
1654 /* Read the transmit DMA status to identify interrupt type. */
1655 /* This also clears the status bits. */
1656
1657 status = usc_InDmaReg( info, TDMR );
1658
1659 if ( debug_level >= DEBUG_LEVEL_ISR )
1660 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1661 __FILE__,__LINE__,info->device_name,status);
1662
1663 if ( status & BIT2 ) {
1664 --info->tx_dma_buffers_used;
1665
1666 /* if there are transmit frames queued,
1667 * try to load the next one
1668 */
1669 if ( load_next_tx_holding_buffer(info) ) {
1670 /* if call returns non-zero value, we have
1671 * at least one free tx holding buffer
1672 */
1673 info->pending_bh |= BH_TRANSMIT;
1674 }
1675 }
1676
1677 } /* end of mgsl_isr_transmit_dma() */
1678
1679 /* mgsl_interrupt()
1680 *
1681 * Interrupt service routine entry point.
1682 *
1683 * Arguments:
1684 *
1685 * irq interrupt number that caused interrupt
1686 * dev_id device ID supplied during interrupt registration
1687 *
1688 * Return Value: None
1689 */
1690 static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
1691 {
1692 struct mgsl_struct *info = dev_id;
1693 u16 UscVector;
1694 u16 DmaVector;
1695
1696 if ( debug_level >= DEBUG_LEVEL_ISR )
1697 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
1698 __FILE__, __LINE__, info->irq_level);
1699
1700 spin_lock(&info->irq_spinlock);
1701
1702 for(;;) {
1703 /* Read the interrupt vectors from hardware. */
1704 UscVector = usc_InReg(info, IVR) >> 9;
1705 DmaVector = usc_InDmaReg(info, DIVR);
1706
1707 if ( debug_level >= DEBUG_LEVEL_ISR )
1708 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1709 __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1710
1711 if ( !UscVector && !DmaVector )
1712 break;
1713
1714 /* Dispatch interrupt vector */
1715 if ( UscVector )
1716 (*UscIsrTable[UscVector])(info);
1717 else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1718 mgsl_isr_transmit_dma(info);
1719 else
1720 mgsl_isr_receive_dma(info);
1721
1722 if ( info->isr_overflow ) {
1723 printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
1724 __FILE__, __LINE__, info->device_name, info->irq_level);
1725 usc_DisableMasterIrqBit(info);
1726 usc_DisableDmaInterrupts(info,DICR_MASTER);
1727 break;
1728 }
1729 }
1730
1731 /* Request bottom half processing if there's something
1732 * for it to do and the bh is not already running
1733 */
1734
1735 if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1736 if ( debug_level >= DEBUG_LEVEL_ISR )
1737 printk("%s(%d):%s queueing bh task.\n",
1738 __FILE__,__LINE__,info->device_name);
1739 schedule_work(&info->task);
1740 info->bh_requested = true;
1741 }
1742
1743 spin_unlock(&info->irq_spinlock);
1744
1745 if ( debug_level >= DEBUG_LEVEL_ISR )
1746 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
1747 __FILE__, __LINE__, info->irq_level);
1748
1749 return IRQ_HANDLED;
1750 } /* end of mgsl_interrupt() */
1751
1752 /* startup()
1753 *
1754 * Initialize and start device.
1755 *
1756 * Arguments: info pointer to device instance data
1757 * Return Value: 0 if success, otherwise error code
1758 */
1759 static int startup(struct mgsl_struct * info)
1760 {
1761 int retval = 0;
1762
1763 if ( debug_level >= DEBUG_LEVEL_INFO )
1764 printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1765
1766 if (info->port.flags & ASYNC_INITIALIZED)
1767 return 0;
1768
1769 if (!info->xmit_buf) {
1770 /* allocate a page of memory for a transmit buffer */
1771 info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1772 if (!info->xmit_buf) {
1773 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1774 __FILE__,__LINE__,info->device_name);
1775 return -ENOMEM;
1776 }
1777 }
1778
1779 info->pending_bh = 0;
1780
1781 memset(&info->icount, 0, sizeof(info->icount));
1782
1783 setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info);
1784
1785 /* Allocate and claim adapter resources */
1786 retval = mgsl_claim_resources(info);
1787
1788 /* perform existence check and diagnostics */
1789 if ( !retval )
1790 retval = mgsl_adapter_test(info);
1791
1792 if ( retval ) {
1793 if (capable(CAP_SYS_ADMIN) && info->port.tty)
1794 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1795 mgsl_release_resources(info);
1796 return retval;
1797 }
1798
1799 /* program hardware for current parameters */
1800 mgsl_change_params(info);
1801
1802 if (info->port.tty)
1803 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1804
1805 info->port.flags |= ASYNC_INITIALIZED;
1806
1807 return 0;
1808
1809 } /* end of startup() */
1810
1811 /* shutdown()
1812 *
1813 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1814 *
1815 * Arguments: info pointer to device instance data
1816 * Return Value: None
1817 */
1818 static void shutdown(struct mgsl_struct * info)
1819 {
1820 unsigned long flags;
1821
1822 if (!(info->port.flags & ASYNC_INITIALIZED))
1823 return;
1824
1825 if (debug_level >= DEBUG_LEVEL_INFO)
1826 printk("%s(%d):mgsl_shutdown(%s)\n",
1827 __FILE__,__LINE__, info->device_name );
1828
1829 /* clear status wait queue because status changes */
1830 /* can't happen after shutting down the hardware */
1831 wake_up_interruptible(&info->status_event_wait_q);
1832 wake_up_interruptible(&info->event_wait_q);
1833
1834 del_timer_sync(&info->tx_timer);
1835
1836 if (info->xmit_buf) {
1837 free_page((unsigned long) info->xmit_buf);
1838 info->xmit_buf = NULL;
1839 }
1840
1841 spin_lock_irqsave(&info->irq_spinlock,flags);
1842 usc_DisableMasterIrqBit(info);
1843 usc_stop_receiver(info);
1844 usc_stop_transmitter(info);
1845 usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
1846 TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
1847 usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1848
1849 /* Disable DMAEN (Port 7, Bit 14) */
1850 /* This disconnects the DMA request signal from the ISA bus */
1851 /* on the ISA adapter. This has no effect for the PCI adapter */
1852 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1853
1854 /* Disable INTEN (Port 6, Bit12) */
1855 /* This disconnects the IRQ request signal to the ISA bus */
1856 /* on the ISA adapter. This has no effect for the PCI adapter */
1857 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1858
1859 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
1860 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1861 usc_set_serial_signals(info);
1862 }
1863
1864 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1865
1866 mgsl_release_resources(info);
1867
1868 if (info->port.tty)
1869 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1870
1871 info->port.flags &= ~ASYNC_INITIALIZED;
1872
1873 } /* end of shutdown() */
1874
1875 static void mgsl_program_hw(struct mgsl_struct *info)
1876 {
1877 unsigned long flags;
1878
1879 spin_lock_irqsave(&info->irq_spinlock,flags);
1880
1881 usc_stop_receiver(info);
1882 usc_stop_transmitter(info);
1883 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1884
1885 if (info->params.mode == MGSL_MODE_HDLC ||
1886 info->params.mode == MGSL_MODE_RAW ||
1887 info->netcount)
1888 usc_set_sync_mode(info);
1889 else
1890 usc_set_async_mode(info);
1891
1892 usc_set_serial_signals(info);
1893
1894 info->dcd_chkcount = 0;
1895 info->cts_chkcount = 0;
1896 info->ri_chkcount = 0;
1897 info->dsr_chkcount = 0;
1898
1899 usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1900 usc_EnableInterrupts(info, IO_PIN);
1901 usc_get_serial_signals(info);
1902
1903 if (info->netcount || info->port.tty->termios->c_cflag & CREAD)
1904 usc_start_receiver(info);
1905
1906 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1907 }
1908
1909 /* Reconfigure adapter based on new parameters
1910 */
1911 static void mgsl_change_params(struct mgsl_struct *info)
1912 {
1913 unsigned cflag;
1914 int bits_per_char;
1915
1916 if (!info->port.tty || !info->port.tty->termios)
1917 return;
1918
1919 if (debug_level >= DEBUG_LEVEL_INFO)
1920 printk("%s(%d):mgsl_change_params(%s)\n",
1921 __FILE__,__LINE__, info->device_name );
1922
1923 cflag = info->port.tty->termios->c_cflag;
1924
1925 /* if B0 rate (hangup) specified then negate DTR and RTS */
1926 /* otherwise assert DTR and RTS */
1927 if (cflag & CBAUD)
1928 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1929 else
1930 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
1931
1932 /* byte size and parity */
1933
1934 switch (cflag & CSIZE) {
1935 case CS5: info->params.data_bits = 5; break;
1936 case CS6: info->params.data_bits = 6; break;
1937 case CS7: info->params.data_bits = 7; break;
1938 case CS8: info->params.data_bits = 8; break;
1939 /* Never happens, but GCC is too dumb to figure it out */
1940 default: info->params.data_bits = 7; break;
1941 }
1942
1943 if (cflag & CSTOPB)
1944 info->params.stop_bits = 2;
1945 else
1946 info->params.stop_bits = 1;
1947
1948 info->params.parity = ASYNC_PARITY_NONE;
1949 if (cflag & PARENB) {
1950 if (cflag & PARODD)
1951 info->params.parity = ASYNC_PARITY_ODD;
1952 else
1953 info->params.parity = ASYNC_PARITY_EVEN;
1954 #ifdef CMSPAR
1955 if (cflag & CMSPAR)
1956 info->params.parity = ASYNC_PARITY_SPACE;
1957 #endif
1958 }
1959
1960 /* calculate number of jiffies to transmit a full
1961 * FIFO (32 bytes) at specified data rate
1962 */
1963 bits_per_char = info->params.data_bits +
1964 info->params.stop_bits + 1;
1965
1966 /* if port data rate is set to 460800 or less then
1967 * allow tty settings to override, otherwise keep the
1968 * current data rate.
1969 */
1970 if (info->params.data_rate <= 460800)
1971 info->params.data_rate = tty_get_baud_rate(info->port.tty);
1972
1973 if ( info->params.data_rate ) {
1974 info->timeout = (32*HZ*bits_per_char) /
1975 info->params.data_rate;
1976 }
1977 info->timeout += HZ/50; /* Add .02 seconds of slop */
1978
1979 if (cflag & CRTSCTS)
1980 info->port.flags |= ASYNC_CTS_FLOW;
1981 else
1982 info->port.flags &= ~ASYNC_CTS_FLOW;
1983
1984 if (cflag & CLOCAL)
1985 info->port.flags &= ~ASYNC_CHECK_CD;
1986 else
1987 info->port.flags |= ASYNC_CHECK_CD;
1988
1989 /* process tty input control flags */
1990
1991 info->read_status_mask = RXSTATUS_OVERRUN;
1992 if (I_INPCK(info->port.tty))
1993 info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1994 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
1995 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
1996
1997 if (I_IGNPAR(info->port.tty))
1998 info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1999 if (I_IGNBRK(info->port.tty)) {
2000 info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
2001 /* If ignoring parity and break indicators, ignore
2002 * overruns too. (For real raw support).
2003 */
2004 if (I_IGNPAR(info->port.tty))
2005 info->ignore_status_mask |= RXSTATUS_OVERRUN;
2006 }
2007
2008 mgsl_program_hw(info);
2009
2010 } /* end of mgsl_change_params() */
2011
2012 /* mgsl_put_char()
2013 *
2014 * Add a character to the transmit buffer.
2015 *
2016 * Arguments: tty pointer to tty information structure
2017 * ch character to add to transmit buffer
2018 *
2019 * Return Value: None
2020 */
2021 static int mgsl_put_char(struct tty_struct *tty, unsigned char ch)
2022 {
2023 struct mgsl_struct *info = tty->driver_data;
2024 unsigned long flags;
2025 int ret = 0;
2026
2027 if (debug_level >= DEBUG_LEVEL_INFO) {
2028 printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n",
2029 __FILE__, __LINE__, ch, info->device_name);
2030 }
2031
2032 if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
2033 return 0;
2034
2035 if (!tty || !info->xmit_buf)
2036 return 0;
2037
2038 spin_lock_irqsave(&info->irq_spinlock, flags);
2039
2040 if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) {
2041 if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2042 info->xmit_buf[info->xmit_head++] = ch;
2043 info->xmit_head &= SERIAL_XMIT_SIZE-1;
2044 info->xmit_cnt++;
2045 ret = 1;
2046 }
2047 }
2048 spin_unlock_irqrestore(&info->irq_spinlock, flags);
2049 return ret;
2050
2051 } /* end of mgsl_put_char() */
2052
2053 /* mgsl_flush_chars()
2054 *
2055 * Enable transmitter so remaining characters in the
2056 * transmit buffer are sent.
2057 *
2058 * Arguments: tty pointer to tty information structure
2059 * Return Value: None
2060 */
2061 static void mgsl_flush_chars(struct tty_struct *tty)
2062 {
2063 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2064 unsigned long flags;
2065
2066 if ( debug_level >= DEBUG_LEVEL_INFO )
2067 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2068 __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2069
2070 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2071 return;
2072
2073 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2074 !info->xmit_buf)
2075 return;
2076
2077 if ( debug_level >= DEBUG_LEVEL_INFO )
2078 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2079 __FILE__,__LINE__,info->device_name );
2080
2081 spin_lock_irqsave(&info->irq_spinlock,flags);
2082
2083 if (!info->tx_active) {
2084 if ( (info->params.mode == MGSL_MODE_HDLC ||
2085 info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2086 /* operating in synchronous (frame oriented) mode */
2087 /* copy data from circular xmit_buf to */
2088 /* transmit DMA buffer. */
2089 mgsl_load_tx_dma_buffer(info,
2090 info->xmit_buf,info->xmit_cnt);
2091 }
2092 usc_start_transmitter(info);
2093 }
2094
2095 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2096
2097 } /* end of mgsl_flush_chars() */
2098
2099 /* mgsl_write()
2100 *
2101 * Send a block of data
2102 *
2103 * Arguments:
2104 *
2105 * tty pointer to tty information structure
2106 * buf pointer to buffer containing send data
2107 * count size of send data in bytes
2108 *
2109 * Return Value: number of characters written
2110 */
2111 static int mgsl_write(struct tty_struct * tty,
2112 const unsigned char *buf, int count)
2113 {
2114 int c, ret = 0;
2115 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2116 unsigned long flags;
2117
2118 if ( debug_level >= DEBUG_LEVEL_INFO )
2119 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2120 __FILE__,__LINE__,info->device_name,count);
2121
2122 if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2123 goto cleanup;
2124
2125 if (!tty || !info->xmit_buf)
2126 goto cleanup;
2127
2128 if ( info->params.mode == MGSL_MODE_HDLC ||
2129 info->params.mode == MGSL_MODE_RAW ) {
2130 /* operating in synchronous (frame oriented) mode */
2131 /* operating in synchronous (frame oriented) mode */
2132 if (info->tx_active) {
2133
2134 if ( info->params.mode == MGSL_MODE_HDLC ) {
2135 ret = 0;
2136 goto cleanup;
2137 }
2138 /* transmitter is actively sending data -
2139 * if we have multiple transmit dma and
2140 * holding buffers, attempt to queue this
2141 * frame for transmission at a later time.
2142 */
2143 if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2144 /* no tx holding buffers available */
2145 ret = 0;
2146 goto cleanup;
2147 }
2148
2149 /* queue transmit frame request */
2150 ret = count;
2151 save_tx_buffer_request(info,buf,count);
2152
2153 /* if we have sufficient tx dma buffers,
2154 * load the next buffered tx request
2155 */
2156 spin_lock_irqsave(&info->irq_spinlock,flags);
2157 load_next_tx_holding_buffer(info);
2158 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2159 goto cleanup;
2160 }
2161
2162 /* if operating in HDLC LoopMode and the adapter */
2163 /* has yet to be inserted into the loop, we can't */
2164 /* transmit */
2165
2166 if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2167 !usc_loopmode_active(info) )
2168 {
2169 ret = 0;
2170 goto cleanup;
2171 }
2172
2173 if ( info->xmit_cnt ) {
2174 /* Send accumulated from send_char() calls */
2175 /* as frame and wait before accepting more data. */
2176 ret = 0;
2177
2178 /* copy data from circular xmit_buf to */
2179 /* transmit DMA buffer. */
2180 mgsl_load_tx_dma_buffer(info,
2181 info->xmit_buf,info->xmit_cnt);
2182 if ( debug_level >= DEBUG_LEVEL_INFO )
2183 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2184 __FILE__,__LINE__,info->device_name);
2185 } else {
2186 if ( debug_level >= DEBUG_LEVEL_INFO )
2187 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2188 __FILE__,__LINE__,info->device_name);
2189 ret = count;
2190 info->xmit_cnt = count;
2191 mgsl_load_tx_dma_buffer(info,buf,count);
2192 }
2193 } else {
2194 while (1) {
2195 spin_lock_irqsave(&info->irq_spinlock,flags);
2196 c = min_t(int, count,
2197 min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2198 SERIAL_XMIT_SIZE - info->xmit_head));
2199 if (c <= 0) {
2200 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2201 break;
2202 }
2203 memcpy(info->xmit_buf + info->xmit_head, buf, c);
2204 info->xmit_head = ((info->xmit_head + c) &
2205 (SERIAL_XMIT_SIZE-1));
2206 info->xmit_cnt += c;
2207 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2208 buf += c;
2209 count -= c;
2210 ret += c;
2211 }
2212 }
2213
2214 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2215 spin_lock_irqsave(&info->irq_spinlock,flags);
2216 if (!info->tx_active)
2217 usc_start_transmitter(info);
2218 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2219 }
2220 cleanup:
2221 if ( debug_level >= DEBUG_LEVEL_INFO )
2222 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2223 __FILE__,__LINE__,info->device_name,ret);
2224
2225 return ret;
2226
2227 } /* end of mgsl_write() */
2228
2229 /* mgsl_write_room()
2230 *
2231 * Return the count of free bytes in transmit buffer
2232 *
2233 * Arguments: tty pointer to tty info structure
2234 * Return Value: None
2235 */
2236 static int mgsl_write_room(struct tty_struct *tty)
2237 {
2238 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2239 int ret;
2240
2241 if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2242 return 0;
2243 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2244 if (ret < 0)
2245 ret = 0;
2246
2247 if (debug_level >= DEBUG_LEVEL_INFO)
2248 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2249 __FILE__,__LINE__, info->device_name,ret );
2250
2251 if ( info->params.mode == MGSL_MODE_HDLC ||
2252 info->params.mode == MGSL_MODE_RAW ) {
2253 /* operating in synchronous (frame oriented) mode */
2254 if ( info->tx_active )
2255 return 0;
2256 else
2257 return HDLC_MAX_FRAME_SIZE;
2258 }
2259
2260 return ret;
2261
2262 } /* end of mgsl_write_room() */
2263
2264 /* mgsl_chars_in_buffer()
2265 *
2266 * Return the count of bytes in transmit buffer
2267 *
2268 * Arguments: tty pointer to tty info structure
2269 * Return Value: None
2270 */
2271 static int mgsl_chars_in_buffer(struct tty_struct *tty)
2272 {
2273 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2274
2275 if (debug_level >= DEBUG_LEVEL_INFO)
2276 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2277 __FILE__,__LINE__, info->device_name );
2278
2279 if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2280 return 0;
2281
2282 if (debug_level >= DEBUG_LEVEL_INFO)
2283 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2284 __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2285
2286 if ( info->params.mode == MGSL_MODE_HDLC ||
2287 info->params.mode == MGSL_MODE_RAW ) {
2288 /* operating in synchronous (frame oriented) mode */
2289 if ( info->tx_active )
2290 return info->max_frame_size;
2291 else
2292 return 0;
2293 }
2294
2295 return info->xmit_cnt;
2296 } /* end of mgsl_chars_in_buffer() */
2297
2298 /* mgsl_flush_buffer()
2299 *
2300 * Discard all data in the send buffer
2301 *
2302 * Arguments: tty pointer to tty info structure
2303 * Return Value: None
2304 */
2305 static void mgsl_flush_buffer(struct tty_struct *tty)
2306 {
2307 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2308 unsigned long flags;
2309
2310 if (debug_level >= DEBUG_LEVEL_INFO)
2311 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2312 __FILE__,__LINE__, info->device_name );
2313
2314 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2315 return;
2316
2317 spin_lock_irqsave(&info->irq_spinlock,flags);
2318 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2319 del_timer(&info->tx_timer);
2320 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2321
2322 tty_wakeup(tty);
2323 }
2324
2325 /* mgsl_send_xchar()
2326 *
2327 * Send a high-priority XON/XOFF character
2328 *
2329 * Arguments: tty pointer to tty info structure
2330 * ch character to send
2331 * Return Value: None
2332 */
2333 static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2334 {
2335 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2336 unsigned long flags;
2337
2338 if (debug_level >= DEBUG_LEVEL_INFO)
2339 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2340 __FILE__,__LINE__, info->device_name, ch );
2341
2342 if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2343 return;
2344
2345 info->x_char = ch;
2346 if (ch) {
2347 /* Make sure transmit interrupts are on */
2348 spin_lock_irqsave(&info->irq_spinlock,flags);
2349 if (!info->tx_enabled)
2350 usc_start_transmitter(info);
2351 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2352 }
2353 } /* end of mgsl_send_xchar() */
2354
2355 /* mgsl_throttle()
2356 *
2357 * Signal remote device to throttle send data (our receive data)
2358 *
2359 * Arguments: tty pointer to tty info structure
2360 * Return Value: None
2361 */
2362 static void mgsl_throttle(struct tty_struct * tty)
2363 {
2364 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2365 unsigned long flags;
2366
2367 if (debug_level >= DEBUG_LEVEL_INFO)
2368 printk("%s(%d):mgsl_throttle(%s) entry\n",
2369 __FILE__,__LINE__, info->device_name );
2370
2371 if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2372 return;
2373
2374 if (I_IXOFF(tty))
2375 mgsl_send_xchar(tty, STOP_CHAR(tty));
2376
2377 if (tty->termios->c_cflag & CRTSCTS) {
2378 spin_lock_irqsave(&info->irq_spinlock,flags);
2379 info->serial_signals &= ~SerialSignal_RTS;
2380 usc_set_serial_signals(info);
2381 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2382 }
2383 } /* end of mgsl_throttle() */
2384
2385 /* mgsl_unthrottle()
2386 *
2387 * Signal remote device to stop throttling send data (our receive data)
2388 *
2389 * Arguments: tty pointer to tty info structure
2390 * Return Value: None
2391 */
2392 static void mgsl_unthrottle(struct tty_struct * tty)
2393 {
2394 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2395 unsigned long flags;
2396
2397 if (debug_level >= DEBUG_LEVEL_INFO)
2398 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2399 __FILE__,__LINE__, info->device_name );
2400
2401 if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2402 return;
2403
2404 if (I_IXOFF(tty)) {
2405 if (info->x_char)
2406 info->x_char = 0;
2407 else
2408 mgsl_send_xchar(tty, START_CHAR(tty));
2409 }
2410
2411 if (tty->termios->c_cflag & CRTSCTS) {
2412 spin_lock_irqsave(&info->irq_spinlock,flags);
2413 info->serial_signals |= SerialSignal_RTS;
2414 usc_set_serial_signals(info);
2415 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2416 }
2417
2418 } /* end of mgsl_unthrottle() */
2419
2420 /* mgsl_get_stats()
2421 *
2422 * get the current serial parameters information
2423 *
2424 * Arguments: info pointer to device instance data
2425 * user_icount pointer to buffer to hold returned stats
2426 *
2427 * Return Value: 0 if success, otherwise error code
2428 */
2429 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2430 {
2431 int err;
2432
2433 if (debug_level >= DEBUG_LEVEL_INFO)
2434 printk("%s(%d):mgsl_get_params(%s)\n",
2435 __FILE__,__LINE__, info->device_name);
2436
2437 if (!user_icount) {
2438 memset(&info->icount, 0, sizeof(info->icount));
2439 } else {
2440 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2441 if (err)
2442 return -EFAULT;
2443 }
2444
2445 return 0;
2446
2447 } /* end of mgsl_get_stats() */
2448
2449 /* mgsl_get_params()
2450 *
2451 * get the current serial parameters information
2452 *
2453 * Arguments: info pointer to device instance data
2454 * user_params pointer to buffer to hold returned params
2455 *
2456 * Return Value: 0 if success, otherwise error code
2457 */
2458 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2459 {
2460 int err;
2461 if (debug_level >= DEBUG_LEVEL_INFO)
2462 printk("%s(%d):mgsl_get_params(%s)\n",
2463 __FILE__,__LINE__, info->device_name);
2464
2465 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2466 if (err) {
2467 if ( debug_level >= DEBUG_LEVEL_INFO )
2468 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2469 __FILE__,__LINE__,info->device_name);
2470 return -EFAULT;
2471 }
2472
2473 return 0;
2474
2475 } /* end of mgsl_get_params() */
2476
2477 /* mgsl_set_params()
2478 *
2479 * set the serial parameters
2480 *
2481 * Arguments:
2482 *
2483 * info pointer to device instance data
2484 * new_params user buffer containing new serial params
2485 *
2486 * Return Value: 0 if success, otherwise error code
2487 */
2488 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2489 {
2490 unsigned long flags;
2491 MGSL_PARAMS tmp_params;
2492 int err;
2493
2494 if (debug_level >= DEBUG_LEVEL_INFO)
2495 printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2496 info->device_name );
2497 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2498 if (err) {
2499 if ( debug_level >= DEBUG_LEVEL_INFO )
2500 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2501 __FILE__,__LINE__,info->device_name);
2502 return -EFAULT;
2503 }
2504
2505 spin_lock_irqsave(&info->irq_spinlock,flags);
2506 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2507 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2508
2509 mgsl_change_params(info);
2510
2511 return 0;
2512
2513 } /* end of mgsl_set_params() */
2514
2515 /* mgsl_get_txidle()
2516 *
2517 * get the current transmit idle mode
2518 *
2519 * Arguments: info pointer to device instance data
2520 * idle_mode pointer to buffer to hold returned idle mode
2521 *
2522 * Return Value: 0 if success, otherwise error code
2523 */
2524 static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2525 {
2526 int err;
2527
2528 if (debug_level >= DEBUG_LEVEL_INFO)
2529 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2530 __FILE__,__LINE__, info->device_name, info->idle_mode);
2531
2532 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2533 if (err) {
2534 if ( debug_level >= DEBUG_LEVEL_INFO )
2535 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2536 __FILE__,__LINE__,info->device_name);
2537 return -EFAULT;
2538 }
2539
2540 return 0;
2541
2542 } /* end of mgsl_get_txidle() */
2543
2544 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2545 *
2546 * Arguments: info pointer to device instance data
2547 * idle_mode new idle mode
2548 *
2549 * Return Value: 0 if success, otherwise error code
2550 */
2551 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2552 {
2553 unsigned long flags;
2554
2555 if (debug_level >= DEBUG_LEVEL_INFO)
2556 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2557 info->device_name, idle_mode );
2558
2559 spin_lock_irqsave(&info->irq_spinlock,flags);
2560 info->idle_mode = idle_mode;
2561 usc_set_txidle( info );
2562 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2563 return 0;
2564
2565 } /* end of mgsl_set_txidle() */
2566
2567 /* mgsl_txenable()
2568 *
2569 * enable or disable the transmitter
2570 *
2571 * Arguments:
2572 *
2573 * info pointer to device instance data
2574 * enable 1 = enable, 0 = disable
2575 *
2576 * Return Value: 0 if success, otherwise error code
2577 */
2578 static int mgsl_txenable(struct mgsl_struct * info, int enable)
2579 {
2580 unsigned long flags;
2581
2582 if (debug_level >= DEBUG_LEVEL_INFO)
2583 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2584 info->device_name, enable);
2585
2586 spin_lock_irqsave(&info->irq_spinlock,flags);
2587 if ( enable ) {
2588 if ( !info->tx_enabled ) {
2589
2590 usc_start_transmitter(info);
2591 /*--------------------------------------------------
2592 * if HDLC/SDLC Loop mode, attempt to insert the
2593 * station in the 'loop' by setting CMR:13. Upon
2594 * receipt of the next GoAhead (RxAbort) sequence,
2595 * the OnLoop indicator (CCSR:7) should go active
2596 * to indicate that we are on the loop
2597 *--------------------------------------------------*/
2598 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2599 usc_loopmode_insert_request( info );
2600 }
2601 } else {
2602 if ( info->tx_enabled )
2603 usc_stop_transmitter(info);
2604 }
2605 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2606 return 0;
2607
2608 } /* end of mgsl_txenable() */
2609
2610 /* mgsl_txabort() abort send HDLC frame
2611 *
2612 * Arguments: info pointer to device instance data
2613 * Return Value: 0 if success, otherwise error code
2614 */
2615 static int mgsl_txabort(struct mgsl_struct * info)
2616 {
2617 unsigned long flags;
2618
2619 if (debug_level >= DEBUG_LEVEL_INFO)
2620 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2621 info->device_name);
2622
2623 spin_lock_irqsave(&info->irq_spinlock,flags);
2624 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2625 {
2626 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2627 usc_loopmode_cancel_transmit( info );
2628 else
2629 usc_TCmd(info,TCmd_SendAbort);
2630 }
2631 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2632 return 0;
2633
2634 } /* end of mgsl_txabort() */
2635
2636 /* mgsl_rxenable() enable or disable the receiver
2637 *
2638 * Arguments: info pointer to device instance data
2639 * enable 1 = enable, 0 = disable
2640 * Return Value: 0 if success, otherwise error code
2641 */
2642 static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2643 {
2644 unsigned long flags;
2645
2646 if (debug_level >= DEBUG_LEVEL_INFO)
2647 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2648 info->device_name, enable);
2649
2650 spin_lock_irqsave(&info->irq_spinlock,flags);
2651 if ( enable ) {
2652 if ( !info->rx_enabled )
2653 usc_start_receiver(info);
2654 } else {
2655 if ( info->rx_enabled )
2656 usc_stop_receiver(info);
2657 }
2658 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2659 return 0;
2660
2661 } /* end of mgsl_rxenable() */
2662
2663 /* mgsl_wait_event() wait for specified event to occur
2664 *
2665 * Arguments: info pointer to device instance data
2666 * mask pointer to bitmask of events to wait for
2667 * Return Value: 0 if successful and bit mask updated with
2668 * of events triggerred,
2669 * otherwise error code
2670 */
2671 static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2672 {
2673 unsigned long flags;
2674 int s;
2675 int rc=0;
2676 struct mgsl_icount cprev, cnow;
2677 int events;
2678 int mask;
2679 struct _input_signal_events oldsigs, newsigs;
2680 DECLARE_WAITQUEUE(wait, current);
2681
2682 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2683 if (rc) {
2684 return -EFAULT;
2685 }
2686
2687 if (debug_level >= DEBUG_LEVEL_INFO)
2688 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2689 info->device_name, mask);
2690
2691 spin_lock_irqsave(&info->irq_spinlock,flags);
2692
2693 /* return immediately if state matches requested events */
2694 usc_get_serial_signals(info);
2695 s = info->serial_signals;
2696 events = mask &
2697 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2698 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2699 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2700 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2701 if (events) {
2702 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2703 goto exit;
2704 }
2705
2706 /* save current irq counts */
2707 cprev = info->icount;
2708 oldsigs = info->input_signal_events;
2709
2710 /* enable hunt and idle irqs if needed */
2711 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2712 u16 oldreg = usc_InReg(info,RICR);
2713 u16 newreg = oldreg +
2714 (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2715 (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2716 if (oldreg != newreg)
2717 usc_OutReg(info, RICR, newreg);
2718 }
2719
2720 set_current_state(TASK_INTERRUPTIBLE);
2721 add_wait_queue(&info->event_wait_q, &wait);
2722
2723 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2724
2725
2726 for(;;) {
2727 schedule();
2728 if (signal_pending(current)) {
2729 rc = -ERESTARTSYS;
2730 break;
2731 }
2732
2733 /* get current irq counts */
2734 spin_lock_irqsave(&info->irq_spinlock,flags);
2735 cnow = info->icount;
2736 newsigs = info->input_signal_events;
2737 set_current_state(TASK_INTERRUPTIBLE);
2738 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2739
2740 /* if no change, wait aborted for some reason */
2741 if (newsigs.dsr_up == oldsigs.dsr_up &&
2742 newsigs.dsr_down == oldsigs.dsr_down &&
2743 newsigs.dcd_up == oldsigs.dcd_up &&
2744 newsigs.dcd_down == oldsigs.dcd_down &&
2745 newsigs.cts_up == oldsigs.cts_up &&
2746 newsigs.cts_down == oldsigs.cts_down &&
2747 newsigs.ri_up == oldsigs.ri_up &&
2748 newsigs.ri_down == oldsigs.ri_down &&
2749 cnow.exithunt == cprev.exithunt &&
2750 cnow.rxidle == cprev.rxidle) {
2751 rc = -EIO;
2752 break;
2753 }
2754
2755 events = mask &
2756 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2757 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2758 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2759 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2760 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2761 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2762 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2763 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2764 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2765 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2766 if (events)
2767 break;
2768
2769 cprev = cnow;
2770 oldsigs = newsigs;
2771 }
2772
2773 remove_wait_queue(&info->event_wait_q, &wait);
2774 set_current_state(TASK_RUNNING);
2775
2776 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2777 spin_lock_irqsave(&info->irq_spinlock,flags);
2778 if (!waitqueue_active(&info->event_wait_q)) {
2779 /* disable enable exit hunt mode/idle rcvd IRQs */
2780 usc_OutReg(info, RICR, usc_InReg(info,RICR) &
2781 ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
2782 }
2783 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2784 }
2785 exit:
2786 if ( rc == 0 )
2787 PUT_USER(rc, events, mask_ptr);
2788
2789 return rc;
2790
2791 } /* end of mgsl_wait_event() */
2792
2793 static int modem_input_wait(struct mgsl_struct *info,int arg)
2794 {
2795 unsigned long flags;
2796 int rc;
2797 struct mgsl_icount cprev, cnow;
2798 DECLARE_WAITQUEUE(wait, current);
2799
2800 /* save current irq counts */
2801 spin_lock_irqsave(&info->irq_spinlock,flags);
2802 cprev = info->icount;
2803 add_wait_queue(&info->status_event_wait_q, &wait);
2804 set_current_state(TASK_INTERRUPTIBLE);
2805 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2806
2807 for(;;) {
2808 schedule();
2809 if (signal_pending(current)) {
2810 rc = -ERESTARTSYS;
2811 break;
2812 }
2813
2814 /* get new irq counts */
2815 spin_lock_irqsave(&info->irq_spinlock,flags);
2816 cnow = info->icount;
2817 set_current_state(TASK_INTERRUPTIBLE);
2818 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2819
2820 /* if no change, wait aborted for some reason */
2821 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2822 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2823 rc = -EIO;
2824 break;
2825 }
2826
2827 /* check for change in caller specified modem input */
2828 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2829 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2830 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2831 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2832 rc = 0;
2833 break;
2834 }
2835
2836 cprev = cnow;
2837 }
2838 remove_wait_queue(&info->status_event_wait_q, &wait);
2839 set_current_state(TASK_RUNNING);
2840 return rc;
2841 }
2842
2843 /* return the state of the serial control and status signals
2844 */
2845 static int tiocmget(struct tty_struct *tty, struct file *file)
2846 {
2847 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2848 unsigned int result;
2849 unsigned long flags;
2850
2851 spin_lock_irqsave(&info->irq_spinlock,flags);
2852 usc_get_serial_signals(info);
2853 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2854
2855 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2856 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2857 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2858 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2859 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2860 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2861
2862 if (debug_level >= DEBUG_LEVEL_INFO)
2863 printk("%s(%d):%s tiocmget() value=%08X\n",
2864 __FILE__,__LINE__, info->device_name, result );
2865 return result;
2866 }
2867
2868 /* set modem control signals (DTR/RTS)
2869 */
2870 static int tiocmset(struct tty_struct *tty, struct file *file,
2871 unsigned int set, unsigned int clear)
2872 {
2873 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2874 unsigned long flags;
2875
2876 if (debug_level >= DEBUG_LEVEL_INFO)
2877 printk("%s(%d):%s tiocmset(%x,%x)\n",
2878 __FILE__,__LINE__,info->device_name, set, clear);
2879
2880 if (set & TIOCM_RTS)
2881 info->serial_signals |= SerialSignal_RTS;
2882 if (set & TIOCM_DTR)
2883 info->serial_signals |= SerialSignal_DTR;
2884 if (clear & TIOCM_RTS)
2885 info->serial_signals &= ~SerialSignal_RTS;
2886 if (clear & TIOCM_DTR)
2887 info->serial_signals &= ~SerialSignal_DTR;
2888
2889 spin_lock_irqsave(&info->irq_spinlock,flags);
2890 usc_set_serial_signals(info);
2891 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2892
2893 return 0;
2894 }
2895
2896 /* mgsl_break() Set or clear transmit break condition
2897 *
2898 * Arguments: tty pointer to tty instance data
2899 * break_state -1=set break condition, 0=clear
2900 * Return Value: error code
2901 */
2902 static int mgsl_break(struct tty_struct *tty, int break_state)
2903 {
2904 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
2905 unsigned long flags;
2906
2907 if (debug_level >= DEBUG_LEVEL_INFO)
2908 printk("%s(%d):mgsl_break(%s,%d)\n",
2909 __FILE__,__LINE__, info->device_name, break_state);
2910
2911 if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
2912 return -EINVAL;
2913
2914 spin_lock_irqsave(&info->irq_spinlock,flags);
2915 if (break_state == -1)
2916 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2917 else
2918 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2919 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2920 return 0;
2921
2922 } /* end of mgsl_break() */
2923
2924 /* mgsl_ioctl() Service an IOCTL request
2925 *
2926 * Arguments:
2927 *
2928 * tty pointer to tty instance data
2929 * file pointer to associated file object for device
2930 * cmd IOCTL command code
2931 * arg command argument/context
2932 *
2933 * Return Value: 0 if success, otherwise error code
2934 */
2935 static int mgsl_ioctl(struct tty_struct *tty, struct file * file,
2936 unsigned int cmd, unsigned long arg)
2937 {
2938 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
2939 int ret;
2940
2941 if (debug_level >= DEBUG_LEVEL_INFO)
2942 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2943 info->device_name, cmd );
2944
2945 if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
2946 return -ENODEV;
2947
2948 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2949 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
2950 if (tty->flags & (1 << TTY_IO_ERROR))
2951 return -EIO;
2952 }
2953
2954 lock_kernel();
2955 ret = mgsl_ioctl_common(info, cmd, arg);
2956 unlock_kernel();
2957 return ret;
2958 }
2959
2960 static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2961 {
2962 int error;
2963 struct mgsl_icount cnow; /* kernel counter temps */
2964 void __user *argp = (void __user *)arg;
2965 struct serial_icounter_struct __user *p_cuser; /* user space */
2966 unsigned long flags;
2967
2968 switch (cmd) {
2969 case MGSL_IOCGPARAMS:
2970 return mgsl_get_params(info, argp);
2971 case MGSL_IOCSPARAMS:
2972 return mgsl_set_params(info, argp);
2973 case MGSL_IOCGTXIDLE:
2974 return mgsl_get_txidle(info, argp);
2975 case MGSL_IOCSTXIDLE:
2976 return mgsl_set_txidle(info,(int)arg);
2977 case MGSL_IOCTXENABLE:
2978 return mgsl_txenable(info,(int)arg);
2979 case MGSL_IOCRXENABLE:
2980 return mgsl_rxenable(info,(int)arg);
2981 case MGSL_IOCTXABORT:
2982 return mgsl_txabort(info);
2983 case MGSL_IOCGSTATS:
2984 return mgsl_get_stats(info, argp);
2985 case MGSL_IOCWAITEVENT:
2986 return mgsl_wait_event(info, argp);
2987 case MGSL_IOCLOOPTXDONE:
2988 return mgsl_loopmode_send_done(info);
2989 /* Wait for modem input (DCD,RI,DSR,CTS) change
2990 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
2991 */
2992 case TIOCMIWAIT:
2993 return modem_input_wait(info,(int)arg);
2994
2995 /*
2996 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2997 * Return: write counters to the user passed counter struct
2998 * NB: both 1->0 and 0->1 transitions are counted except for
2999 * RI where only 0->1 is counted.
3000 */
3001 case TIOCGICOUNT:
3002 spin_lock_irqsave(&info->irq_spinlock,flags);
3003 cnow = info->icount;
3004 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3005 p_cuser = argp;
3006 PUT_USER(error,cnow.cts, &p_cuser->cts);
3007 if (error) return error;
3008 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
3009 if (error) return error;
3010 PUT_USER(error,cnow.rng, &p_cuser->rng);
3011 if (error) return error;
3012 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
3013 if (error) return error;
3014 PUT_USER(error,cnow.rx, &p_cuser->rx);
3015 if (error) return error;
3016 PUT_USER(error,cnow.tx, &p_cuser->tx);
3017 if (error) return error;
3018 PUT_USER(error,cnow.frame, &p_cuser->frame);
3019 if (error) return error;
3020 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
3021 if (error) return error;
3022 PUT_USER(error,cnow.parity, &p_cuser->parity);
3023 if (error) return error;
3024 PUT_USER(error,cnow.brk, &p_cuser->brk);
3025 if (error) return error;
3026 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
3027 if (error) return error;
3028 return 0;
3029 default:
3030 return -ENOIOCTLCMD;
3031 }
3032 return 0;
3033 }
3034
3035 /* mgsl_set_termios()
3036 *
3037 * Set new termios settings
3038 *
3039 * Arguments:
3040 *
3041 * tty pointer to tty structure
3042 * termios pointer to buffer to hold returned old termios
3043 *
3044 * Return Value: None
3045 */
3046 static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3047 {
3048 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
3049 unsigned long flags;
3050
3051 if (debug_level >= DEBUG_LEVEL_INFO)
3052 printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3053 tty->driver->name );
3054
3055 mgsl_change_params(info);
3056
3057 /* Handle transition to B0 status */
3058 if (old_termios->c_cflag & CBAUD &&
3059 !(tty->termios->c_cflag & CBAUD)) {
3060 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3061 spin_lock_irqsave(&info->irq_spinlock,flags);
3062 usc_set_serial_signals(info);
3063 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3064 }
3065
3066 /* Handle transition away from B0 status */
3067 if (!(old_termios->c_cflag & CBAUD) &&
3068 tty->termios->c_cflag & CBAUD) {
3069 info->serial_signals |= SerialSignal_DTR;
3070 if (!(tty->termios->c_cflag & CRTSCTS) ||
3071 !test_bit(TTY_THROTTLED, &tty->flags)) {
3072 info->serial_signals |= SerialSignal_RTS;
3073 }
3074 spin_lock_irqsave(&info->irq_spinlock,flags);
3075 usc_set_serial_signals(info);
3076 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3077 }
3078
3079 /* Handle turning off CRTSCTS */
3080 if (old_termios->c_cflag & CRTSCTS &&
3081 !(tty->termios->c_cflag & CRTSCTS)) {
3082 tty->hw_stopped = 0;
3083 mgsl_start(tty);
3084 }
3085
3086 } /* end of mgsl_set_termios() */
3087
3088 /* mgsl_close()
3089 *
3090 * Called when port is closed. Wait for remaining data to be
3091 * sent. Disable port and free resources.
3092 *
3093 * Arguments:
3094 *
3095 * tty pointer to open tty structure
3096 * filp pointer to open file object
3097 *
3098 * Return Value: None
3099 */
3100 static void mgsl_close(struct tty_struct *tty, struct file * filp)
3101 {
3102 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3103
3104 if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3105 return;
3106
3107 if (debug_level >= DEBUG_LEVEL_INFO)
3108 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3109 __FILE__,__LINE__, info->device_name, info->port.count);
3110
3111 if (!info->port.count)
3112 return;
3113
3114 if (tty_hung_up_p(filp))
3115 goto cleanup;
3116
3117 if ((tty->count == 1) && (info->port.count != 1)) {
3118 /*
3119 * tty->count is 1 and the tty structure will be freed.
3120 * info->port.count should be one in this case.
3121 * if it's not, correct it so that the port is shutdown.
3122 */
3123 printk("mgsl_close: bad refcount; tty->count is 1, "
3124 "info->port.count is %d\n", info->port.count);
3125 info->port.count = 1;
3126 }
3127
3128 info->port.count--;
3129
3130 /* if at least one open remaining, leave hardware active */
3131 if (info->port.count)
3132 goto cleanup;
3133
3134 info->port.flags |= ASYNC_CLOSING;
3135
3136 /* set tty->closing to notify line discipline to
3137 * only process XON/XOFF characters. Only the N_TTY
3138 * discipline appears to use this (ppp does not).
3139 */
3140 tty->closing = 1;
3141
3142 /* wait for transmit data to clear all layers */
3143
3144 if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE) {
3145 if (debug_level >= DEBUG_LEVEL_INFO)
3146 printk("%s(%d):mgsl_close(%s) calling tty_wait_until_sent\n",
3147 __FILE__,__LINE__, info->device_name );
3148 tty_wait_until_sent(tty, info->port.closing_wait);
3149 }
3150
3151 if (info->port.flags & ASYNC_INITIALIZED)
3152 mgsl_wait_until_sent(tty, info->timeout);
3153
3154 mgsl_flush_buffer(tty);
3155
3156 tty_ldisc_flush(tty);
3157
3158 shutdown(info);
3159
3160 tty->closing = 0;
3161 info->port.tty = NULL;
3162
3163 if (info->port.blocked_open) {
3164 if (info->port.close_delay) {
3165 msleep_interruptible(jiffies_to_msecs(info->port.close_delay));
3166 }
3167 wake_up_interruptible(&info->port.open_wait);
3168 }
3169
3170 info->port.flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
3171
3172 wake_up_interruptible(&info->port.close_wait);
3173
3174 cleanup:
3175 if (debug_level >= DEBUG_LEVEL_INFO)
3176 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3177 tty->driver->name, info->port.count);
3178
3179 } /* end of mgsl_close() */
3180
3181 /* mgsl_wait_until_sent()
3182 *
3183 * Wait until the transmitter is empty.
3184 *
3185 * Arguments:
3186 *
3187 * tty pointer to tty info structure
3188 * timeout time to wait for send completion
3189 *
3190 * Return Value: None
3191 */
3192 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3193 {
3194 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3195 unsigned long orig_jiffies, char_time;
3196
3197 if (!info )
3198 return;
3199
3200 if (debug_level >= DEBUG_LEVEL_INFO)
3201 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3202 __FILE__,__LINE__, info->device_name );
3203
3204 if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3205 return;
3206
3207 if (!(info->port.flags & ASYNC_INITIALIZED))
3208 goto exit;
3209
3210 orig_jiffies = jiffies;
3211
3212 /* Set check interval to 1/5 of estimated time to
3213 * send a character, and make it at least 1. The check
3214 * interval should also be less than the timeout.
3215 * Note: use tight timings here to satisfy the NIST-PCTS.
3216 */
3217
3218 lock_kernel();
3219 if ( info->params.data_rate ) {
3220 char_time = info->timeout/(32 * 5);
3221 if (!char_time)
3222 char_time++;
3223 } else
3224 char_time = 1;
3225
3226 if (timeout)
3227 char_time = min_t(unsigned long, char_time, timeout);
3228
3229 if ( info->params.mode == MGSL_MODE_HDLC ||
3230 info->params.mode == MGSL_MODE_RAW ) {
3231 while (info->tx_active) {
3232 msleep_interruptible(jiffies_to_msecs(char_time));
3233 if (signal_pending(current))
3234 break;
3235 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3236 break;
3237 }
3238 } else {
3239 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3240 info->tx_enabled) {
3241 msleep_interruptible(jiffies_to_msecs(char_time));
3242 if (signal_pending(current))
3243 break;
3244 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3245 break;
3246 }
3247 }
3248 unlock_kernel();
3249
3250 exit:
3251 if (debug_level >= DEBUG_LEVEL_INFO)
3252 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3253 __FILE__,__LINE__, info->device_name );
3254
3255 } /* end of mgsl_wait_until_sent() */
3256
3257 /* mgsl_hangup()
3258 *
3259 * Called by tty_hangup() when a hangup is signaled.
3260 * This is the same as to closing all open files for the port.
3261 *
3262 * Arguments: tty pointer to associated tty object
3263 * Return Value: None
3264 */
3265 static void mgsl_hangup(struct tty_struct *tty)
3266 {
3267 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3268
3269 if (debug_level >= DEBUG_LEVEL_INFO)
3270 printk("%s(%d):mgsl_hangup(%s)\n",
3271 __FILE__,__LINE__, info->device_name );
3272
3273 if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3274 return;
3275
3276 mgsl_flush_buffer(tty);
3277 shutdown(info);
3278
3279 info->port.count = 0;
3280 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
3281 info->port.tty = NULL;
3282
3283 wake_up_interruptible(&info->port.open_wait);
3284
3285 } /* end of mgsl_hangup() */
3286
3287 /* block_til_ready()
3288 *
3289 * Block the current process until the specified port
3290 * is ready to be opened.
3291 *
3292 * Arguments:
3293 *
3294 * tty pointer to tty info structure
3295 * filp pointer to open file object
3296 * info pointer to device instance data
3297 *
3298 * Return Value: 0 if success, otherwise error code
3299 */
3300 static int block_til_ready(struct tty_struct *tty, struct file * filp,
3301 struct mgsl_struct *info)
3302 {
3303 DECLARE_WAITQUEUE(wait, current);
3304 int retval;
3305 bool do_clocal = false;
3306 bool extra_count = false;
3307 unsigned long flags;
3308
3309 if (debug_level >= DEBUG_LEVEL_INFO)
3310 printk("%s(%d):block_til_ready on %s\n",
3311 __FILE__,__LINE__, tty->driver->name );
3312
3313 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3314 /* nonblock mode is set or port is not enabled */
3315 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3316 return 0;
3317 }
3318
3319 if (tty->termios->c_cflag & CLOCAL)
3320 do_clocal = true;
3321
3322 /* Wait for carrier detect and the line to become
3323 * free (i.e., not in use by the callout). While we are in
3324 * this loop, info->port.count is dropped by one, so that
3325 * mgsl_close() knows when to free things. We restore it upon
3326 * exit, either normal or abnormal.
3327 */
3328
3329 retval = 0;
3330 add_wait_queue(&info->port.open_wait, &wait);
3331
3332 if (debug_level >= DEBUG_LEVEL_INFO)
3333 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3334 __FILE__,__LINE__, tty->driver->name, info->port.count );
3335
3336 spin_lock_irqsave(&info->irq_spinlock, flags);
3337 if (!tty_hung_up_p(filp)) {
3338 extra_count = true;
3339 info->port.count--;
3340 }
3341 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3342 info->port.blocked_open++;
3343
3344 while (1) {
3345 if (tty->termios->c_cflag & CBAUD) {
3346 spin_lock_irqsave(&info->irq_spinlock,flags);
3347 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3348 usc_set_serial_signals(info);
3349 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3350 }
3351
3352 set_current_state(TASK_INTERRUPTIBLE);
3353
3354 if (tty_hung_up_p(filp) || !(info->port.flags & ASYNC_INITIALIZED)){
3355 retval = (info->port.flags & ASYNC_HUP_NOTIFY) ?
3356 -EAGAIN : -ERESTARTSYS;
3357 break;
3358 }
3359
3360 spin_lock_irqsave(&info->irq_spinlock,flags);
3361 usc_get_serial_signals(info);
3362 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3363
3364 if (!(info->port.flags & ASYNC_CLOSING) &&
3365 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3366 break;
3367 }
3368
3369 if (signal_pending(current)) {
3370 retval = -ERESTARTSYS;
3371 break;
3372 }
3373
3374 if (debug_level >= DEBUG_LEVEL_INFO)
3375 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3376 __FILE__,__LINE__, tty->driver->name, info->port.count );
3377
3378 schedule();
3379 }
3380
3381 set_current_state(TASK_RUNNING);
3382 remove_wait_queue(&info->port.open_wait, &wait);
3383
3384 if (extra_count)
3385 info->port.count++;
3386 info->port.blocked_open--;
3387
3388 if (debug_level >= DEBUG_LEVEL_INFO)
3389 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3390 __FILE__,__LINE__, tty->driver->name, info->port.count );
3391
3392 if (!retval)
3393 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3394
3395 return retval;
3396
3397 } /* end of block_til_ready() */
3398
3399 /* mgsl_open()
3400 *
3401 * Called when a port is opened. Init and enable port.
3402 * Perform serial-specific initialization for the tty structure.
3403 *
3404 * Arguments: tty pointer to tty info structure
3405 * filp associated file pointer
3406 *
3407 * Return Value: 0 if success, otherwise error code
3408 */
3409 static int mgsl_open(struct tty_struct *tty, struct file * filp)
3410 {
3411 struct mgsl_struct *info;
3412 int retval, line;
3413 unsigned long flags;
3414
3415 /* verify range of specified line number */
3416 line = tty->index;
3417 if ((line < 0) || (line >= mgsl_device_count)) {
3418 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3419 __FILE__,__LINE__,line);
3420 return -ENODEV;
3421 }
3422
3423 /* find the info structure for the specified line */
3424 info = mgsl_device_list;
3425 while(info && info->line != line)
3426 info = info->next_device;
3427 if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3428 return -ENODEV;
3429
3430 tty->driver_data = info;
3431 info->port.tty = tty;
3432
3433 if (debug_level >= DEBUG_LEVEL_INFO)
3434 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3435 __FILE__,__LINE__,tty->driver->name, info->port.count);
3436
3437 /* If port is closing, signal caller to try again */
3438 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
3439 if (info->port.flags & ASYNC_CLOSING)
3440 interruptible_sleep_on(&info->port.close_wait);
3441 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
3442 -EAGAIN : -ERESTARTSYS);
3443 goto cleanup;
3444 }
3445
3446 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3447
3448 spin_lock_irqsave(&info->netlock, flags);
3449 if (info->netcount) {
3450 retval = -EBUSY;
3451 spin_unlock_irqrestore(&info->netlock, flags);
3452 goto cleanup;
3453 }
3454 info->port.count++;
3455 spin_unlock_irqrestore(&info->netlock, flags);
3456
3457 if (info->port.count == 1) {
3458 /* 1st open on this device, init hardware */
3459 retval = startup(info);
3460 if (retval < 0)
3461 goto cleanup;
3462 }
3463
3464 retval = block_til_ready(tty, filp, info);
3465 if (retval) {
3466 if (debug_level >= DEBUG_LEVEL_INFO)
3467 printk("%s(%d):block_til_ready(%s) returned %d\n",
3468 __FILE__,__LINE__, info->device_name, retval);
3469 goto cleanup;
3470 }
3471
3472 if (debug_level >= DEBUG_LEVEL_INFO)
3473 printk("%s(%d):mgsl_open(%s) success\n",
3474 __FILE__,__LINE__, info->device_name);
3475 retval = 0;
3476
3477 cleanup:
3478 if (retval) {
3479 if (tty->count == 1)
3480 info->port.tty = NULL; /* tty layer will release tty struct */
3481 if(info->port.count)
3482 info->port.count--;
3483 }
3484
3485 return retval;
3486
3487 } /* end of mgsl_open() */
3488
3489 /*
3490 * /proc fs routines....
3491 */
3492
3493 static inline int line_info(char *buf, struct mgsl_struct *info)
3494 {
3495 char stat_buf[30];
3496 int ret;
3497 unsigned long flags;
3498
3499 if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3500 ret = sprintf(buf, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3501 info->device_name, info->io_base, info->irq_level,
3502 info->phys_memory_base, info->phys_lcr_base);
3503 } else {
3504 ret = sprintf(buf, "%s:(E)ISA io:%04X irq:%d dma:%d",
3505 info->device_name, info->io_base,
3506 info->irq_level, info->dma_level);
3507 }
3508
3509 /* output current serial signal states */
3510 spin_lock_irqsave(&info->irq_spinlock,flags);
3511 usc_get_serial_signals(info);
3512 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3513
3514 stat_buf[0] = 0;
3515 stat_buf[1] = 0;
3516 if (info->serial_signals & SerialSignal_RTS)
3517 strcat(stat_buf, "|RTS");
3518 if (info->serial_signals & SerialSignal_CTS)
3519 strcat(stat_buf, "|CTS");
3520 if (info->serial_signals & SerialSignal_DTR)
3521 strcat(stat_buf, "|DTR");
3522 if (info->serial_signals & SerialSignal_DSR)
3523 strcat(stat_buf, "|DSR");
3524 if (info->serial_signals & SerialSignal_DCD)
3525 strcat(stat_buf, "|CD");
3526 if (info->serial_signals & SerialSignal_RI)
3527 strcat(stat_buf, "|RI");
3528
3529 if (info->params.mode == MGSL_MODE_HDLC ||
3530 info->params.mode == MGSL_MODE_RAW ) {
3531 ret += sprintf(buf+ret, " HDLC txok:%d rxok:%d",
3532 info->icount.txok, info->icount.rxok);
3533 if (info->icount.txunder)
3534 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
3535 if (info->icount.txabort)
3536 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
3537 if (info->icount.rxshort)
3538 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
3539 if (info->icount.rxlong)
3540 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
3541 if (info->icount.rxover)
3542 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
3543 if (info->icount.rxcrc)
3544 ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
3545 } else {
3546 ret += sprintf(buf+ret, " ASYNC tx:%d rx:%d",
3547 info->icount.tx, info->icount.rx);
3548 if (info->icount.frame)
3549 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
3550 if (info->icount.parity)
3551 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
3552 if (info->icount.brk)
3553 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
3554 if (info->icount.overrun)
3555 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
3556 }
3557
3558 /* Append serial signal status to end */
3559 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
3560
3561 ret += sprintf(buf+ret, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3562 info->tx_active,info->bh_requested,info->bh_running,
3563 info->pending_bh);
3564
3565 spin_lock_irqsave(&info->irq_spinlock,flags);
3566 {
3567 u16 Tcsr = usc_InReg( info, TCSR );
3568 u16 Tdmr = usc_InDmaReg( info, TDMR );
3569 u16 Ticr = usc_InReg( info, TICR );
3570 u16 Rscr = usc_InReg( info, RCSR );
3571 u16 Rdmr = usc_InDmaReg( info, RDMR );
3572 u16 Ricr = usc_InReg( info, RICR );
3573 u16 Icr = usc_InReg( info, ICR );
3574 u16 Dccr = usc_InReg( info, DCCR );
3575 u16 Tmr = usc_InReg( info, TMR );
3576 u16 Tccr = usc_InReg( info, TCCR );
3577 u16 Ccar = inw( info->io_base + CCAR );
3578 ret += sprintf(buf+ret, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3579 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3580 Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3581 }
3582 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3583
3584 return ret;
3585
3586 } /* end of line_info() */
3587
3588 /* mgsl_read_proc()
3589 *
3590 * Called to print information about devices
3591 *
3592 * Arguments:
3593 * page page of memory to hold returned info
3594 * start
3595 * off
3596 * count
3597 * eof
3598 * data
3599 *
3600 * Return Value:
3601 */
3602 static int mgsl_read_proc(char *page, char **start, off_t off, int count,
3603 int *eof, void *data)
3604 {
3605 int len = 0, l;
3606 off_t begin = 0;
3607 struct mgsl_struct *info;
3608
3609 len += sprintf(page, "synclink driver:%s\n", driver_version);
3610
3611 info = mgsl_device_list;
3612 while( info ) {
3613 l = line_info(page + len, info);
3614 len += l;
3615 if (len+begin > off+count)
3616 goto done;
3617 if (len+begin < off) {
3618 begin += len;
3619 len = 0;
3620 }
3621 info = info->next_device;
3622 }
3623
3624 *eof = 1;
3625 done:
3626 if (off >= len+begin)
3627 return 0;
3628 *start = page + (off-begin);
3629 return ((count < begin+len-off) ? count : begin+len-off);
3630
3631 } /* end of mgsl_read_proc() */
3632
3633 /* mgsl_allocate_dma_buffers()
3634 *
3635 * Allocate and format DMA buffers (ISA adapter)
3636 * or format shared memory buffers (PCI adapter).
3637 *
3638 * Arguments: info pointer to device instance data
3639 * Return Value: 0 if success, otherwise error
3640 */
3641 static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3642 {
3643 unsigned short BuffersPerFrame;
3644
3645 info->last_mem_alloc = 0;
3646
3647 /* Calculate the number of DMA buffers necessary to hold the */
3648 /* largest allowable frame size. Note: If the max frame size is */
3649 /* not an even multiple of the DMA buffer size then we need to */
3650 /* round the buffer count per frame up one. */
3651
3652 BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3653 if ( info->max_frame_size % DMABUFFERSIZE )
3654 BuffersPerFrame++;
3655
3656 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3657 /*
3658 * The PCI adapter has 256KBytes of shared memory to use.
3659 * This is 64 PAGE_SIZE buffers.
3660 *
3661 * The first page is used for padding at this time so the
3662 * buffer list does not begin at offset 0 of the PCI
3663 * adapter's shared memory.
3664 *
3665 * The 2nd page is used for the buffer list. A 4K buffer
3666 * list can hold 128 DMA_BUFFER structures at 32 bytes
3667 * each.
3668 *
3669 * This leaves 62 4K pages.
3670 *
3671 * The next N pages are used for transmit frame(s). We
3672 * reserve enough 4K page blocks to hold the required
3673 * number of transmit dma buffers (num_tx_dma_buffers),
3674 * each of MaxFrameSize size.
3675 *
3676 * Of the remaining pages (62-N), determine how many can
3677 * be used to receive full MaxFrameSize inbound frames
3678 */
3679 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3680 info->rx_buffer_count = 62 - info->tx_buffer_count;
3681 } else {
3682 /* Calculate the number of PAGE_SIZE buffers needed for */
3683 /* receive and transmit DMA buffers. */
3684
3685
3686 /* Calculate the number of DMA buffers necessary to */
3687 /* hold 7 max size receive frames and one max size transmit frame. */
3688 /* The receive buffer count is bumped by one so we avoid an */
3689 /* End of List condition if all receive buffers are used when */
3690 /* using linked list DMA buffers. */
3691
3692 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3693 info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3694
3695 /*
3696 * limit total TxBuffers & RxBuffers to 62 4K total
3697 * (ala PCI Allocation)
3698 */
3699
3700 if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3701 info->rx_buffer_count = 62 - info->tx_buffer_count;
3702
3703 }
3704
3705 if ( debug_level >= DEBUG_LEVEL_INFO )
3706 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3707 __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3708
3709 if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3710 mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3711 mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
3712 mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
3713 mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3714 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3715 return -ENOMEM;
3716 }
3717
3718 mgsl_reset_rx_dma_buffers( info );
3719 mgsl_reset_tx_dma_buffers( info );
3720
3721 return 0;
3722
3723 } /* end of mgsl_allocate_dma_buffers() */
3724
3725 /*
3726 * mgsl_alloc_buffer_list_memory()
3727 *
3728 * Allocate a common DMA buffer for use as the
3729 * receive and transmit buffer lists.
3730 *
3731 * A buffer list is a set of buffer entries where each entry contains
3732 * a pointer to an actual buffer and a pointer to the next buffer entry
3733 * (plus some other info about the buffer).
3734 *
3735 * The buffer entries for a list are built to form a circular list so
3736 * that when the entire list has been traversed you start back at the
3737 * beginning.
3738 *
3739 * This function allocates memory for just the buffer entries.
3740 * The links (pointer to next entry) are filled in with the physical
3741 * address of the next entry so the adapter can navigate the list
3742 * using bus master DMA. The pointers to the actual buffers are filled
3743 * out later when the actual buffers are allocated.
3744 *
3745 * Arguments: info pointer to device instance data
3746 * Return Value: 0 if success, otherwise error
3747 */
3748 static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3749 {
3750 unsigned int i;
3751
3752 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3753 /* PCI adapter uses shared memory. */
3754 info->buffer_list = info->memory_base + info->last_mem_alloc;
3755 info->buffer_list_phys = info->last_mem_alloc;
3756 info->last_mem_alloc += BUFFERLISTSIZE;
3757 } else {
3758 /* ISA adapter uses system memory. */
3759 /* The buffer lists are allocated as a common buffer that both */
3760 /* the processor and adapter can access. This allows the driver to */
3761 /* inspect portions of the buffer while other portions are being */
3762 /* updated by the adapter using Bus Master DMA. */
3763
3764 info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
3765 if (info->buffer_list == NULL)
3766 return -ENOMEM;
3767 info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
3768 }
3769
3770 /* We got the memory for the buffer entry lists. */
3771 /* Initialize the memory block to all zeros. */
3772 memset( info->buffer_list, 0, BUFFERLISTSIZE );
3773
3774 /* Save virtual address pointers to the receive and */
3775 /* transmit buffer lists. (Receive 1st). These pointers will */
3776 /* be used by the processor to access the lists. */
3777 info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3778 info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3779 info->tx_buffer_list += info->rx_buffer_count;
3780
3781 /*
3782 * Build the links for the buffer entry lists such that
3783 * two circular lists are built. (Transmit and Receive).
3784 *
3785 * Note: the links are physical addresses
3786 * which are read by the adapter to determine the next
3787 * buffer entry to use.
3788 */
3789
3790 for ( i = 0; i < info->rx_buffer_count; i++ ) {
3791 /* calculate and store physical address of this buffer entry */
3792 info->rx_buffer_list[i].phys_entry =
3793 info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3794
3795 /* calculate and store physical address of */
3796 /* next entry in cirular list of entries */
3797
3798 info->rx_buffer_list[i].link = info->buffer_list_phys;
3799
3800 if ( i < info->rx_buffer_count - 1 )
3801 info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3802 }
3803
3804 for ( i = 0; i < info->tx_buffer_count; i++ ) {
3805 /* calculate and store physical address of this buffer entry */
3806 info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3807 ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3808
3809 /* calculate and store physical address of */
3810 /* next entry in cirular list of entries */
3811
3812 info->tx_buffer_list[i].link = info->buffer_list_phys +
3813 info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3814
3815 if ( i < info->tx_buffer_count - 1 )
3816 info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3817 }
3818
3819 return 0;
3820
3821 } /* end of mgsl_alloc_buffer_list_memory() */
3822
3823 /* Free DMA buffers allocated for use as the
3824 * receive and transmit buffer lists.
3825 * Warning:
3826 *
3827 * The data transfer buffers associated with the buffer list
3828 * MUST be freed before freeing the buffer list itself because
3829 * the buffer list contains the information necessary to free
3830 * the individual buffers!
3831 */
3832 static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3833 {
3834 if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
3835 dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
3836
3837 info->buffer_list = NULL;
3838 info->rx_buffer_list = NULL;
3839 info->tx_buffer_list = NULL;
3840
3841 } /* end of mgsl_free_buffer_list_memory() */
3842
3843 /*
3844 * mgsl_alloc_frame_memory()
3845 *
3846 * Allocate the frame DMA buffers used by the specified buffer list.
3847 * Each DMA buffer will be one memory page in size. This is necessary
3848 * because memory can fragment enough that it may be impossible
3849 * contiguous pages.
3850 *
3851 * Arguments:
3852 *
3853 * info pointer to device instance data
3854 * BufferList pointer to list of buffer entries
3855 * Buffercount count of buffer entries in buffer list
3856 *
3857 * Return Value: 0 if success, otherwise -ENOMEM
3858 */
3859 static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3860 {
3861 int i;
3862 u32 phys_addr;
3863
3864 /* Allocate page sized buffers for the receive buffer list */
3865
3866 for ( i = 0; i < Buffercount; i++ ) {
3867 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3868 /* PCI adapter uses shared memory buffers. */
3869 BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3870 phys_addr = info->last_mem_alloc;
3871 info->last_mem_alloc += DMABUFFERSIZE;
3872 } else {
3873 /* ISA adapter uses system memory. */
3874 BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
3875 if (BufferList[i].virt_addr == NULL)
3876 return -ENOMEM;
3877 phys_addr = (u32)(BufferList[i].dma_addr);
3878 }
3879 BufferList[i].phys_addr = phys_addr;
3880 }
3881
3882 return 0;
3883
3884 } /* end of mgsl_alloc_frame_memory() */
3885
3886 /*
3887 * mgsl_free_frame_memory()
3888 *
3889 * Free the buffers associated with
3890 * each buffer entry of a buffer list.
3891 *
3892 * Arguments:
3893 *
3894 * info pointer to device instance data
3895 * BufferList pointer to list of buffer entries
3896 * Buffercount count of buffer entries in buffer list
3897 *
3898 * Return Value: None
3899 */
3900 static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3901 {
3902 int i;
3903
3904 if ( BufferList ) {
3905 for ( i = 0 ; i < Buffercount ; i++ ) {
3906 if ( BufferList[i].virt_addr ) {
3907 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3908 dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
3909 BufferList[i].virt_addr = NULL;
3910 }
3911 }
3912 }
3913
3914 } /* end of mgsl_free_frame_memory() */
3915
3916 /* mgsl_free_dma_buffers()
3917 *
3918 * Free DMA buffers
3919 *
3920 * Arguments: info pointer to device instance data
3921 * Return Value: None
3922 */
3923 static void mgsl_free_dma_buffers( struct mgsl_struct *info )
3924 {
3925 mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3926 mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3927 mgsl_free_buffer_list_memory( info );
3928
3929 } /* end of mgsl_free_dma_buffers() */
3930
3931
3932 /*
3933 * mgsl_alloc_intermediate_rxbuffer_memory()
3934 *
3935 * Allocate a buffer large enough to hold max_frame_size. This buffer
3936 * is used to pass an assembled frame to the line discipline.
3937 *
3938 * Arguments:
3939 *
3940 * info pointer to device instance data
3941 *
3942 * Return Value: 0 if success, otherwise -ENOMEM
3943 */
3944 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3945 {
3946 info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
3947 if ( info->intermediate_rxbuffer == NULL )
3948 return -ENOMEM;
3949
3950 return 0;
3951
3952 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3953
3954 /*
3955 * mgsl_free_intermediate_rxbuffer_memory()
3956 *
3957 *
3958 * Arguments:
3959 *
3960 * info pointer to device instance data
3961 *
3962 * Return Value: None
3963 */
3964 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3965 {
3966 kfree(info->intermediate_rxbuffer);
3967 info->intermediate_rxbuffer = NULL;
3968
3969 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
3970
3971 /*
3972 * mgsl_alloc_intermediate_txbuffer_memory()
3973 *
3974 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3975 * This buffer is used to load transmit frames into the adapter's dma transfer
3976 * buffers when there is sufficient space.
3977 *
3978 * Arguments:
3979 *
3980 * info pointer to device instance data
3981 *
3982 * Return Value: 0 if success, otherwise -ENOMEM
3983 */
3984 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
3985 {
3986 int i;
3987
3988 if ( debug_level >= DEBUG_LEVEL_INFO )
3989 printk("%s %s(%d) allocating %d tx holding buffers\n",
3990 info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
3991
3992 memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
3993
3994 for ( i=0; i<info->num_tx_holding_buffers; ++i) {
3995 info->tx_holding_buffers[i].buffer =
3996 kmalloc(info->max_frame_size, GFP_KERNEL);
3997 if (info->tx_holding_buffers[i].buffer == NULL) {
3998 for (--i; i >= 0; i--) {
3999 kfree(info->tx_holding_buffers[i].buffer);
4000 info->tx_holding_buffers[i].buffer = NULL;
4001 }
4002 return -ENOMEM;
4003 }
4004 }
4005
4006 return 0;
4007
4008 } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
4009
4010 /*
4011 * mgsl_free_intermediate_txbuffer_memory()
4012 *
4013 *
4014 * Arguments:
4015 *
4016 * info pointer to device instance data
4017 *
4018 * Return Value: None
4019 */
4020 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
4021 {
4022 int i;
4023
4024 for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
4025 kfree(info->tx_holding_buffers[i].buffer);
4026 info->tx_holding_buffers[i].buffer = NULL;
4027 }
4028
4029 info->get_tx_holding_index = 0;
4030 info->put_tx_holding_index = 0;
4031 info->tx_holding_count = 0;
4032
4033 } /* end of mgsl_free_intermediate_txbuffer_memory() */
4034
4035
4036 /*
4037 * load_next_tx_holding_buffer()
4038 *
4039 * attempts to load the next buffered tx request into the
4040 * tx dma buffers
4041 *
4042 * Arguments:
4043 *
4044 * info pointer to device instance data
4045 *
4046 * Return Value: true if next buffered tx request loaded
4047 * into adapter's tx dma buffer,
4048 * false otherwise
4049 */
4050 static bool load_next_tx_holding_buffer(struct mgsl_struct *info)
4051 {
4052 bool ret = false;
4053
4054 if ( info->tx_holding_count ) {
4055 /* determine if we have enough tx dma buffers
4056 * to accommodate the next tx frame
4057 */
4058 struct tx_holding_buffer *ptx =
4059 &info->tx_holding_buffers[info->get_tx_holding_index];
4060 int num_free = num_free_tx_dma_buffers(info);
4061 int num_needed = ptx->buffer_size / DMABUFFERSIZE;
4062 if ( ptx->buffer_size % DMABUFFERSIZE )
4063 ++num_needed;
4064
4065 if (num_needed <= num_free) {
4066 info->xmit_cnt = ptx->buffer_size;
4067 mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
4068
4069 --info->tx_holding_count;
4070 if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
4071 info->get_tx_holding_index=0;
4072
4073 /* restart transmit timer */
4074 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4075
4076 ret = true;
4077 }
4078 }
4079
4080 return ret;
4081 }
4082
4083 /*
4084 * save_tx_buffer_request()
4085 *
4086 * attempt to store transmit frame request for later transmission
4087 *
4088 * Arguments:
4089 *
4090 * info pointer to device instance data
4091 * Buffer pointer to buffer containing frame to load
4092 * BufferSize size in bytes of frame in Buffer
4093 *
4094 * Return Value: 1 if able to store, 0 otherwise
4095 */
4096 static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4097 {
4098 struct tx_holding_buffer *ptx;
4099
4100 if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4101 return 0; /* all buffers in use */
4102 }
4103
4104 ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4105 ptx->buffer_size = BufferSize;
4106 memcpy( ptx->buffer, Buffer, BufferSize);
4107
4108 ++info->tx_holding_count;
4109 if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4110 info->put_tx_holding_index=0;
4111
4112 return 1;
4113 }
4114
4115 static int mgsl_claim_resources(struct mgsl_struct *info)
4116 {
4117 if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4118 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4119 __FILE__,__LINE__,info->device_name, info->io_base);
4120 return -ENODEV;
4121 }
4122 info->io_addr_requested = true;
4123
4124 if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4125 info->device_name, info ) < 0 ) {
4126 printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4127 __FILE__,__LINE__,info->device_name, info->irq_level );
4128 goto errout;
4129 }
4130 info->irq_requested = true;
4131
4132 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4133 if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4134 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4135 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4136 goto errout;
4137 }
4138 info->shared_mem_requested = true;
4139 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4140 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4141 __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4142 goto errout;
4143 }
4144 info->lcr_mem_requested = true;
4145
4146 info->memory_base = ioremap_nocache(info->phys_memory_base,
4147 0x40000);
4148 if (!info->memory_base) {
4149 printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4150 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4151 goto errout;
4152 }
4153
4154 if ( !mgsl_memory_test(info) ) {
4155 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4156 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4157 goto errout;
4158 }
4159
4160 info->lcr_base = ioremap_nocache(info->phys_lcr_base,
4161 PAGE_SIZE);
4162 if (!info->lcr_base) {
4163 printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4164 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4165 goto errout;
4166 }
4167 info->lcr_base += info->lcr_offset;
4168
4169 } else {
4170 /* claim DMA channel */
4171
4172 if (request_dma(info->dma_level,info->device_name) < 0){
4173 printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4174 __FILE__,__LINE__,info->device_name, info->dma_level );
4175 mgsl_release_resources( info );
4176 return -ENODEV;
4177 }
4178 info->dma_requested = true;
4179
4180 /* ISA adapter uses bus master DMA */
4181 set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4182 enable_dma(info->dma_level);
4183 }
4184
4185 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4186 printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4187 __FILE__,__LINE__,info->device_name, info->dma_level );
4188 goto errout;
4189 }
4190
4191 return 0;
4192 errout:
4193 mgsl_release_resources(info);
4194 return -ENODEV;
4195
4196 } /* end of mgsl_claim_resources() */
4197
4198 static void mgsl_release_resources(struct mgsl_struct *info)
4199 {
4200 if ( debug_level >= DEBUG_LEVEL_INFO )
4201 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4202 __FILE__,__LINE__,info->device_name );
4203
4204 if ( info->irq_requested ) {
4205 free_irq(info->irq_level, info);
4206 info->irq_requested = false;
4207 }
4208 if ( info->dma_requested ) {
4209 disable_dma(info->dma_level);
4210 free_dma(info->dma_level);
4211 info->dma_requested = false;
4212 }
4213 mgsl_free_dma_buffers(info);
4214 mgsl_free_intermediate_rxbuffer_memory(info);
4215 mgsl_free_intermediate_txbuffer_memory(info);
4216
4217 if ( info->io_addr_requested ) {
4218 release_region(info->io_base,info->io_addr_size);
4219 info->io_addr_requested = false;
4220 }
4221 if ( info->shared_mem_requested ) {
4222 release_mem_region(info->phys_memory_base,0x40000);
4223 info->shared_mem_requested = false;
4224 }
4225 if ( info->lcr_mem_requested ) {
4226 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
4227 info->lcr_mem_requested = false;
4228 }
4229 if (info->memory_base){
4230 iounmap(info->memory_base);
4231 info->memory_base = NULL;
4232 }
4233 if (info->lcr_base){
4234 iounmap(info->lcr_base - info->lcr_offset);
4235 info->lcr_base = NULL;
4236 }
4237
4238 if ( debug_level >= DEBUG_LEVEL_INFO )
4239 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4240 __FILE__,__LINE__,info->device_name );
4241
4242 } /* end of mgsl_release_resources() */
4243
4244 /* mgsl_add_device()
4245 *
4246 * Add the specified device instance data structure to the
4247 * global linked list of devices and increment the device count.
4248 *
4249 * Arguments: info pointer to device instance data
4250 * Return Value: None
4251 */
4252 static void mgsl_add_device( struct mgsl_struct *info )
4253 {
4254 info->next_device = NULL;
4255 info->line = mgsl_device_count;
4256 sprintf(info->device_name,"ttySL%d",info->line);
4257
4258 if (info->line < MAX_TOTAL_DEVICES) {
4259 if (maxframe[info->line])
4260 info->max_frame_size = maxframe[info->line];
4261 info->dosyncppp = dosyncppp[info->line];
4262
4263 if (txdmabufs[info->line]) {
4264 info->num_tx_dma_buffers = txdmabufs[info->line];
4265 if (info->num_tx_dma_buffers < 1)
4266 info->num_tx_dma_buffers = 1;
4267 }
4268
4269 if (txholdbufs[info->line]) {
4270 info->num_tx_holding_buffers = txholdbufs[info->line];
4271 if (info->num_tx_holding_buffers < 1)
4272 info->num_tx_holding_buffers = 1;
4273 else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4274 info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4275 }
4276 }
4277
4278 mgsl_device_count++;
4279
4280 if ( !mgsl_device_list )
4281 mgsl_device_list = info;
4282 else {
4283 struct mgsl_struct *current_dev = mgsl_device_list;
4284 while( current_dev->next_device )
4285 current_dev = current_dev->next_device;
4286 current_dev->next_device = info;
4287 }
4288
4289 if ( info->max_frame_size < 4096 )
4290 info->max_frame_size = 4096;
4291 else if ( info->max_frame_size > 65535 )
4292 info->max_frame_size = 65535;
4293
4294 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4295 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4296 info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4297 info->phys_memory_base, info->phys_lcr_base,
4298 info->max_frame_size );
4299 } else {
4300 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4301 info->device_name, info->io_base, info->irq_level, info->dma_level,
4302 info->max_frame_size );
4303 }
4304
4305 #if SYNCLINK_GENERIC_HDLC
4306 hdlcdev_init(info);
4307 #endif
4308
4309 } /* end of mgsl_add_device() */
4310
4311 /* mgsl_allocate_device()
4312 *
4313 * Allocate and initialize a device instance structure
4314 *
4315 * Arguments: none
4316 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4317 */
4318 static struct mgsl_struct* mgsl_allocate_device(void)
4319 {
4320 struct mgsl_struct *info;
4321
4322 info = kzalloc(sizeof(struct mgsl_struct),
4323 GFP_KERNEL);
4324
4325 if (!info) {
4326 printk("Error can't allocate device instance data\n");
4327 } else {
4328 tty_port_init(&info->port);
4329 info->magic = MGSL_MAGIC;
4330 INIT_WORK(&info->task, mgsl_bh_handler);
4331 info->max_frame_size = 4096;
4332 info->port.close_delay = 5*HZ/10;
4333 info->port.closing_wait = 30*HZ;
4334 init_waitqueue_head(&info->status_event_wait_q);
4335 init_waitqueue_head(&info->event_wait_q);
4336 spin_lock_init(&info->irq_spinlock);
4337 spin_lock_init(&info->netlock);
4338 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4339 info->idle_mode = HDLC_TXIDLE_FLAGS;
4340 info->num_tx_dma_buffers = 1;
4341 info->num_tx_holding_buffers = 0;
4342 }
4343
4344 return info;
4345
4346 } /* end of mgsl_allocate_device()*/
4347
4348 static const struct tty_operations mgsl_ops = {
4349 .open = mgsl_open,
4350 .close = mgsl_close,
4351 .write = mgsl_write,
4352 .put_char = mgsl_put_char,
4353 .flush_chars = mgsl_flush_chars,
4354 .write_room = mgsl_write_room,
4355 .chars_in_buffer = mgsl_chars_in_buffer,
4356 .flush_buffer = mgsl_flush_buffer,
4357 .ioctl = mgsl_ioctl,
4358 .throttle = mgsl_throttle,
4359 .unthrottle = mgsl_unthrottle,
4360 .send_xchar = mgsl_send_xchar,
4361 .break_ctl = mgsl_break,
4362 .wait_until_sent = mgsl_wait_until_sent,
4363 .read_proc = mgsl_read_proc,
4364 .set_termios = mgsl_set_termios,
4365 .stop = mgsl_stop,
4366 .start = mgsl_start,
4367 .hangup = mgsl_hangup,
4368 .tiocmget = tiocmget,
4369 .tiocmset = tiocmset,
4370 };
4371
4372 /*
4373 * perform tty device initialization
4374 */
4375 static int mgsl_init_tty(void)
4376 {
4377 int rc;
4378
4379 serial_driver = alloc_tty_driver(128);
4380 if (!serial_driver)
4381 return -ENOMEM;
4382
4383 serial_driver->owner = THIS_MODULE;
4384 serial_driver->driver_name = "synclink";
4385 serial_driver->name = "ttySL";
4386 serial_driver->major = ttymajor;
4387 serial_driver->minor_start = 64;
4388 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4389 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4390 serial_driver->init_termios = tty_std_termios;
4391 serial_driver->init_termios.c_cflag =
4392 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4393 serial_driver->init_termios.c_ispeed = 9600;
4394 serial_driver->init_termios.c_ospeed = 9600;
4395 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4396 tty_set_operations(serial_driver, &mgsl_ops);
4397 if ((rc = tty_register_driver(serial_driver)) < 0) {
4398 printk("%s(%d):Couldn't register serial driver\n",
4399 __FILE__,__LINE__);
4400 put_tty_driver(serial_driver);
4401 serial_driver = NULL;
4402 return rc;
4403 }
4404
4405 printk("%s %s, tty major#%d\n",
4406 driver_name, driver_version,
4407 serial_driver->major);
4408 return 0;
4409 }
4410
4411 /* enumerate user specified ISA adapters
4412 */
4413 static void mgsl_enum_isa_devices(void)
4414 {
4415 struct mgsl_struct *info;
4416 int i;
4417
4418 /* Check for user specified ISA devices */
4419
4420 for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4421 if ( debug_level >= DEBUG_LEVEL_INFO )
4422 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4423 io[i], irq[i], dma[i] );
4424
4425 info = mgsl_allocate_device();
4426 if ( !info ) {
4427 /* error allocating device instance data */
4428 if ( debug_level >= DEBUG_LEVEL_ERROR )
4429 printk( "can't allocate device instance data.\n");
4430 continue;
4431 }
4432
4433 /* Copy user configuration info to device instance data */
4434 info->io_base = (unsigned int)io[i];
4435 info->irq_level = (unsigned int)irq[i];
4436 info->irq_level = irq_canonicalize(info->irq_level);
4437 info->dma_level = (unsigned int)dma[i];
4438 info->bus_type = MGSL_BUS_TYPE_ISA;
4439 info->io_addr_size = 16;
4440 info->irq_flags = 0;
4441
4442 mgsl_add_device( info );
4443 }
4444 }
4445
4446 static void synclink_cleanup(void)
4447 {
4448 int rc;
4449 struct mgsl_struct *info;
4450 struct mgsl_struct *tmp;
4451
4452 printk("Unloading %s: %s\n", driver_name, driver_version);
4453
4454 if (serial_driver) {
4455 if ((rc = tty_unregister_driver(serial_driver)))
4456 printk("%s(%d) failed to unregister tty driver err=%d\n",
4457 __FILE__,__LINE__,rc);
4458 put_tty_driver(serial_driver);
4459 }
4460
4461 info = mgsl_device_list;
4462 while(info) {
4463 #if SYNCLINK_GENERIC_HDLC
4464 hdlcdev_exit(info);
4465 #endif
4466 mgsl_release_resources(info);
4467 tmp = info;
4468 info = info->next_device;
4469 kfree(tmp);
4470 }
4471
4472 if (pci_registered)
4473 pci_unregister_driver(&synclink_pci_driver);
4474 }
4475
4476 static int __init synclink_init(void)
4477 {
4478 int rc;
4479
4480 if (break_on_load) {
4481 mgsl_get_text_ptr();
4482 BREAKPOINT();
4483 }
4484
4485 printk("%s %s\n", driver_name, driver_version);
4486
4487 mgsl_enum_isa_devices();
4488 if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4489 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4490 else
4491 pci_registered = true;
4492
4493 if ((rc = mgsl_init_tty()) < 0)
4494 goto error;
4495
4496 return 0;
4497
4498 error:
4499 synclink_cleanup();
4500 return rc;
4501 }
4502
4503 static void __exit synclink_exit(void)
4504 {
4505 synclink_cleanup();
4506 }
4507
4508 module_init(synclink_init);
4509 module_exit(synclink_exit);
4510
4511 /*
4512 * usc_RTCmd()
4513 *
4514 * Issue a USC Receive/Transmit command to the
4515 * Channel Command/Address Register (CCAR).
4516 *
4517 * Notes:
4518 *
4519 * The command is encoded in the most significant 5 bits <15..11>
4520 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4521 * and Bits <6..0> must be written as zeros.
4522 *
4523 * Arguments:
4524 *
4525 * info pointer to device information structure
4526 * Cmd command mask (use symbolic macros)
4527 *
4528 * Return Value:
4529 *
4530 * None
4531 */
4532 static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4533 {
4534 /* output command to CCAR in bits <15..11> */
4535 /* preserve bits <10..7>, bits <6..0> must be zero */
4536
4537 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4538
4539 /* Read to flush write to CCAR */
4540 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4541 inw( info->io_base + CCAR );
4542
4543 } /* end of usc_RTCmd() */
4544
4545 /*
4546 * usc_DmaCmd()
4547 *
4548 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4549 *
4550 * Arguments:
4551 *
4552 * info pointer to device information structure
4553 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4554 *
4555 * Return Value:
4556 *
4557 * None
4558 */
4559 static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4560 {
4561 /* write command mask to DCAR */
4562 outw( Cmd + info->mbre_bit, info->io_base );
4563
4564 /* Read to flush write to DCAR */
4565 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4566 inw( info->io_base );
4567
4568 } /* end of usc_DmaCmd() */
4569
4570 /*
4571 * usc_OutDmaReg()
4572 *
4573 * Write a 16-bit value to a USC DMA register
4574 *
4575 * Arguments:
4576 *
4577 * info pointer to device info structure
4578 * RegAddr register address (number) for write
4579 * RegValue 16-bit value to write to register
4580 *
4581 * Return Value:
4582 *
4583 * None
4584 *
4585 */
4586 static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4587 {
4588 /* Note: The DCAR is located at the adapter base address */
4589 /* Note: must preserve state of BIT8 in DCAR */
4590
4591 outw( RegAddr + info->mbre_bit, info->io_base );
4592 outw( RegValue, info->io_base );
4593
4594 /* Read to flush write to DCAR */
4595 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4596 inw( info->io_base );
4597
4598 } /* end of usc_OutDmaReg() */
4599
4600 /*
4601 * usc_InDmaReg()
4602 *
4603 * Read a 16-bit value from a DMA register
4604 *
4605 * Arguments:
4606 *
4607 * info pointer to device info structure
4608 * RegAddr register address (number) to read from
4609 *
4610 * Return Value:
4611 *
4612 * The 16-bit value read from register
4613 *
4614 */
4615 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4616 {
4617 /* Note: The DCAR is located at the adapter base address */
4618 /* Note: must preserve state of BIT8 in DCAR */
4619
4620 outw( RegAddr + info->mbre_bit, info->io_base );
4621 return inw( info->io_base );
4622
4623 } /* end of usc_InDmaReg() */
4624
4625 /*
4626 *
4627 * usc_OutReg()
4628 *
4629 * Write a 16-bit value to a USC serial channel register
4630 *
4631 * Arguments:
4632 *
4633 * info pointer to device info structure
4634 * RegAddr register address (number) to write to
4635 * RegValue 16-bit value to write to register
4636 *
4637 * Return Value:
4638 *
4639 * None
4640 *
4641 */
4642 static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4643 {
4644 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4645 outw( RegValue, info->io_base + CCAR );
4646
4647 /* Read to flush write to CCAR */
4648 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4649 inw( info->io_base + CCAR );
4650
4651 } /* end of usc_OutReg() */
4652
4653 /*
4654 * usc_InReg()
4655 *
4656 * Reads a 16-bit value from a USC serial channel register
4657 *
4658 * Arguments:
4659 *
4660 * info pointer to device extension
4661 * RegAddr register address (number) to read from
4662 *
4663 * Return Value:
4664 *
4665 * 16-bit value read from register
4666 */
4667 static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4668 {
4669 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4670 return inw( info->io_base + CCAR );
4671
4672 } /* end of usc_InReg() */
4673
4674 /* usc_set_sdlc_mode()
4675 *
4676 * Set up the adapter for SDLC DMA communications.
4677 *
4678 * Arguments: info pointer to device instance data
4679 * Return Value: NONE
4680 */
4681 static void usc_set_sdlc_mode( struct mgsl_struct *info )
4682 {
4683 u16 RegValue;
4684 bool PreSL1660;
4685
4686 /*
4687 * determine if the IUSC on the adapter is pre-SL1660. If
4688 * not, take advantage of the UnderWait feature of more
4689 * modern chips. If an underrun occurs and this bit is set,
4690 * the transmitter will idle the programmed idle pattern
4691 * until the driver has time to service the underrun. Otherwise,
4692 * the dma controller may get the cycles previously requested
4693 * and begin transmitting queued tx data.
4694 */
4695 usc_OutReg(info,TMCR,0x1f);
4696 RegValue=usc_InReg(info,TMDR);
4697 PreSL1660 = (RegValue == IUSC_PRE_SL1660);
4698
4699 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4700 {
4701 /*
4702 ** Channel Mode Register (CMR)
4703 **
4704 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4705 ** <13> 0 0 = Transmit Disabled (initially)
4706 ** <12> 0 1 = Consecutive Idles share common 0
4707 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4708 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4709 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4710 **
4711 ** 1000 1110 0000 0110 = 0x8e06
4712 */
4713 RegValue = 0x8e06;
4714
4715 /*--------------------------------------------------
4716 * ignore user options for UnderRun Actions and
4717 * preambles
4718 *--------------------------------------------------*/
4719 }
4720 else
4721 {
4722 /* Channel mode Register (CMR)
4723 *
4724 * <15..14> 00 Tx Sub modes, Underrun Action
4725 * <13> 0 1 = Send Preamble before opening flag
4726 * <12> 0 1 = Consecutive Idles share common 0
4727 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4728 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4729 * <3..0> 0110 Receiver mode = HDLC/SDLC
4730 *
4731 * 0000 0110 0000 0110 = 0x0606
4732 */
4733 if (info->params.mode == MGSL_MODE_RAW) {
4734 RegValue = 0x0001; /* Set Receive mode = external sync */
4735
4736 usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */
4737 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4738
4739 /*
4740 * TxSubMode:
4741 * CMR <15> 0 Don't send CRC on Tx Underrun
4742 * CMR <14> x undefined
4743 * CMR <13> 0 Send preamble before openning sync
4744 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4745 *
4746 * TxMode:
4747 * CMR <11-8) 0100 MonoSync
4748 *
4749 * 0x00 0100 xxxx xxxx 04xx
4750 */
4751 RegValue |= 0x0400;
4752 }
4753 else {
4754
4755 RegValue = 0x0606;
4756
4757 if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4758 RegValue |= BIT14;
4759 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4760 RegValue |= BIT15;
4761 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4762 RegValue |= BIT15 + BIT14;
4763 }
4764
4765 if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4766 RegValue |= BIT13;
4767 }
4768
4769 if ( info->params.mode == MGSL_MODE_HDLC &&
4770 (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4771 RegValue |= BIT12;
4772
4773 if ( info->params.addr_filter != 0xff )
4774 {
4775 /* set up receive address filtering */
4776 usc_OutReg( info, RSR, info->params.addr_filter );
4777 RegValue |= BIT4;
4778 }
4779
4780 usc_OutReg( info, CMR, RegValue );
4781 info->cmr_value = RegValue;
4782
4783 /* Receiver mode Register (RMR)
4784 *
4785 * <15..13> 000 encoding
4786 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4787 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4788 * <9> 0 1 = Include Receive chars in CRC
4789 * <8> 1 1 = Use Abort/PE bit as abort indicator
4790 * <7..6> 00 Even parity
4791 * <5> 0 parity disabled
4792 * <4..2> 000 Receive Char Length = 8 bits
4793 * <1..0> 00 Disable Receiver
4794 *
4795 * 0000 0101 0000 0000 = 0x0500
4796 */
4797
4798 RegValue = 0x0500;
4799
4800 switch ( info->params.encoding ) {
4801 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4802 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4803 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4804 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4805 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4806 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4807 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4808 }
4809
4810 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4811 RegValue |= BIT9;
4812 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4813 RegValue |= ( BIT12 | BIT10 | BIT9 );
4814
4815 usc_OutReg( info, RMR, RegValue );
4816
4817 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4818 /* When an opening flag of an SDLC frame is recognized the */
4819 /* Receive Character count (RCC) is loaded with the value in */
4820 /* RCLR. The RCC is decremented for each received byte. The */
4821 /* value of RCC is stored after the closing flag of the frame */
4822 /* allowing the frame size to be computed. */
4823
4824 usc_OutReg( info, RCLR, RCLRVALUE );
4825
4826 usc_RCmd( info, RCmd_SelectRicrdma_level );
4827
4828 /* Receive Interrupt Control Register (RICR)
4829 *
4830 * <15..8> ? RxFIFO DMA Request Level
4831 * <7> 0 Exited Hunt IA (Interrupt Arm)
4832 * <6> 0 Idle Received IA
4833 * <5> 0 Break/Abort IA
4834 * <4> 0 Rx Bound IA
4835 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4836 * <2> 0 Abort/PE IA
4837 * <1> 1 Rx Overrun IA
4838 * <0> 0 Select TC0 value for readback
4839 *
4840 * 0000 0000 0000 1000 = 0x000a
4841 */
4842
4843 /* Carry over the Exit Hunt and Idle Received bits */
4844 /* in case they have been armed by usc_ArmEvents. */
4845
4846 RegValue = usc_InReg( info, RICR ) & 0xc0;
4847
4848 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4849 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4850 else
4851 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4852
4853 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4854
4855 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4856 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4857
4858 /* Transmit mode Register (TMR)
4859 *
4860 * <15..13> 000 encoding
4861 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4862 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4863 * <9> 0 1 = Tx CRC Enabled
4864 * <8> 0 1 = Append CRC to end of transmit frame
4865 * <7..6> 00 Transmit parity Even
4866 * <5> 0 Transmit parity Disabled
4867 * <4..2> 000 Tx Char Length = 8 bits
4868 * <1..0> 00 Disable Transmitter
4869 *
4870 * 0000 0100 0000 0000 = 0x0400
4871 */
4872
4873 RegValue = 0x0400;
4874
4875 switch ( info->params.encoding ) {
4876 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4877 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4878 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4879 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4880 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4881 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4882 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4883 }
4884
4885 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4886 RegValue |= BIT9 + BIT8;
4887 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4888 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4889
4890 usc_OutReg( info, TMR, RegValue );
4891
4892 usc_set_txidle( info );
4893
4894
4895 usc_TCmd( info, TCmd_SelectTicrdma_level );
4896
4897 /* Transmit Interrupt Control Register (TICR)
4898 *
4899 * <15..8> ? Transmit FIFO DMA Level
4900 * <7> 0 Present IA (Interrupt Arm)
4901 * <6> 0 Idle Sent IA
4902 * <5> 1 Abort Sent IA
4903 * <4> 1 EOF/EOM Sent IA
4904 * <3> 0 CRC Sent IA
4905 * <2> 1 1 = Wait for SW Trigger to Start Frame
4906 * <1> 1 Tx Underrun IA
4907 * <0> 0 TC0 constant on read back
4908 *
4909 * 0000 0000 0011 0110 = 0x0036
4910 */
4911
4912 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4913 usc_OutReg( info, TICR, 0x0736 );
4914 else
4915 usc_OutReg( info, TICR, 0x1436 );
4916
4917 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4918 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4919
4920 /*
4921 ** Transmit Command/Status Register (TCSR)
4922 **
4923 ** <15..12> 0000 TCmd
4924 ** <11> 0/1 UnderWait
4925 ** <10..08> 000 TxIdle
4926 ** <7> x PreSent
4927 ** <6> x IdleSent
4928 ** <5> x AbortSent
4929 ** <4> x EOF/EOM Sent
4930 ** <3> x CRC Sent
4931 ** <2> x All Sent
4932 ** <1> x TxUnder
4933 ** <0> x TxEmpty
4934 **
4935 ** 0000 0000 0000 0000 = 0x0000
4936 */
4937 info->tcsr_value = 0;
4938
4939 if ( !PreSL1660 )
4940 info->tcsr_value |= TCSR_UNDERWAIT;
4941
4942 usc_OutReg( info, TCSR, info->tcsr_value );
4943
4944 /* Clock mode Control Register (CMCR)
4945 *
4946 * <15..14> 00 counter 1 Source = Disabled
4947 * <13..12> 00 counter 0 Source = Disabled
4948 * <11..10> 11 BRG1 Input is TxC Pin
4949 * <9..8> 11 BRG0 Input is TxC Pin
4950 * <7..6> 01 DPLL Input is BRG1 Output
4951 * <5..3> XXX TxCLK comes from Port 0
4952 * <2..0> XXX RxCLK comes from Port 1
4953 *
4954 * 0000 1111 0111 0111 = 0x0f77
4955 */
4956
4957 RegValue = 0x0f40;
4958
4959 if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
4960 RegValue |= 0x0003; /* RxCLK from DPLL */
4961 else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
4962 RegValue |= 0x0004; /* RxCLK from BRG0 */
4963 else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4964 RegValue |= 0x0006; /* RxCLK from TXC Input */
4965 else
4966 RegValue |= 0x0007; /* RxCLK from Port1 */
4967
4968 if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
4969 RegValue |= 0x0018; /* TxCLK from DPLL */
4970 else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
4971 RegValue |= 0x0020; /* TxCLK from BRG0 */
4972 else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4973 RegValue |= 0x0038; /* RxCLK from TXC Input */
4974 else
4975 RegValue |= 0x0030; /* TxCLK from Port0 */
4976
4977 usc_OutReg( info, CMCR, RegValue );
4978
4979
4980 /* Hardware Configuration Register (HCR)
4981 *
4982 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
4983 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
4984 * <12> 0 CVOK:0=report code violation in biphase
4985 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
4986 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
4987 * <7..6> 00 reserved
4988 * <5> 0 BRG1 mode:0=continuous,1=single cycle
4989 * <4> X BRG1 Enable
4990 * <3..2> 00 reserved
4991 * <1> 0 BRG0 mode:0=continuous,1=single cycle
4992 * <0> 0 BRG0 Enable
4993 */
4994
4995 RegValue = 0x0000;
4996
4997 if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
4998 u32 XtalSpeed;
4999 u32 DpllDivisor;
5000 u16 Tc;
5001
5002 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
5003 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
5004
5005 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5006 XtalSpeed = 11059200;
5007 else
5008 XtalSpeed = 14745600;
5009
5010 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
5011 DpllDivisor = 16;
5012 RegValue |= BIT10;
5013 }
5014 else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
5015 DpllDivisor = 8;
5016 RegValue |= BIT11;
5017 }
5018 else
5019 DpllDivisor = 32;
5020
5021 /* Tc = (Xtal/Speed) - 1 */
5022 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5023 /* then rounding up gives a more precise time constant. Instead */
5024 /* of rounding up and then subtracting 1 we just don't subtract */
5025 /* the one in this case. */
5026
5027 /*--------------------------------------------------
5028 * ejz: for DPLL mode, application should use the
5029 * same clock speed as the partner system, even
5030 * though clocking is derived from the input RxData.
5031 * In case the user uses a 0 for the clock speed,
5032 * default to 0xffffffff and don't try to divide by
5033 * zero
5034 *--------------------------------------------------*/
5035 if ( info->params.clock_speed )
5036 {
5037 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
5038 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
5039 / info->params.clock_speed) )
5040 Tc--;
5041 }
5042 else
5043 Tc = -1;
5044
5045
5046 /* Write 16-bit Time Constant for BRG1 */
5047 usc_OutReg( info, TC1R, Tc );
5048
5049 RegValue |= BIT4; /* enable BRG1 */
5050
5051 switch ( info->params.encoding ) {
5052 case HDLC_ENCODING_NRZ:
5053 case HDLC_ENCODING_NRZB:
5054 case HDLC_ENCODING_NRZI_MARK:
5055 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5056 case HDLC_ENCODING_BIPHASE_MARK:
5057 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5058 case HDLC_ENCODING_BIPHASE_LEVEL:
5059 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
5060 }
5061 }
5062
5063 usc_OutReg( info, HCR, RegValue );
5064
5065
5066 /* Channel Control/status Register (CCSR)
5067 *
5068 * <15> X RCC FIFO Overflow status (RO)
5069 * <14> X RCC FIFO Not Empty status (RO)
5070 * <13> 0 1 = Clear RCC FIFO (WO)
5071 * <12> X DPLL Sync (RW)
5072 * <11> X DPLL 2 Missed Clocks status (RO)
5073 * <10> X DPLL 1 Missed Clock status (RO)
5074 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5075 * <7> X SDLC Loop On status (RO)
5076 * <6> X SDLC Loop Send status (RO)
5077 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5078 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5079 * <1..0> 00 reserved
5080 *
5081 * 0000 0000 0010 0000 = 0x0020
5082 */
5083
5084 usc_OutReg( info, CCSR, 0x1020 );
5085
5086
5087 if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5088 usc_OutReg( info, SICR,
5089 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5090 }
5091
5092
5093 /* enable Master Interrupt Enable bit (MIE) */
5094 usc_EnableMasterIrqBit( info );
5095
5096 usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
5097 TRANSMIT_STATUS + TRANSMIT_DATA + MISC);
5098
5099 /* arm RCC underflow interrupt */
5100 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5101 usc_EnableInterrupts(info, MISC);
5102
5103 info->mbre_bit = 0;
5104 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5105 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5106 info->mbre_bit = BIT8;
5107 outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
5108
5109 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5110 /* Enable DMAEN (Port 7, Bit 14) */
5111 /* This connects the DMA request signal to the ISA bus */
5112 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5113 }
5114
5115 /* DMA Control Register (DCR)
5116 *
5117 * <15..14> 10 Priority mode = Alternating Tx/Rx
5118 * 01 Rx has priority
5119 * 00 Tx has priority
5120 *
5121 * <13> 1 Enable Priority Preempt per DCR<15..14>
5122 * (WARNING DCR<11..10> must be 00 when this is 1)
5123 * 0 Choose activate channel per DCR<11..10>
5124 *
5125 * <12> 0 Little Endian for Array/List
5126 * <11..10> 00 Both Channels can use each bus grant
5127 * <9..6> 0000 reserved
5128 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5129 * <4> 0 1 = drive D/C and S/D pins
5130 * <3> 1 1 = Add one wait state to all DMA cycles.
5131 * <2> 0 1 = Strobe /UAS on every transfer.
5132 * <1..0> 11 Addr incrementing only affects LS24 bits
5133 *
5134 * 0110 0000 0000 1011 = 0x600b
5135 */
5136
5137 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5138 /* PCI adapter does not need DMA wait state */
5139 usc_OutDmaReg( info, DCR, 0xa00b );
5140 }
5141 else
5142 usc_OutDmaReg( info, DCR, 0x800b );
5143
5144
5145 /* Receive DMA mode Register (RDMR)
5146 *
5147 * <15..14> 11 DMA mode = Linked List Buffer mode
5148 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5149 * <12> 1 Clear count of List Entry after fetching
5150 * <11..10> 00 Address mode = Increment
5151 * <9> 1 Terminate Buffer on RxBound
5152 * <8> 0 Bus Width = 16bits
5153 * <7..0> ? status Bits (write as 0s)
5154 *
5155 * 1111 0010 0000 0000 = 0xf200
5156 */
5157
5158 usc_OutDmaReg( info, RDMR, 0xf200 );
5159
5160
5161 /* Transmit DMA mode Register (TDMR)
5162 *
5163 * <15..14> 11 DMA mode = Linked List Buffer mode
5164 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5165 * <12> 1 Clear count of List Entry after fetching
5166 * <11..10> 00 Address mode = Increment
5167 * <9> 1 Terminate Buffer on end of frame
5168 * <8> 0 Bus Width = 16bits
5169 * <7..0> ? status Bits (Read Only so write as 0)
5170 *
5171 * 1111 0010 0000 0000 = 0xf200
5172 */
5173
5174 usc_OutDmaReg( info, TDMR, 0xf200 );
5175
5176
5177 /* DMA Interrupt Control Register (DICR)
5178 *
5179 * <15> 1 DMA Interrupt Enable
5180 * <14> 0 1 = Disable IEO from USC
5181 * <13> 0 1 = Don't provide vector during IntAck
5182 * <12> 1 1 = Include status in Vector
5183 * <10..2> 0 reserved, Must be 0s
5184 * <1> 0 1 = Rx DMA Interrupt Enabled
5185 * <0> 0 1 = Tx DMA Interrupt Enabled
5186 *
5187 * 1001 0000 0000 0000 = 0x9000
5188 */
5189
5190 usc_OutDmaReg( info, DICR, 0x9000 );
5191
5192 usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */
5193 usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */
5194 usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5195
5196 /* Channel Control Register (CCR)
5197 *
5198 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5199 * <13> 0 Trigger Tx on SW Command Disabled
5200 * <12> 0 Flag Preamble Disabled
5201 * <11..10> 00 Preamble Length
5202 * <9..8> 00 Preamble Pattern
5203 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5204 * <5> 0 Trigger Rx on SW Command Disabled
5205 * <4..0> 0 reserved
5206 *
5207 * 1000 0000 1000 0000 = 0x8080
5208 */
5209
5210 RegValue = 0x8080;
5211
5212 switch ( info->params.preamble_length ) {
5213 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5214 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5215 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
5216 }
5217
5218 switch ( info->params.preamble ) {
5219 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5220 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5221 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
5222 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
5223 }
5224
5225 usc_OutReg( info, CCR, RegValue );
5226
5227
5228 /*
5229 * Burst/Dwell Control Register
5230 *
5231 * <15..8> 0x20 Maximum number of transfers per bus grant
5232 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5233 */
5234
5235 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5236 /* don't limit bus occupancy on PCI adapter */
5237 usc_OutDmaReg( info, BDCR, 0x0000 );
5238 }
5239 else
5240 usc_OutDmaReg( info, BDCR, 0x2000 );
5241
5242 usc_stop_transmitter(info);
5243 usc_stop_receiver(info);
5244
5245 } /* end of usc_set_sdlc_mode() */
5246
5247 /* usc_enable_loopback()
5248 *
5249 * Set the 16C32 for internal loopback mode.
5250 * The TxCLK and RxCLK signals are generated from the BRG0 and
5251 * the TxD is looped back to the RxD internally.
5252 *
5253 * Arguments: info pointer to device instance data
5254 * enable 1 = enable loopback, 0 = disable
5255 * Return Value: None
5256 */
5257 static void usc_enable_loopback(struct mgsl_struct *info, int enable)
5258 {
5259 if (enable) {
5260 /* blank external TXD output */
5261 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
5262
5263 /* Clock mode Control Register (CMCR)
5264 *
5265 * <15..14> 00 counter 1 Disabled
5266 * <13..12> 00 counter 0 Disabled
5267 * <11..10> 11 BRG1 Input is TxC Pin
5268 * <9..8> 11 BRG0 Input is TxC Pin
5269 * <7..6> 01 DPLL Input is BRG1 Output
5270 * <5..3> 100 TxCLK comes from BRG0
5271 * <2..0> 100 RxCLK comes from BRG0
5272 *
5273 * 0000 1111 0110 0100 = 0x0f64
5274 */
5275
5276 usc_OutReg( info, CMCR, 0x0f64 );
5277
5278 /* Write 16-bit Time Constant for BRG0 */
5279 /* use clock speed if available, otherwise use 8 for diagnostics */
5280 if (info->params.clock_speed) {
5281 if (info->bus_type == MGSL_BUS_TYPE_PCI)
5282 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5283 else
5284 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5285 } else
5286 usc_OutReg(info, TC0R, (u16)8);
5287
5288 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5289 mode = Continuous Set Bit 0 to enable BRG0. */
5290 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5291
5292 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5293 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5294
5295 /* set Internal Data loopback mode */
5296 info->loopback_bits = 0x300;
5297 outw( 0x0300, info->io_base + CCAR );
5298 } else {
5299 /* enable external TXD output */
5300 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6));
5301
5302 /* clear Internal Data loopback mode */
5303 info->loopback_bits = 0;
5304 outw( 0,info->io_base + CCAR );
5305 }
5306
5307 } /* end of usc_enable_loopback() */
5308
5309 /* usc_enable_aux_clock()
5310 *
5311 * Enabled the AUX clock output at the specified frequency.
5312 *
5313 * Arguments:
5314 *
5315 * info pointer to device extension
5316 * data_rate data rate of clock in bits per second
5317 * A data rate of 0 disables the AUX clock.
5318 *
5319 * Return Value: None
5320 */
5321 static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5322 {
5323 u32 XtalSpeed;
5324 u16 Tc;
5325
5326 if ( data_rate ) {
5327 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5328 XtalSpeed = 11059200;
5329 else
5330 XtalSpeed = 14745600;
5331
5332
5333 /* Tc = (Xtal/Speed) - 1 */
5334 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5335 /* then rounding up gives a more precise time constant. Instead */
5336 /* of rounding up and then subtracting 1 we just don't subtract */
5337 /* the one in this case. */
5338
5339
5340 Tc = (u16)(XtalSpeed/data_rate);
5341 if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5342 Tc--;
5343
5344 /* Write 16-bit Time Constant for BRG0 */
5345 usc_OutReg( info, TC0R, Tc );
5346
5347 /*
5348 * Hardware Configuration Register (HCR)
5349 * Clear Bit 1, BRG0 mode = Continuous
5350 * Set Bit 0 to enable BRG0.
5351 */
5352
5353 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5354
5355 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5356 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5357 } else {
5358 /* data rate == 0 so turn off BRG0 */
5359 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5360 }
5361
5362 } /* end of usc_enable_aux_clock() */
5363
5364 /*
5365 *
5366 * usc_process_rxoverrun_sync()
5367 *
5368 * This function processes a receive overrun by resetting the
5369 * receive DMA buffers and issuing a Purge Rx FIFO command
5370 * to allow the receiver to continue receiving.
5371 *
5372 * Arguments:
5373 *
5374 * info pointer to device extension
5375 *
5376 * Return Value: None
5377 */
5378 static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5379 {
5380 int start_index;
5381 int end_index;
5382 int frame_start_index;
5383 bool start_of_frame_found = false;
5384 bool end_of_frame_found = false;
5385 bool reprogram_dma = false;
5386
5387 DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5388 u32 phys_addr;
5389
5390 usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5391 usc_RCmd( info, RCmd_EnterHuntmode );
5392 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5393
5394 /* CurrentRxBuffer points to the 1st buffer of the next */
5395 /* possibly available receive frame. */
5396
5397 frame_start_index = start_index = end_index = info->current_rx_buffer;
5398
5399 /* Search for an unfinished string of buffers. This means */
5400 /* that a receive frame started (at least one buffer with */
5401 /* count set to zero) but there is no terminiting buffer */
5402 /* (status set to non-zero). */
5403
5404 while( !buffer_list[end_index].count )
5405 {
5406 /* Count field has been reset to zero by 16C32. */
5407 /* This buffer is currently in use. */
5408
5409 if ( !start_of_frame_found )
5410 {
5411 start_of_frame_found = true;
5412 frame_start_index = end_index;
5413 end_of_frame_found = false;
5414 }
5415
5416 if ( buffer_list[end_index].status )
5417 {
5418 /* Status field has been set by 16C32. */
5419 /* This is the last buffer of a received frame. */
5420
5421 /* We want to leave the buffers for this frame intact. */
5422 /* Move on to next possible frame. */
5423
5424 start_of_frame_found = false;
5425 end_of_frame_found = true;
5426 }
5427
5428 /* advance to next buffer entry in linked list */
5429 end_index++;
5430 if ( end_index == info->rx_buffer_count )
5431 end_index = 0;
5432
5433 if ( start_index == end_index )
5434 {
5435 /* The entire list has been searched with all Counts == 0 and */
5436 /* all Status == 0. The receive buffers are */
5437 /* completely screwed, reset all receive buffers! */
5438 mgsl_reset_rx_dma_buffers( info );
5439 frame_start_index = 0;
5440 start_of_frame_found = false;
5441 reprogram_dma = true;
5442 break;
5443 }
5444 }
5445
5446 if ( start_of_frame_found && !end_of_frame_found )
5447 {
5448 /* There is an unfinished string of receive DMA buffers */
5449 /* as a result of the receiver overrun. */
5450
5451 /* Reset the buffers for the unfinished frame */
5452 /* and reprogram the receive DMA controller to start */
5453 /* at the 1st buffer of unfinished frame. */
5454
5455 start_index = frame_start_index;
5456
5457 do
5458 {
5459 *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5460
5461 /* Adjust index for wrap around. */
5462 if ( start_index == info->rx_buffer_count )
5463 start_index = 0;
5464
5465 } while( start_index != end_index );
5466
5467 reprogram_dma = true;
5468 }
5469
5470 if ( reprogram_dma )
5471 {
5472 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5473 usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5474 usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5475
5476 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5477
5478 /* This empties the receive FIFO and loads the RCC with RCLR */
5479 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5480
5481 /* program 16C32 with physical address of 1st DMA buffer entry */
5482 phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5483 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5484 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5485
5486 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5487 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5488 usc_EnableInterrupts( info, RECEIVE_STATUS );
5489
5490 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5491 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5492
5493 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5494 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5495 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5496 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5497 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5498 else
5499 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5500 }
5501 else
5502 {
5503 /* This empties the receive FIFO and loads the RCC with RCLR */
5504 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5505 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5506 }
5507
5508 } /* end of usc_process_rxoverrun_sync() */
5509
5510 /* usc_stop_receiver()
5511 *
5512 * Disable USC receiver
5513 *
5514 * Arguments: info pointer to device instance data
5515 * Return Value: None
5516 */
5517 static void usc_stop_receiver( struct mgsl_struct *info )
5518 {
5519 if (debug_level >= DEBUG_LEVEL_ISR)
5520 printk("%s(%d):usc_stop_receiver(%s)\n",
5521 __FILE__,__LINE__, info->device_name );
5522
5523 /* Disable receive DMA channel. */
5524 /* This also disables receive DMA channel interrupts */
5525 usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5526
5527 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5528 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5529 usc_DisableInterrupts( info, RECEIVE_DATA + RECEIVE_STATUS );
5530
5531 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5532
5533 /* This empties the receive FIFO and loads the RCC with RCLR */
5534 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5535 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5536
5537 info->rx_enabled = false;
5538 info->rx_overflow = false;
5539 info->rx_rcc_underrun = false;
5540
5541 } /* end of stop_receiver() */
5542
5543 /* usc_start_receiver()
5544 *
5545 * Enable the USC receiver
5546 *
5547 * Arguments: info pointer to device instance data
5548 * Return Value: None
5549 */
5550 static void usc_start_receiver( struct mgsl_struct *info )
5551 {
5552 u32 phys_addr;
5553
5554 if (debug_level >= DEBUG_LEVEL_ISR)
5555 printk("%s(%d):usc_start_receiver(%s)\n",
5556 __FILE__,__LINE__, info->device_name );
5557
5558 mgsl_reset_rx_dma_buffers( info );
5559 usc_stop_receiver( info );
5560
5561 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5562 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5563
5564 if ( info->params.mode == MGSL_MODE_HDLC ||
5565 info->params.mode == MGSL_MODE_RAW ) {
5566 /* DMA mode Transfers */
5567 /* Program the DMA controller. */
5568 /* Enable the DMA controller end of buffer interrupt. */
5569
5570 /* program 16C32 with physical address of 1st DMA buffer entry */
5571 phys_addr = info->rx_buffer_list[0].phys_entry;
5572 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5573 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5574
5575 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5576 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5577 usc_EnableInterrupts( info, RECEIVE_STATUS );
5578
5579 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5580 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5581
5582 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5583 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5584 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5585 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5586 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5587 else
5588 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5589 } else {
5590 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
5591 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
5592 usc_EnableInterrupts(info, RECEIVE_DATA);
5593
5594 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5595 usc_RCmd( info, RCmd_EnterHuntmode );
5596
5597 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5598 }
5599
5600 usc_OutReg( info, CCSR, 0x1020 );
5601
5602 info->rx_enabled = true;
5603
5604 } /* end of usc_start_receiver() */
5605
5606 /* usc_start_transmitter()
5607 *
5608 * Enable the USC transmitter and send a transmit frame if
5609 * one is loaded in the DMA buffers.
5610 *
5611 * Arguments: info pointer to device instance data
5612 * Return Value: None
5613 */
5614 static void usc_start_transmitter( struct mgsl_struct *info )
5615 {
5616 u32 phys_addr;
5617 unsigned int FrameSize;
5618
5619 if (debug_level >= DEBUG_LEVEL_ISR)
5620 printk("%s(%d):usc_start_transmitter(%s)\n",
5621 __FILE__,__LINE__, info->device_name );
5622
5623 if ( info->xmit_cnt ) {
5624
5625 /* If auto RTS enabled and RTS is inactive, then assert */
5626 /* RTS and set a flag indicating that the driver should */
5627 /* negate RTS when the transmission completes. */
5628
5629 info->drop_rts_on_tx_done = false;
5630
5631 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5632 usc_get_serial_signals( info );
5633 if ( !(info->serial_signals & SerialSignal_RTS) ) {
5634 info->serial_signals |= SerialSignal_RTS;
5635 usc_set_serial_signals( info );
5636 info->drop_rts_on_tx_done = true;
5637 }
5638 }
5639
5640
5641 if ( info->params.mode == MGSL_MODE_ASYNC ) {
5642 if ( !info->tx_active ) {
5643 usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5644 usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5645 usc_EnableInterrupts(info, TRANSMIT_DATA);
5646 usc_load_txfifo(info);
5647 }
5648 } else {
5649 /* Disable transmit DMA controller while programming. */
5650 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5651
5652 /* Transmit DMA buffer is loaded, so program USC */
5653 /* to send the frame contained in the buffers. */
5654
5655 FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
5656
5657 /* if operating in Raw sync mode, reset the rcc component
5658 * of the tx dma buffer entry, otherwise, the serial controller
5659 * will send a closing sync char after this count.
5660 */
5661 if ( info->params.mode == MGSL_MODE_RAW )
5662 info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
5663
5664 /* Program the Transmit Character Length Register (TCLR) */
5665 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5666 usc_OutReg( info, TCLR, (u16)FrameSize );
5667
5668 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5669
5670 /* Program the address of the 1st DMA Buffer Entry in linked list */
5671 phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
5672 usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5673 usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5674
5675 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5676 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5677 usc_EnableInterrupts( info, TRANSMIT_STATUS );
5678
5679 if ( info->params.mode == MGSL_MODE_RAW &&
5680 info->num_tx_dma_buffers > 1 ) {
5681 /* When running external sync mode, attempt to 'stream' transmit */
5682 /* by filling tx dma buffers as they become available. To do this */
5683 /* we need to enable Tx DMA EOB Status interrupts : */
5684 /* */
5685 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5686 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5687
5688 usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5689 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
5690 }
5691
5692 /* Initialize Transmit DMA Channel */
5693 usc_DmaCmd( info, DmaCmd_InitTxChannel );
5694
5695 usc_TCmd( info, TCmd_SendFrame );
5696
5697 mod_timer(&info->tx_timer, jiffies +
5698 msecs_to_jiffies(5000));
5699 }
5700 info->tx_active = true;
5701 }
5702
5703 if ( !info->tx_enabled ) {
5704 info->tx_enabled = true;
5705 if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5706 usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5707 else
5708 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5709 }
5710
5711 } /* end of usc_start_transmitter() */
5712
5713 /* usc_stop_transmitter()
5714 *
5715 * Stops the transmitter and DMA
5716 *
5717 * Arguments: info pointer to device isntance data
5718 * Return Value: None
5719 */
5720 static void usc_stop_transmitter( struct mgsl_struct *info )
5721 {
5722 if (debug_level >= DEBUG_LEVEL_ISR)
5723 printk("%s(%d):usc_stop_transmitter(%s)\n",
5724 __FILE__,__LINE__, info->device_name );
5725
5726 del_timer(&info->tx_timer);
5727
5728 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5729 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5730 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5731
5732 usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5733 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5734 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5735
5736 info->tx_enabled = false;
5737 info->tx_active = false;
5738
5739 } /* end of usc_stop_transmitter() */
5740
5741 /* usc_load_txfifo()
5742 *
5743 * Fill the transmit FIFO until the FIFO is full or
5744 * there is no more data to load.
5745 *
5746 * Arguments: info pointer to device extension (instance data)
5747 * Return Value: None
5748 */
5749 static void usc_load_txfifo( struct mgsl_struct *info )
5750 {
5751 int Fifocount;
5752 u8 TwoBytes[2];
5753
5754 if ( !info->xmit_cnt && !info->x_char )
5755 return;
5756
5757 /* Select transmit FIFO status readback in TICR */
5758 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5759
5760 /* load the Transmit FIFO until FIFOs full or all data sent */
5761
5762 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5763 /* there is more space in the transmit FIFO and */
5764 /* there is more data in transmit buffer */
5765
5766 if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5767 /* write a 16-bit word from transmit buffer to 16C32 */
5768
5769 TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5770 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5771 TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5772 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5773
5774 outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5775
5776 info->xmit_cnt -= 2;
5777 info->icount.tx += 2;
5778 } else {
5779 /* only 1 byte left to transmit or 1 FIFO slot left */
5780
5781 outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5782 info->io_base + CCAR );
5783
5784 if (info->x_char) {
5785 /* transmit pending high priority char */
5786 outw( info->x_char,info->io_base + CCAR );
5787 info->x_char = 0;
5788 } else {
5789 outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5790 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5791 info->xmit_cnt--;
5792 }
5793 info->icount.tx++;
5794 }
5795 }
5796
5797 } /* end of usc_load_txfifo() */
5798
5799 /* usc_reset()
5800 *
5801 * Reset the adapter to a known state and prepare it for further use.
5802 *
5803 * Arguments: info pointer to device instance data
5804 * Return Value: None
5805 */
5806 static void usc_reset( struct mgsl_struct *info )
5807 {
5808 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5809 int i;
5810 u32 readval;
5811
5812 /* Set BIT30 of Misc Control Register */
5813 /* (Local Control Register 0x50) to force reset of USC. */
5814
5815 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5816 u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5817
5818 info->misc_ctrl_value |= BIT30;
5819 *MiscCtrl = info->misc_ctrl_value;
5820
5821 /*
5822 * Force at least 170ns delay before clearing
5823 * reset bit. Each read from LCR takes at least
5824 * 30ns so 10 times for 300ns to be safe.
5825 */
5826 for(i=0;i<10;i++)
5827 readval = *MiscCtrl;
5828
5829 info->misc_ctrl_value &= ~BIT30;
5830 *MiscCtrl = info->misc_ctrl_value;
5831
5832 *LCR0BRDR = BUS_DESCRIPTOR(
5833 1, // Write Strobe Hold (0-3)
5834 2, // Write Strobe Delay (0-3)
5835 2, // Read Strobe Delay (0-3)
5836 0, // NWDD (Write data-data) (0-3)
5837 4, // NWAD (Write Addr-data) (0-31)
5838 0, // NXDA (Read/Write Data-Addr) (0-3)
5839 0, // NRDD (Read Data-Data) (0-3)
5840 5 // NRAD (Read Addr-Data) (0-31)
5841 );
5842 } else {
5843 /* do HW reset */
5844 outb( 0,info->io_base + 8 );
5845 }
5846
5847 info->mbre_bit = 0;
5848 info->loopback_bits = 0;
5849 info->usc_idle_mode = 0;
5850
5851 /*
5852 * Program the Bus Configuration Register (BCR)
5853 *
5854 * <15> 0 Don't use separate address
5855 * <14..6> 0 reserved
5856 * <5..4> 00 IAckmode = Default, don't care
5857 * <3> 1 Bus Request Totem Pole output
5858 * <2> 1 Use 16 Bit data bus
5859 * <1> 0 IRQ Totem Pole output
5860 * <0> 0 Don't Shift Right Addr
5861 *
5862 * 0000 0000 0000 1100 = 0x000c
5863 *
5864 * By writing to io_base + SDPIN the Wait/Ack pin is
5865 * programmed to work as a Wait pin.
5866 */
5867
5868 outw( 0x000c,info->io_base + SDPIN );
5869
5870
5871 outw( 0,info->io_base );
5872 outw( 0,info->io_base + CCAR );
5873
5874 /* select little endian byte ordering */
5875 usc_RTCmd( info, RTCmd_SelectLittleEndian );
5876
5877
5878 /* Port Control Register (PCR)
5879 *
5880 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5881 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5882 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5883 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5884 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5885 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5886 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5887 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5888 *
5889 * 1111 0000 1111 0101 = 0xf0f5
5890 */
5891
5892 usc_OutReg( info, PCR, 0xf0f5 );
5893
5894
5895 /*
5896 * Input/Output Control Register
5897 *
5898 * <15..14> 00 CTS is active low input
5899 * <13..12> 00 DCD is active low input
5900 * <11..10> 00 TxREQ pin is input (DSR)
5901 * <9..8> 00 RxREQ pin is input (RI)
5902 * <7..6> 00 TxD is output (Transmit Data)
5903 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5904 * <2..0> 100 RxC is Output (drive with BRG0)
5905 *
5906 * 0000 0000 0000 0100 = 0x0004
5907 */
5908
5909 usc_OutReg( info, IOCR, 0x0004 );
5910
5911 } /* end of usc_reset() */
5912
5913 /* usc_set_async_mode()
5914 *
5915 * Program adapter for asynchronous communications.
5916 *
5917 * Arguments: info pointer to device instance data
5918 * Return Value: None
5919 */
5920 static void usc_set_async_mode( struct mgsl_struct *info )
5921 {
5922 u16 RegValue;
5923
5924 /* disable interrupts while programming USC */
5925 usc_DisableMasterIrqBit( info );
5926
5927 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5928 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5929
5930 usc_loopback_frame( info );
5931
5932 /* Channel mode Register (CMR)
5933 *
5934 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5935 * <13..12> 00 00 = 16X Clock
5936 * <11..8> 0000 Transmitter mode = Asynchronous
5937 * <7..6> 00 reserved?
5938 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5939 * <3..0> 0000 Receiver mode = Asynchronous
5940 *
5941 * 0000 0000 0000 0000 = 0x0
5942 */
5943
5944 RegValue = 0;
5945 if ( info->params.stop_bits != 1 )
5946 RegValue |= BIT14;
5947 usc_OutReg( info, CMR, RegValue );
5948
5949
5950 /* Receiver mode Register (RMR)
5951 *
5952 * <15..13> 000 encoding = None
5953 * <12..08> 00000 reserved (Sync Only)
5954 * <7..6> 00 Even parity
5955 * <5> 0 parity disabled
5956 * <4..2> 000 Receive Char Length = 8 bits
5957 * <1..0> 00 Disable Receiver
5958 *
5959 * 0000 0000 0000 0000 = 0x0
5960 */
5961
5962 RegValue = 0;
5963
5964 if ( info->params.data_bits != 8 )
5965 RegValue |= BIT4+BIT3+BIT2;
5966
5967 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5968 RegValue |= BIT5;
5969 if ( info->params.parity != ASYNC_PARITY_ODD )
5970 RegValue |= BIT6;
5971 }
5972
5973 usc_OutReg( info, RMR, RegValue );
5974
5975
5976 /* Set IRQ trigger level */
5977
5978 usc_RCmd( info, RCmd_SelectRicrIntLevel );
5979
5980
5981 /* Receive Interrupt Control Register (RICR)
5982 *
5983 * <15..8> ? RxFIFO IRQ Request Level
5984 *
5985 * Note: For async mode the receive FIFO level must be set
5986 * to 0 to avoid the situation where the FIFO contains fewer bytes
5987 * than the trigger level and no more data is expected.
5988 *
5989 * <7> 0 Exited Hunt IA (Interrupt Arm)
5990 * <6> 0 Idle Received IA
5991 * <5> 0 Break/Abort IA
5992 * <4> 0 Rx Bound IA
5993 * <3> 0 Queued status reflects oldest byte in FIFO
5994 * <2> 0 Abort/PE IA
5995 * <1> 0 Rx Overrun IA
5996 * <0> 0 Select TC0 value for readback
5997 *
5998 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
5999 */
6000
6001 usc_OutReg( info, RICR, 0x0000 );
6002
6003 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
6004 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
6005
6006
6007 /* Transmit mode Register (TMR)
6008 *
6009 * <15..13> 000 encoding = None
6010 * <12..08> 00000 reserved (Sync Only)
6011 * <7..6> 00 Transmit parity Even
6012 * <5> 0 Transmit parity Disabled
6013 * <4..2> 000 Tx Char Length = 8 bits
6014 * <1..0> 00 Disable Transmitter
6015 *
6016 * 0000 0000 0000 0000 = 0x0
6017 */
6018
6019 RegValue = 0;
6020
6021 if ( info->params.data_bits != 8 )
6022 RegValue |= BIT4+BIT3+BIT2;
6023
6024 if ( info->params.parity != ASYNC_PARITY_NONE ) {
6025 RegValue |= BIT5;
6026 if ( info->params.parity != ASYNC_PARITY_ODD )
6027 RegValue |= BIT6;
6028 }
6029
6030 usc_OutReg( info, TMR, RegValue );
6031
6032 usc_set_txidle( info );
6033
6034
6035 /* Set IRQ trigger level */
6036
6037 usc_TCmd( info, TCmd_SelectTicrIntLevel );
6038
6039
6040 /* Transmit Interrupt Control Register (TICR)
6041 *
6042 * <15..8> ? Transmit FIFO IRQ Level
6043 * <7> 0 Present IA (Interrupt Arm)
6044 * <6> 1 Idle Sent IA
6045 * <5> 0 Abort Sent IA
6046 * <4> 0 EOF/EOM Sent IA
6047 * <3> 0 CRC Sent IA
6048 * <2> 0 1 = Wait for SW Trigger to Start Frame
6049 * <1> 0 Tx Underrun IA
6050 * <0> 0 TC0 constant on read back
6051 *
6052 * 0000 0000 0100 0000 = 0x0040
6053 */
6054
6055 usc_OutReg( info, TICR, 0x1f40 );
6056
6057 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
6058 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
6059
6060 usc_enable_async_clock( info, info->params.data_rate );
6061
6062
6063 /* Channel Control/status Register (CCSR)
6064 *
6065 * <15> X RCC FIFO Overflow status (RO)
6066 * <14> X RCC FIFO Not Empty status (RO)
6067 * <13> 0 1 = Clear RCC FIFO (WO)
6068 * <12> X DPLL in Sync status (RO)
6069 * <11> X DPLL 2 Missed Clocks status (RO)
6070 * <10> X DPLL 1 Missed Clock status (RO)
6071 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6072 * <7> X SDLC Loop On status (RO)
6073 * <6> X SDLC Loop Send status (RO)
6074 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6075 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6076 * <1..0> 00 reserved
6077 *
6078 * 0000 0000 0010 0000 = 0x0020
6079 */
6080
6081 usc_OutReg( info, CCSR, 0x0020 );
6082
6083 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6084 RECEIVE_DATA + RECEIVE_STATUS );
6085
6086 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6087 RECEIVE_DATA + RECEIVE_STATUS );
6088
6089 usc_EnableMasterIrqBit( info );
6090
6091 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6092 /* Enable INTEN (Port 6, Bit12) */
6093 /* This connects the IRQ request signal to the ISA bus */
6094 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6095 }
6096
6097 if (info->params.loopback) {
6098 info->loopback_bits = 0x300;
6099 outw(0x0300, info->io_base + CCAR);
6100 }
6101
6102 } /* end of usc_set_async_mode() */
6103
6104 /* usc_loopback_frame()
6105 *
6106 * Loop back a small (2 byte) dummy SDLC frame.
6107 * Interrupts and DMA are NOT used. The purpose of this is to
6108 * clear any 'stale' status info left over from running in async mode.
6109 *
6110 * The 16C32 shows the strange behaviour of marking the 1st
6111 * received SDLC frame with a CRC error even when there is no
6112 * CRC error. To get around this a small dummy from of 2 bytes
6113 * is looped back when switching from async to sync mode.
6114 *
6115 * Arguments: info pointer to device instance data
6116 * Return Value: None
6117 */
6118 static void usc_loopback_frame( struct mgsl_struct *info )
6119 {
6120 int i;
6121 unsigned long oldmode = info->params.mode;
6122
6123 info->params.mode = MGSL_MODE_HDLC;
6124
6125 usc_DisableMasterIrqBit( info );
6126
6127 usc_set_sdlc_mode( info );
6128 usc_enable_loopback( info, 1 );
6129
6130 /* Write 16-bit Time Constant for BRG0 */
6131 usc_OutReg( info, TC0R, 0 );
6132
6133 /* Channel Control Register (CCR)
6134 *
6135 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6136 * <13> 0 Trigger Tx on SW Command Disabled
6137 * <12> 0 Flag Preamble Disabled
6138 * <11..10> 00 Preamble Length = 8-Bits
6139 * <9..8> 01 Preamble Pattern = flags
6140 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6141 * <5> 0 Trigger Rx on SW Command Disabled
6142 * <4..0> 0 reserved
6143 *
6144 * 0000 0001 0000 0000 = 0x0100
6145 */
6146
6147 usc_OutReg( info, CCR, 0x0100 );
6148
6149 /* SETUP RECEIVER */
6150 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6151 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6152
6153 /* SETUP TRANSMITTER */
6154 /* Program the Transmit Character Length Register (TCLR) */
6155 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6156 usc_OutReg( info, TCLR, 2 );
6157 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6158
6159 /* unlatch Tx status bits, and start transmit channel. */
6160 usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6161 outw(0,info->io_base + DATAREG);
6162
6163 /* ENABLE TRANSMITTER */
6164 usc_TCmd( info, TCmd_SendFrame );
6165 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6166
6167 /* WAIT FOR RECEIVE COMPLETE */
6168 for (i=0 ; i<1000 ; i++)
6169 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
6170 break;
6171
6172 /* clear Internal Data loopback mode */
6173 usc_enable_loopback(info, 0);
6174
6175 usc_EnableMasterIrqBit(info);
6176
6177 info->params.mode = oldmode;
6178
6179 } /* end of usc_loopback_frame() */
6180
6181 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6182 *
6183 * Arguments: info pointer to adapter info structure
6184 * Return Value: None
6185 */
6186 static void usc_set_sync_mode( struct mgsl_struct *info )
6187 {
6188 usc_loopback_frame( info );
6189 usc_set_sdlc_mode( info );
6190
6191 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6192 /* Enable INTEN (Port 6, Bit12) */
6193 /* This connects the IRQ request signal to the ISA bus */
6194 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6195 }
6196
6197 usc_enable_aux_clock(info, info->params.clock_speed);
6198
6199 if (info->params.loopback)
6200 usc_enable_loopback(info,1);
6201
6202 } /* end of mgsl_set_sync_mode() */
6203
6204 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6205 *
6206 * Arguments: info pointer to device instance data
6207 * Return Value: None
6208 */
6209 static void usc_set_txidle( struct mgsl_struct *info )
6210 {
6211 u16 usc_idle_mode = IDLEMODE_FLAGS;
6212
6213 /* Map API idle mode to USC register bits */
6214
6215 switch( info->idle_mode ){
6216 case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
6217 case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6218 case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
6219 case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
6220 case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6221 case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
6222 case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
6223 }
6224
6225 info->usc_idle_mode = usc_idle_mode;
6226 //usc_OutReg(info, TCSR, usc_idle_mode);
6227 info->tcsr_value &= ~IDLEMODE_MASK; /* clear idle mode bits */
6228 info->tcsr_value += usc_idle_mode;
6229 usc_OutReg(info, TCSR, info->tcsr_value);
6230
6231 /*
6232 * if SyncLink WAN adapter is running in external sync mode, the
6233 * transmitter has been set to Monosync in order to try to mimic
6234 * a true raw outbound bit stream. Monosync still sends an open/close
6235 * sync char at the start/end of a frame. Try to match those sync
6236 * patterns to the idle mode set here
6237 */
6238 if ( info->params.mode == MGSL_MODE_RAW ) {
6239 unsigned char syncpat = 0;
6240 switch( info->idle_mode ) {
6241 case HDLC_TXIDLE_FLAGS:
6242 syncpat = 0x7e;
6243 break;
6244 case HDLC_TXIDLE_ALT_ZEROS_ONES:
6245 syncpat = 0x55;
6246 break;
6247 case HDLC_TXIDLE_ZEROS:
6248 case HDLC_TXIDLE_SPACE:
6249 syncpat = 0x00;
6250 break;
6251 case HDLC_TXIDLE_ONES:
6252 case HDLC_TXIDLE_MARK:
6253 syncpat = 0xff;
6254 break;
6255 case HDLC_TXIDLE_ALT_MARK_SPACE:
6256 syncpat = 0xaa;
6257 break;
6258 }
6259
6260 usc_SetTransmitSyncChars(info,syncpat,syncpat);
6261 }
6262
6263 } /* end of usc_set_txidle() */
6264
6265 /* usc_get_serial_signals()
6266 *
6267 * Query the adapter for the state of the V24 status (input) signals.
6268 *
6269 * Arguments: info pointer to device instance data
6270 * Return Value: None
6271 */
6272 static void usc_get_serial_signals( struct mgsl_struct *info )
6273 {
6274 u16 status;
6275
6276 /* clear all serial signals except DTR and RTS */
6277 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
6278
6279 /* Read the Misc Interrupt status Register (MISR) to get */
6280 /* the V24 status signals. */
6281
6282 status = usc_InReg( info, MISR );
6283
6284 /* set serial signal bits to reflect MISR */
6285
6286 if ( status & MISCSTATUS_CTS )
6287 info->serial_signals |= SerialSignal_CTS;
6288
6289 if ( status & MISCSTATUS_DCD )
6290 info->serial_signals |= SerialSignal_DCD;
6291
6292 if ( status & MISCSTATUS_RI )
6293 info->serial_signals |= SerialSignal_RI;
6294
6295 if ( status & MISCSTATUS_DSR )
6296 info->serial_signals |= SerialSignal_DSR;
6297
6298 } /* end of usc_get_serial_signals() */
6299
6300 /* usc_set_serial_signals()
6301 *
6302 * Set the state of DTR and RTS based on contents of
6303 * serial_signals member of device extension.
6304 *
6305 * Arguments: info pointer to device instance data
6306 * Return Value: None
6307 */
6308 static void usc_set_serial_signals( struct mgsl_struct *info )
6309 {
6310 u16 Control;
6311 unsigned char V24Out = info->serial_signals;
6312
6313 /* get the current value of the Port Control Register (PCR) */
6314
6315 Control = usc_InReg( info, PCR );
6316
6317 if ( V24Out & SerialSignal_RTS )
6318 Control &= ~(BIT6);
6319 else
6320 Control |= BIT6;
6321
6322 if ( V24Out & SerialSignal_DTR )
6323 Control &= ~(BIT4);
6324 else
6325 Control |= BIT4;
6326
6327 usc_OutReg( info, PCR, Control );
6328
6329 } /* end of usc_set_serial_signals() */
6330
6331 /* usc_enable_async_clock()
6332 *
6333 * Enable the async clock at the specified frequency.
6334 *
6335 * Arguments: info pointer to device instance data
6336 * data_rate data rate of clock in bps
6337 * 0 disables the AUX clock.
6338 * Return Value: None
6339 */
6340 static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6341 {
6342 if ( data_rate ) {
6343 /*
6344 * Clock mode Control Register (CMCR)
6345 *
6346 * <15..14> 00 counter 1 Disabled
6347 * <13..12> 00 counter 0 Disabled
6348 * <11..10> 11 BRG1 Input is TxC Pin
6349 * <9..8> 11 BRG0 Input is TxC Pin
6350 * <7..6> 01 DPLL Input is BRG1 Output
6351 * <5..3> 100 TxCLK comes from BRG0
6352 * <2..0> 100 RxCLK comes from BRG0
6353 *
6354 * 0000 1111 0110 0100 = 0x0f64
6355 */
6356
6357 usc_OutReg( info, CMCR, 0x0f64 );
6358
6359
6360 /*
6361 * Write 16-bit Time Constant for BRG0
6362 * Time Constant = (ClkSpeed / data_rate) - 1
6363 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6364 */
6365
6366 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6367 usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6368 else
6369 usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6370
6371
6372 /*
6373 * Hardware Configuration Register (HCR)
6374 * Clear Bit 1, BRG0 mode = Continuous
6375 * Set Bit 0 to enable BRG0.
6376 */
6377
6378 usc_OutReg( info, HCR,
6379 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6380
6381
6382 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6383
6384 usc_OutReg( info, IOCR,
6385 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6386 } else {
6387 /* data rate == 0 so turn off BRG0 */
6388 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6389 }
6390
6391 } /* end of usc_enable_async_clock() */
6392
6393 /*
6394 * Buffer Structures:
6395 *
6396 * Normal memory access uses virtual addresses that can make discontiguous
6397 * physical memory pages appear to be contiguous in the virtual address
6398 * space (the processors memory mapping handles the conversions).
6399 *
6400 * DMA transfers require physically contiguous memory. This is because
6401 * the DMA system controller and DMA bus masters deal with memory using
6402 * only physical addresses.
6403 *
6404 * This causes a problem under Windows NT when large DMA buffers are
6405 * needed. Fragmentation of the nonpaged pool prevents allocations of
6406 * physically contiguous buffers larger than the PAGE_SIZE.
6407 *
6408 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6409 * allows DMA transfers to physically discontiguous buffers. Information
6410 * about each data transfer buffer is contained in a memory structure
6411 * called a 'buffer entry'. A list of buffer entries is maintained
6412 * to track and control the use of the data transfer buffers.
6413 *
6414 * To support this strategy we will allocate sufficient PAGE_SIZE
6415 * contiguous memory buffers to allow for the total required buffer
6416 * space.
6417 *
6418 * The 16C32 accesses the list of buffer entries using Bus Master
6419 * DMA. Control information is read from the buffer entries by the
6420 * 16C32 to control data transfers. status information is written to
6421 * the buffer entries by the 16C32 to indicate the status of completed
6422 * transfers.
6423 *
6424 * The CPU writes control information to the buffer entries to control
6425 * the 16C32 and reads status information from the buffer entries to
6426 * determine information about received and transmitted frames.
6427 *
6428 * Because the CPU and 16C32 (adapter) both need simultaneous access
6429 * to the buffer entries, the buffer entry memory is allocated with
6430 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6431 * entry list to PAGE_SIZE.
6432 *
6433 * The actual data buffers on the other hand will only be accessed
6434 * by the CPU or the adapter but not by both simultaneously. This allows
6435 * Scatter/Gather packet based DMA procedures for using physically
6436 * discontiguous pages.
6437 */
6438
6439 /*
6440 * mgsl_reset_tx_dma_buffers()
6441 *
6442 * Set the count for all transmit buffers to 0 to indicate the
6443 * buffer is available for use and set the current buffer to the
6444 * first buffer. This effectively makes all buffers free and
6445 * discards any data in buffers.
6446 *
6447 * Arguments: info pointer to device instance data
6448 * Return Value: None
6449 */
6450 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
6451 {
6452 unsigned int i;
6453
6454 for ( i = 0; i < info->tx_buffer_count; i++ ) {
6455 *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
6456 }
6457
6458 info->current_tx_buffer = 0;
6459 info->start_tx_dma_buffer = 0;
6460 info->tx_dma_buffers_used = 0;
6461
6462 info->get_tx_holding_index = 0;
6463 info->put_tx_holding_index = 0;
6464 info->tx_holding_count = 0;
6465
6466 } /* end of mgsl_reset_tx_dma_buffers() */
6467
6468 /*
6469 * num_free_tx_dma_buffers()
6470 *
6471 * returns the number of free tx dma buffers available
6472 *
6473 * Arguments: info pointer to device instance data
6474 * Return Value: number of free tx dma buffers
6475 */
6476 static int num_free_tx_dma_buffers(struct mgsl_struct *info)
6477 {
6478 return info->tx_buffer_count - info->tx_dma_buffers_used;
6479 }
6480
6481 /*
6482 * mgsl_reset_rx_dma_buffers()
6483 *
6484 * Set the count for all receive buffers to DMABUFFERSIZE
6485 * and set the current buffer to the first buffer. This effectively
6486 * makes all buffers free and discards any data in buffers.
6487 *
6488 * Arguments: info pointer to device instance data
6489 * Return Value: None
6490 */
6491 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6492 {
6493 unsigned int i;
6494
6495 for ( i = 0; i < info->rx_buffer_count; i++ ) {
6496 *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6497 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6498 // info->rx_buffer_list[i].status = 0;
6499 }
6500
6501 info->current_rx_buffer = 0;
6502
6503 } /* end of mgsl_reset_rx_dma_buffers() */
6504
6505 /*
6506 * mgsl_free_rx_frame_buffers()
6507 *
6508 * Free the receive buffers used by a received SDLC
6509 * frame such that the buffers can be reused.
6510 *
6511 * Arguments:
6512 *
6513 * info pointer to device instance data
6514 * StartIndex index of 1st receive buffer of frame
6515 * EndIndex index of last receive buffer of frame
6516 *
6517 * Return Value: None
6518 */
6519 static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6520 {
6521 bool Done = false;
6522 DMABUFFERENTRY *pBufEntry;
6523 unsigned int Index;
6524
6525 /* Starting with 1st buffer entry of the frame clear the status */
6526 /* field and set the count field to DMA Buffer Size. */
6527
6528 Index = StartIndex;
6529
6530 while( !Done ) {
6531 pBufEntry = &(info->rx_buffer_list[Index]);
6532
6533 if ( Index == EndIndex ) {
6534 /* This is the last buffer of the frame! */
6535 Done = true;
6536 }
6537
6538 /* reset current buffer for reuse */
6539 // pBufEntry->status = 0;
6540 // pBufEntry->count = DMABUFFERSIZE;
6541 *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6542
6543 /* advance to next buffer entry in linked list */
6544 Index++;
6545 if ( Index == info->rx_buffer_count )
6546 Index = 0;
6547 }
6548
6549 /* set current buffer to next buffer after last buffer of frame */
6550 info->current_rx_buffer = Index;
6551
6552 } /* end of free_rx_frame_buffers() */
6553
6554 /* mgsl_get_rx_frame()
6555 *
6556 * This function attempts to return a received SDLC frame from the
6557 * receive DMA buffers. Only frames received without errors are returned.
6558 *
6559 * Arguments: info pointer to device extension
6560 * Return Value: true if frame returned, otherwise false
6561 */
6562 static bool mgsl_get_rx_frame(struct mgsl_struct *info)
6563 {
6564 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
6565 unsigned short status;
6566 DMABUFFERENTRY *pBufEntry;
6567 unsigned int framesize = 0;
6568 bool ReturnCode = false;
6569 unsigned long flags;
6570 struct tty_struct *tty = info->port.tty;
6571 bool return_frame = false;
6572
6573 /*
6574 * current_rx_buffer points to the 1st buffer of the next available
6575 * receive frame. To find the last buffer of the frame look for
6576 * a non-zero status field in the buffer entries. (The status
6577 * field is set by the 16C32 after completing a receive frame.
6578 */
6579
6580 StartIndex = EndIndex = info->current_rx_buffer;
6581
6582 while( !info->rx_buffer_list[EndIndex].status ) {
6583 /*
6584 * If the count field of the buffer entry is non-zero then
6585 * this buffer has not been used. (The 16C32 clears the count
6586 * field when it starts using the buffer.) If an unused buffer
6587 * is encountered then there are no frames available.
6588 */
6589
6590 if ( info->rx_buffer_list[EndIndex].count )
6591 goto Cleanup;
6592
6593 /* advance to next buffer entry in linked list */
6594 EndIndex++;
6595 if ( EndIndex == info->rx_buffer_count )
6596 EndIndex = 0;
6597
6598 /* if entire list searched then no frame available */
6599 if ( EndIndex == StartIndex ) {
6600 /* If this occurs then something bad happened,
6601 * all buffers have been 'used' but none mark
6602 * the end of a frame. Reset buffers and receiver.
6603 */
6604
6605 if ( info->rx_enabled ){
6606 spin_lock_irqsave(&info->irq_spinlock,flags);
6607 usc_start_receiver(info);
6608 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6609 }
6610 goto Cleanup;
6611 }
6612 }
6613
6614
6615 /* check status of receive frame */
6616
6617 status = info->rx_buffer_list[EndIndex].status;
6618
6619 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6620 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6621 if ( status & RXSTATUS_SHORT_FRAME )
6622 info->icount.rxshort++;
6623 else if ( status & RXSTATUS_ABORT )
6624 info->icount.rxabort++;
6625 else if ( status & RXSTATUS_OVERRUN )
6626 info->icount.rxover++;
6627 else {
6628 info->icount.rxcrc++;
6629 if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
6630 return_frame = true;
6631 }
6632 framesize = 0;
6633 #if SYNCLINK_GENERIC_HDLC
6634 {
6635 info->netdev->stats.rx_errors++;
6636 info->netdev->stats.rx_frame_errors++;
6637 }
6638 #endif
6639 } else
6640 return_frame = true;
6641
6642 if ( return_frame ) {
6643 /* receive frame has no errors, get frame size.
6644 * The frame size is the starting value of the RCC (which was
6645 * set to 0xffff) minus the ending value of the RCC (decremented
6646 * once for each receive character) minus 2 for the 16-bit CRC.
6647 */
6648
6649 framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6650
6651 /* adjust frame size for CRC if any */
6652 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6653 framesize -= 2;
6654 else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
6655 framesize -= 4;
6656 }
6657
6658 if ( debug_level >= DEBUG_LEVEL_BH )
6659 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6660 __FILE__,__LINE__,info->device_name,status,framesize);
6661
6662 if ( debug_level >= DEBUG_LEVEL_DATA )
6663 mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6664 min_t(int, framesize, DMABUFFERSIZE),0);
6665
6666 if (framesize) {
6667 if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
6668 ((framesize+1) > info->max_frame_size) ) ||
6669 (framesize > info->max_frame_size) )
6670 info->icount.rxlong++;
6671 else {
6672 /* copy dma buffer(s) to contiguous intermediate buffer */
6673 int copy_count = framesize;
6674 int index = StartIndex;
6675 unsigned char *ptmp = info->intermediate_rxbuffer;
6676
6677 if ( !(status & RXSTATUS_CRC_ERROR))
6678 info->icount.rxok++;
6679
6680 while(copy_count) {
6681 int partial_count;
6682 if ( copy_count > DMABUFFERSIZE )
6683 partial_count = DMABUFFERSIZE;
6684 else
6685 partial_count = copy_count;
6686
6687 pBufEntry = &(info->rx_buffer_list[index]);
6688 memcpy( ptmp, pBufEntry->virt_addr, partial_count );
6689 ptmp += partial_count;
6690 copy_count -= partial_count;
6691
6692 if ( ++index == info->rx_buffer_count )
6693 index = 0;
6694 }
6695
6696 if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
6697 ++framesize;
6698 *ptmp = (status & RXSTATUS_CRC_ERROR ?
6699 RX_CRC_ERROR :
6700 RX_OK);
6701
6702 if ( debug_level >= DEBUG_LEVEL_DATA )
6703 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6704 __FILE__,__LINE__,info->device_name,
6705 *ptmp);
6706 }
6707
6708 #if SYNCLINK_GENERIC_HDLC
6709 if (info->netcount)
6710 hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
6711 else
6712 #endif
6713 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6714 }
6715 }
6716 /* Free the buffers used by this frame. */
6717 mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6718
6719 ReturnCode = true;
6720
6721 Cleanup:
6722
6723 if ( info->rx_enabled && info->rx_overflow ) {
6724 /* The receiver needs to restarted because of
6725 * a receive overflow (buffer or FIFO). If the
6726 * receive buffers are now empty, then restart receiver.
6727 */
6728
6729 if ( !info->rx_buffer_list[EndIndex].status &&
6730 info->rx_buffer_list[EndIndex].count ) {
6731 spin_lock_irqsave(&info->irq_spinlock,flags);
6732 usc_start_receiver(info);
6733 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6734 }
6735 }
6736
6737 return ReturnCode;
6738
6739 } /* end of mgsl_get_rx_frame() */
6740
6741 /* mgsl_get_raw_rx_frame()
6742 *
6743 * This function attempts to return a received frame from the
6744 * receive DMA buffers when running in external loop mode. In this mode,
6745 * we will return at most one DMABUFFERSIZE frame to the application.
6746 * The USC receiver is triggering off of DCD going active to start a new
6747 * frame, and DCD going inactive to terminate the frame (similar to
6748 * processing a closing flag character).
6749 *
6750 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6751 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6752 * status field and the RCC field will indicate the length of the
6753 * entire received frame. We take this RCC field and get the modulus
6754 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6755 * last Rx DMA buffer and return that last portion of the frame.
6756 *
6757 * Arguments: info pointer to device extension
6758 * Return Value: true if frame returned, otherwise false
6759 */
6760 static bool mgsl_get_raw_rx_frame(struct mgsl_struct *info)
6761 {
6762 unsigned int CurrentIndex, NextIndex;
6763 unsigned short status;
6764 DMABUFFERENTRY *pBufEntry;
6765 unsigned int framesize = 0;
6766 bool ReturnCode = false;
6767 unsigned long flags;
6768 struct tty_struct *tty = info->port.tty;
6769
6770 /*
6771 * current_rx_buffer points to the 1st buffer of the next available
6772 * receive frame. The status field is set by the 16C32 after
6773 * completing a receive frame. If the status field of this buffer
6774 * is zero, either the USC is still filling this buffer or this
6775 * is one of a series of buffers making up a received frame.
6776 *
6777 * If the count field of this buffer is zero, the USC is either
6778 * using this buffer or has used this buffer. Look at the count
6779 * field of the next buffer. If that next buffer's count is
6780 * non-zero, the USC is still actively using the current buffer.
6781 * Otherwise, if the next buffer's count field is zero, the
6782 * current buffer is complete and the USC is using the next
6783 * buffer.
6784 */
6785 CurrentIndex = NextIndex = info->current_rx_buffer;
6786 ++NextIndex;
6787 if ( NextIndex == info->rx_buffer_count )
6788 NextIndex = 0;
6789
6790 if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
6791 (info->rx_buffer_list[CurrentIndex].count == 0 &&
6792 info->rx_buffer_list[NextIndex].count == 0)) {
6793 /*
6794 * Either the status field of this dma buffer is non-zero
6795 * (indicating the last buffer of a receive frame) or the next
6796 * buffer is marked as in use -- implying this buffer is complete
6797 * and an intermediate buffer for this received frame.
6798 */
6799
6800 status = info->rx_buffer_list[CurrentIndex].status;
6801
6802 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6803 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6804 if ( status & RXSTATUS_SHORT_FRAME )
6805 info->icount.rxshort++;
6806 else if ( status & RXSTATUS_ABORT )
6807 info->icount.rxabort++;
6808 else if ( status & RXSTATUS_OVERRUN )
6809 info->icount.rxover++;
6810 else
6811 info->icount.rxcrc++;
6812 framesize = 0;
6813 } else {
6814 /*
6815 * A receive frame is available, get frame size and status.
6816 *
6817 * The frame size is the starting value of the RCC (which was
6818 * set to 0xffff) minus the ending value of the RCC (decremented
6819 * once for each receive character) minus 2 or 4 for the 16-bit
6820 * or 32-bit CRC.
6821 *
6822 * If the status field is zero, this is an intermediate buffer.
6823 * It's size is 4K.
6824 *
6825 * If the DMA Buffer Entry's Status field is non-zero, the
6826 * receive operation completed normally (ie: DCD dropped). The
6827 * RCC field is valid and holds the received frame size.
6828 * It is possible that the RCC field will be zero on a DMA buffer
6829 * entry with a non-zero status. This can occur if the total
6830 * frame size (number of bytes between the time DCD goes active
6831 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6832 * case the 16C32 has underrun on the RCC count and appears to
6833 * stop updating this counter to let us know the actual received
6834 * frame size. If this happens (non-zero status and zero RCC),
6835 * simply return the entire RxDMA Buffer
6836 */
6837 if ( status ) {
6838 /*
6839 * In the event that the final RxDMA Buffer is
6840 * terminated with a non-zero status and the RCC
6841 * field is zero, we interpret this as the RCC
6842 * having underflowed (received frame > 65535 bytes).
6843 *
6844 * Signal the event to the user by passing back
6845 * a status of RxStatus_CrcError returning the full
6846 * buffer and let the app figure out what data is
6847 * actually valid
6848 */
6849 if ( info->rx_buffer_list[CurrentIndex].rcc )
6850 framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
6851 else
6852 framesize = DMABUFFERSIZE;
6853 }
6854 else
6855 framesize = DMABUFFERSIZE;
6856 }
6857
6858 if ( framesize > DMABUFFERSIZE ) {
6859 /*
6860 * if running in raw sync mode, ISR handler for
6861 * End Of Buffer events terminates all buffers at 4K.
6862 * If this frame size is said to be >4K, get the
6863 * actual number of bytes of the frame in this buffer.
6864 */
6865 framesize = framesize % DMABUFFERSIZE;
6866 }
6867
6868
6869 if ( debug_level >= DEBUG_LEVEL_BH )
6870 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6871 __FILE__,__LINE__,info->device_name,status,framesize);
6872
6873 if ( debug_level >= DEBUG_LEVEL_DATA )
6874 mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
6875 min_t(int, framesize, DMABUFFERSIZE),0);
6876
6877 if (framesize) {
6878 /* copy dma buffer(s) to contiguous intermediate buffer */
6879 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6880
6881 pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
6882 memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
6883 info->icount.rxok++;
6884
6885 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6886 }
6887
6888 /* Free the buffers used by this frame. */
6889 mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
6890
6891 ReturnCode = true;
6892 }
6893
6894
6895 if ( info->rx_enabled && info->rx_overflow ) {
6896 /* The receiver needs to restarted because of
6897 * a receive overflow (buffer or FIFO). If the
6898 * receive buffers are now empty, then restart receiver.
6899 */
6900
6901 if ( !info->rx_buffer_list[CurrentIndex].status &&
6902 info->rx_buffer_list[CurrentIndex].count ) {
6903 spin_lock_irqsave(&info->irq_spinlock,flags);
6904 usc_start_receiver(info);
6905 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6906 }
6907 }
6908
6909 return ReturnCode;
6910
6911 } /* end of mgsl_get_raw_rx_frame() */
6912
6913 /* mgsl_load_tx_dma_buffer()
6914 *
6915 * Load the transmit DMA buffer with the specified data.
6916 *
6917 * Arguments:
6918 *
6919 * info pointer to device extension
6920 * Buffer pointer to buffer containing frame to load
6921 * BufferSize size in bytes of frame in Buffer
6922 *
6923 * Return Value: None
6924 */
6925 static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
6926 const char *Buffer, unsigned int BufferSize)
6927 {
6928 unsigned short Copycount;
6929 unsigned int i = 0;
6930 DMABUFFERENTRY *pBufEntry;
6931
6932 if ( debug_level >= DEBUG_LEVEL_DATA )
6933 mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
6934
6935 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
6936 /* set CMR:13 to start transmit when
6937 * next GoAhead (abort) is received
6938 */
6939 info->cmr_value |= BIT13;
6940 }
6941
6942 /* begin loading the frame in the next available tx dma
6943 * buffer, remember it's starting location for setting
6944 * up tx dma operation
6945 */
6946 i = info->current_tx_buffer;
6947 info->start_tx_dma_buffer = i;
6948
6949 /* Setup the status and RCC (Frame Size) fields of the 1st */
6950 /* buffer entry in the transmit DMA buffer list. */
6951
6952 info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
6953 info->tx_buffer_list[i].rcc = BufferSize;
6954 info->tx_buffer_list[i].count = BufferSize;
6955
6956 /* Copy frame data from 1st source buffer to the DMA buffers. */
6957 /* The frame data may span multiple DMA buffers. */
6958
6959 while( BufferSize ){
6960 /* Get a pointer to next DMA buffer entry. */
6961 pBufEntry = &info->tx_buffer_list[i++];
6962
6963 if ( i == info->tx_buffer_count )
6964 i=0;
6965
6966 /* Calculate the number of bytes that can be copied from */
6967 /* the source buffer to this DMA buffer. */
6968 if ( BufferSize > DMABUFFERSIZE )
6969 Copycount = DMABUFFERSIZE;
6970 else
6971 Copycount = BufferSize;
6972
6973 /* Actually copy data from source buffer to DMA buffer. */
6974 /* Also set the data count for this individual DMA buffer. */
6975 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6976 mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
6977 else
6978 memcpy(pBufEntry->virt_addr, Buffer, Copycount);
6979
6980 pBufEntry->count = Copycount;
6981
6982 /* Advance source pointer and reduce remaining data count. */
6983 Buffer += Copycount;
6984 BufferSize -= Copycount;
6985
6986 ++info->tx_dma_buffers_used;
6987 }
6988
6989 /* remember next available tx dma buffer */
6990 info->current_tx_buffer = i;
6991
6992 } /* end of mgsl_load_tx_dma_buffer() */
6993
6994 /*
6995 * mgsl_register_test()
6996 *
6997 * Performs a register test of the 16C32.
6998 *
6999 * Arguments: info pointer to device instance data
7000 * Return Value: true if test passed, otherwise false
7001 */
7002 static bool mgsl_register_test( struct mgsl_struct *info )
7003 {
7004 static unsigned short BitPatterns[] =
7005 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
7006 static unsigned int Patterncount = ARRAY_SIZE(BitPatterns);
7007 unsigned int i;
7008 bool rc = true;
7009 unsigned long flags;
7010
7011 spin_lock_irqsave(&info->irq_spinlock,flags);
7012 usc_reset(info);
7013
7014 /* Verify the reset state of some registers. */
7015
7016 if ( (usc_InReg( info, SICR ) != 0) ||
7017 (usc_InReg( info, IVR ) != 0) ||
7018 (usc_InDmaReg( info, DIVR ) != 0) ){
7019 rc = false;
7020 }
7021
7022 if ( rc ){
7023 /* Write bit patterns to various registers but do it out of */
7024 /* sync, then read back and verify values. */
7025
7026 for ( i = 0 ; i < Patterncount ; i++ ) {
7027 usc_OutReg( info, TC0R, BitPatterns[i] );
7028 usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
7029 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
7030 usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
7031 usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
7032 usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
7033
7034 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
7035 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
7036 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
7037 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
7038 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
7039 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
7040 rc = false;
7041 break;
7042 }
7043 }
7044 }
7045
7046 usc_reset(info);
7047 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7048
7049 return rc;
7050
7051 } /* end of mgsl_register_test() */
7052
7053 /* mgsl_irq_test() Perform interrupt test of the 16C32.
7054 *
7055 * Arguments: info pointer to device instance data
7056 * Return Value: true if test passed, otherwise false
7057 */
7058 static bool mgsl_irq_test( struct mgsl_struct *info )
7059 {
7060 unsigned long EndTime;
7061 unsigned long flags;
7062
7063 spin_lock_irqsave(&info->irq_spinlock,flags);
7064 usc_reset(info);
7065
7066 /*
7067 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
7068 * The ISR sets irq_occurred to true.
7069 */
7070
7071 info->irq_occurred = false;
7072
7073 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7074 /* Enable INTEN (Port 6, Bit12) */
7075 /* This connects the IRQ request signal to the ISA bus */
7076 /* on the ISA adapter. This has no effect for the PCI adapter */
7077 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
7078
7079 usc_EnableMasterIrqBit(info);
7080 usc_EnableInterrupts(info, IO_PIN);
7081 usc_ClearIrqPendingBits(info, IO_PIN);
7082
7083 usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
7084 usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
7085
7086 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7087
7088 EndTime=100;
7089 while( EndTime-- && !info->irq_occurred ) {
7090 msleep_interruptible(10);
7091 }
7092
7093 spin_lock_irqsave(&info->irq_spinlock,flags);
7094 usc_reset(info);
7095 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7096
7097 return info->irq_occurred;
7098
7099 } /* end of mgsl_irq_test() */
7100
7101 /* mgsl_dma_test()
7102 *
7103 * Perform a DMA test of the 16C32. A small frame is
7104 * transmitted via DMA from a transmit buffer to a receive buffer
7105 * using single buffer DMA mode.
7106 *
7107 * Arguments: info pointer to device instance data
7108 * Return Value: true if test passed, otherwise false
7109 */
7110 static bool mgsl_dma_test( struct mgsl_struct *info )
7111 {
7112 unsigned short FifoLevel;
7113 unsigned long phys_addr;
7114 unsigned int FrameSize;
7115 unsigned int i;
7116 char *TmpPtr;
7117 bool rc = true;
7118 unsigned short status=0;
7119 unsigned long EndTime;
7120 unsigned long flags;
7121 MGSL_PARAMS tmp_params;
7122
7123 /* save current port options */
7124 memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
7125 /* load default port options */
7126 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
7127
7128 #define TESTFRAMESIZE 40
7129
7130 spin_lock_irqsave(&info->irq_spinlock,flags);
7131
7132 /* setup 16C32 for SDLC DMA transfer mode */
7133
7134 usc_reset(info);
7135 usc_set_sdlc_mode(info);
7136 usc_enable_loopback(info,1);
7137
7138 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7139 * field of the buffer entry after fetching buffer address. This
7140 * way we can detect a DMA failure for a DMA read (which should be
7141 * non-destructive to system memory) before we try and write to
7142 * memory (where a failure could corrupt system memory).
7143 */
7144
7145 /* Receive DMA mode Register (RDMR)
7146 *
7147 * <15..14> 11 DMA mode = Linked List Buffer mode
7148 * <13> 1 RSBinA/L = store Rx status Block in List entry
7149 * <12> 0 1 = Clear count of List Entry after fetching
7150 * <11..10> 00 Address mode = Increment
7151 * <9> 1 Terminate Buffer on RxBound
7152 * <8> 0 Bus Width = 16bits
7153 * <7..0> ? status Bits (write as 0s)
7154 *
7155 * 1110 0010 0000 0000 = 0xe200
7156 */
7157
7158 usc_OutDmaReg( info, RDMR, 0xe200 );
7159
7160 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7161
7162
7163 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7164
7165 FrameSize = TESTFRAMESIZE;
7166
7167 /* setup 1st transmit buffer entry: */
7168 /* with frame size and transmit control word */
7169
7170 info->tx_buffer_list[0].count = FrameSize;
7171 info->tx_buffer_list[0].rcc = FrameSize;
7172 info->tx_buffer_list[0].status = 0x4000;
7173
7174 /* build a transmit frame in 1st transmit DMA buffer */
7175
7176 TmpPtr = info->tx_buffer_list[0].virt_addr;
7177 for (i = 0; i < FrameSize; i++ )
7178 *TmpPtr++ = i;
7179
7180 /* setup 1st receive buffer entry: */
7181 /* clear status, set max receive buffer size */
7182
7183 info->rx_buffer_list[0].status = 0;
7184 info->rx_buffer_list[0].count = FrameSize + 4;
7185
7186 /* zero out the 1st receive buffer */
7187
7188 memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
7189
7190 /* Set count field of next buffer entries to prevent */
7191 /* 16C32 from using buffers after the 1st one. */
7192
7193 info->tx_buffer_list[1].count = 0;
7194 info->rx_buffer_list[1].count = 0;
7195
7196
7197 /***************************/
7198 /* Program 16C32 receiver. */
7199 /***************************/
7200
7201 spin_lock_irqsave(&info->irq_spinlock,flags);
7202
7203 /* setup DMA transfers */
7204 usc_RTCmd( info, RTCmd_PurgeRxFifo );
7205
7206 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7207 phys_addr = info->rx_buffer_list[0].phys_entry;
7208 usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
7209 usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
7210
7211 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7212 usc_InDmaReg( info, RDMR );
7213 usc_DmaCmd( info, DmaCmd_InitRxChannel );
7214
7215 /* Enable Receiver (RMR <1..0> = 10) */
7216 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
7217
7218 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7219
7220
7221 /*************************************************************/
7222 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7223 /*************************************************************/
7224
7225 /* Wait 100ms for interrupt. */
7226 EndTime = jiffies + msecs_to_jiffies(100);
7227
7228 for(;;) {
7229 if (time_after(jiffies, EndTime)) {
7230 rc = false;
7231 break;
7232 }
7233
7234 spin_lock_irqsave(&info->irq_spinlock,flags);
7235 status = usc_InDmaReg( info, RDMR );
7236 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7237
7238 if ( !(status & BIT4) && (status & BIT5) ) {
7239 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7240 /* BUSY (BIT 5) is active (channel still active). */
7241 /* This means the buffer entry read has completed. */
7242 break;
7243 }
7244 }
7245
7246
7247 /******************************/
7248 /* Program 16C32 transmitter. */
7249 /******************************/
7250
7251 spin_lock_irqsave(&info->irq_spinlock,flags);
7252
7253 /* Program the Transmit Character Length Register (TCLR) */
7254 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7255
7256 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
7257 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7258
7259 /* Program the address of the 1st DMA Buffer Entry in linked list */
7260
7261 phys_addr = info->tx_buffer_list[0].phys_entry;
7262 usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
7263 usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
7264
7265 /* unlatch Tx status bits, and start transmit channel. */
7266
7267 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
7268 usc_DmaCmd( info, DmaCmd_InitTxChannel );
7269
7270 /* wait for DMA controller to fill transmit FIFO */
7271
7272 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
7273
7274 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7275
7276
7277 /**********************************/
7278 /* WAIT FOR TRANSMIT FIFO TO FILL */
7279 /**********************************/
7280
7281 /* Wait 100ms */
7282 EndTime = jiffies + msecs_to_jiffies(100);
7283
7284 for(;;) {
7285 if (time_after(jiffies, EndTime)) {
7286 rc = false;
7287 break;
7288 }
7289
7290 spin_lock_irqsave(&info->irq_spinlock,flags);
7291 FifoLevel = usc_InReg(info, TICR) >> 8;
7292 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7293
7294 if ( FifoLevel < 16 )
7295 break;
7296 else
7297 if ( FrameSize < 32 ) {
7298 /* This frame is smaller than the entire transmit FIFO */
7299 /* so wait for the entire frame to be loaded. */
7300 if ( FifoLevel <= (32 - FrameSize) )
7301 break;
7302 }
7303 }
7304
7305
7306 if ( rc )
7307 {
7308 /* Enable 16C32 transmitter. */
7309
7310 spin_lock_irqsave(&info->irq_spinlock,flags);
7311
7312 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7313 usc_TCmd( info, TCmd_SendFrame );
7314 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
7315
7316 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7317
7318
7319 /******************************/
7320 /* WAIT FOR TRANSMIT COMPLETE */
7321 /******************************/
7322
7323 /* Wait 100ms */
7324 EndTime = jiffies + msecs_to_jiffies(100);
7325
7326 /* While timer not expired wait for transmit complete */
7327
7328 spin_lock_irqsave(&info->irq_spinlock,flags);
7329 status = usc_InReg( info, TCSR );
7330 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7331
7332 while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) {
7333 if (time_after(jiffies, EndTime)) {
7334 rc = false;
7335 break;
7336 }
7337
7338 spin_lock_irqsave(&info->irq_spinlock,flags);
7339 status = usc_InReg( info, TCSR );
7340 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7341 }
7342 }
7343
7344
7345 if ( rc ){
7346 /* CHECK FOR TRANSMIT ERRORS */
7347 if ( status & (BIT5 + BIT1) )
7348 rc = false;
7349 }
7350
7351 if ( rc ) {
7352 /* WAIT FOR RECEIVE COMPLETE */
7353
7354 /* Wait 100ms */
7355 EndTime = jiffies + msecs_to_jiffies(100);
7356
7357 /* Wait for 16C32 to write receive status to buffer entry. */
7358 status=info->rx_buffer_list[0].status;
7359 while ( status == 0 ) {
7360 if (time_after(jiffies, EndTime)) {
7361 rc = false;
7362 break;
7363 }
7364 status=info->rx_buffer_list[0].status;
7365 }
7366 }
7367
7368
7369 if ( rc ) {
7370 /* CHECK FOR RECEIVE ERRORS */
7371 status = info->rx_buffer_list[0].status;
7372
7373 if ( status & (BIT8 + BIT3 + BIT1) ) {
7374 /* receive error has occurred */
7375 rc = false;
7376 } else {
7377 if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7378 info->rx_buffer_list[0].virt_addr, FrameSize ) ){
7379 rc = false;
7380 }
7381 }
7382 }
7383
7384 spin_lock_irqsave(&info->irq_spinlock,flags);
7385 usc_reset( info );
7386 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7387
7388 /* restore current port options */
7389 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7390
7391 return rc;
7392
7393 } /* end of mgsl_dma_test() */
7394
7395 /* mgsl_adapter_test()
7396 *
7397 * Perform the register, IRQ, and DMA tests for the 16C32.
7398 *
7399 * Arguments: info pointer to device instance data
7400 * Return Value: 0 if success, otherwise -ENODEV
7401 */
7402 static int mgsl_adapter_test( struct mgsl_struct *info )
7403 {
7404 if ( debug_level >= DEBUG_LEVEL_INFO )
7405 printk( "%s(%d):Testing device %s\n",
7406 __FILE__,__LINE__,info->device_name );
7407
7408 if ( !mgsl_register_test( info ) ) {
7409 info->init_error = DiagStatus_AddressFailure;
7410 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7411 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7412 return -ENODEV;
7413 }
7414
7415 if ( !mgsl_irq_test( info ) ) {
7416 info->init_error = DiagStatus_IrqFailure;
7417 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7418 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7419 return -ENODEV;
7420 }
7421
7422 if ( !mgsl_dma_test( info ) ) {
7423 info->init_error = DiagStatus_DmaFailure;
7424 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7425 __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7426 return -ENODEV;
7427 }
7428
7429 if ( debug_level >= DEBUG_LEVEL_INFO )
7430 printk( "%s(%d):device %s passed diagnostics\n",
7431 __FILE__,__LINE__,info->device_name );
7432
7433 return 0;
7434
7435 } /* end of mgsl_adapter_test() */
7436
7437 /* mgsl_memory_test()
7438 *
7439 * Test the shared memory on a PCI adapter.
7440 *
7441 * Arguments: info pointer to device instance data
7442 * Return Value: true if test passed, otherwise false
7443 */
7444 static bool mgsl_memory_test( struct mgsl_struct *info )
7445 {
7446 static unsigned long BitPatterns[] =
7447 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7448 unsigned long Patterncount = ARRAY_SIZE(BitPatterns);
7449 unsigned long i;
7450 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7451 unsigned long * TestAddr;
7452
7453 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
7454 return true;
7455
7456 TestAddr = (unsigned long *)info->memory_base;
7457
7458 /* Test data lines with test pattern at one location. */
7459
7460 for ( i = 0 ; i < Patterncount ; i++ ) {
7461 *TestAddr = BitPatterns[i];
7462 if ( *TestAddr != BitPatterns[i] )
7463 return false;
7464 }
7465
7466 /* Test address lines with incrementing pattern over */
7467 /* entire address range. */
7468
7469 for ( i = 0 ; i < TestLimit ; i++ ) {
7470 *TestAddr = i * 4;
7471 TestAddr++;
7472 }
7473
7474 TestAddr = (unsigned long *)info->memory_base;
7475
7476 for ( i = 0 ; i < TestLimit ; i++ ) {
7477 if ( *TestAddr != i * 4 )
7478 return false;
7479 TestAddr++;
7480 }
7481
7482 memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
7483
7484 return true;
7485
7486 } /* End Of mgsl_memory_test() */
7487
7488
7489 /* mgsl_load_pci_memory()
7490 *
7491 * Load a large block of data into the PCI shared memory.
7492 * Use this instead of memcpy() or memmove() to move data
7493 * into the PCI shared memory.
7494 *
7495 * Notes:
7496 *
7497 * This function prevents the PCI9050 interface chip from hogging
7498 * the adapter local bus, which can starve the 16C32 by preventing
7499 * 16C32 bus master cycles.
7500 *
7501 * The PCI9050 documentation says that the 9050 will always release
7502 * control of the local bus after completing the current read
7503 * or write operation.
7504 *
7505 * It appears that as long as the PCI9050 write FIFO is full, the
7506 * PCI9050 treats all of the writes as a single burst transaction
7507 * and will not release the bus. This causes DMA latency problems
7508 * at high speeds when copying large data blocks to the shared
7509 * memory.
7510 *
7511 * This function in effect, breaks the a large shared memory write
7512 * into multiple transations by interleaving a shared memory read
7513 * which will flush the write FIFO and 'complete' the write
7514 * transation. This allows any pending DMA request to gain control
7515 * of the local bus in a timely fasion.
7516 *
7517 * Arguments:
7518 *
7519 * TargetPtr pointer to target address in PCI shared memory
7520 * SourcePtr pointer to source buffer for data
7521 * count count in bytes of data to copy
7522 *
7523 * Return Value: None
7524 */
7525 static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
7526 unsigned short count )
7527 {
7528 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7529 #define PCI_LOAD_INTERVAL 64
7530
7531 unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
7532 unsigned short Index;
7533 unsigned long Dummy;
7534
7535 for ( Index = 0 ; Index < Intervalcount ; Index++ )
7536 {
7537 memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
7538 Dummy = *((volatile unsigned long *)TargetPtr);
7539 TargetPtr += PCI_LOAD_INTERVAL;
7540 SourcePtr += PCI_LOAD_INTERVAL;
7541 }
7542
7543 memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
7544
7545 } /* End Of mgsl_load_pci_memory() */
7546
7547 static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
7548 {
7549 int i;
7550 int linecount;
7551 if (xmit)
7552 printk("%s tx data:\n",info->device_name);
7553 else
7554 printk("%s rx data:\n",info->device_name);
7555
7556 while(count) {
7557 if (count > 16)
7558 linecount = 16;
7559 else
7560 linecount = count;
7561
7562 for(i=0;i<linecount;i++)
7563 printk("%02X ",(unsigned char)data[i]);
7564 for(;i<17;i++)
7565 printk(" ");
7566 for(i=0;i<linecount;i++) {
7567 if (data[i]>=040 && data[i]<=0176)
7568 printk("%c",data[i]);
7569 else
7570 printk(".");
7571 }
7572 printk("\n");
7573
7574 data += linecount;
7575 count -= linecount;
7576 }
7577 } /* end of mgsl_trace_block() */
7578
7579 /* mgsl_tx_timeout()
7580 *
7581 * called when HDLC frame times out
7582 * update stats and do tx completion processing
7583 *
7584 * Arguments: context pointer to device instance data
7585 * Return Value: None
7586 */
7587 static void mgsl_tx_timeout(unsigned long context)
7588 {
7589 struct mgsl_struct *info = (struct mgsl_struct*)context;
7590 unsigned long flags;
7591
7592 if ( debug_level >= DEBUG_LEVEL_INFO )
7593 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7594 __FILE__,__LINE__,info->device_name);
7595 if(info->tx_active &&
7596 (info->params.mode == MGSL_MODE_HDLC ||
7597 info->params.mode == MGSL_MODE_RAW) ) {
7598 info->icount.txtimeout++;
7599 }
7600 spin_lock_irqsave(&info->irq_spinlock,flags);
7601 info->tx_active = false;
7602 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
7603
7604 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
7605 usc_loopmode_cancel_transmit( info );
7606
7607 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7608
7609 #if SYNCLINK_GENERIC_HDLC
7610 if (info->netcount)
7611 hdlcdev_tx_done(info);
7612 else
7613 #endif
7614 mgsl_bh_transmit(info);
7615
7616 } /* end of mgsl_tx_timeout() */
7617
7618 /* signal that there are no more frames to send, so that
7619 * line is 'released' by echoing RxD to TxD when current
7620 * transmission is complete (or immediately if no tx in progress).
7621 */
7622 static int mgsl_loopmode_send_done( struct mgsl_struct * info )
7623 {
7624 unsigned long flags;
7625
7626 spin_lock_irqsave(&info->irq_spinlock,flags);
7627 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7628 if (info->tx_active)
7629 info->loopmode_send_done_requested = true;
7630 else
7631 usc_loopmode_send_done(info);
7632 }
7633 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7634
7635 return 0;
7636 }
7637
7638 /* release the line by echoing RxD to TxD
7639 * upon completion of a transmit frame
7640 */
7641 static void usc_loopmode_send_done( struct mgsl_struct * info )
7642 {
7643 info->loopmode_send_done_requested = false;
7644 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7645 info->cmr_value &= ~BIT13;
7646 usc_OutReg(info, CMR, info->cmr_value);
7647 }
7648
7649 /* abort a transmit in progress while in HDLC LoopMode
7650 */
7651 static void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
7652 {
7653 /* reset tx dma channel and purge TxFifo */
7654 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7655 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
7656 usc_loopmode_send_done( info );
7657 }
7658
7659 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7660 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7661 * we must clear CMR:13 to begin repeating TxData to RxData
7662 */
7663 static void usc_loopmode_insert_request( struct mgsl_struct * info )
7664 {
7665 info->loopmode_insert_requested = true;
7666
7667 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7668 * begin repeating TxData on RxData (complete insertion)
7669 */
7670 usc_OutReg( info, RICR,
7671 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
7672
7673 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7674 info->cmr_value |= BIT13;
7675 usc_OutReg(info, CMR, info->cmr_value);
7676 }
7677
7678 /* return 1 if station is inserted into the loop, otherwise 0
7679 */
7680 static int usc_loopmode_active( struct mgsl_struct * info)
7681 {
7682 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
7683 }
7684
7685 #if SYNCLINK_GENERIC_HDLC
7686
7687 /**
7688 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7689 * set encoding and frame check sequence (FCS) options
7690 *
7691 * dev pointer to network device structure
7692 * encoding serial encoding setting
7693 * parity FCS setting
7694 *
7695 * returns 0 if success, otherwise error code
7696 */
7697 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
7698 unsigned short parity)
7699 {
7700 struct mgsl_struct *info = dev_to_port(dev);
7701 unsigned char new_encoding;
7702 unsigned short new_crctype;
7703
7704 /* return error if TTY interface open */
7705 if (info->port.count)
7706 return -EBUSY;
7707
7708 switch (encoding)
7709 {
7710 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
7711 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
7712 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
7713 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
7714 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
7715 default: return -EINVAL;
7716 }
7717
7718 switch (parity)
7719 {
7720 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
7721 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
7722 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
7723 default: return -EINVAL;
7724 }
7725
7726 info->params.encoding = new_encoding;
7727 info->params.crc_type = new_crctype;
7728
7729 /* if network interface up, reprogram hardware */
7730 if (info->netcount)
7731 mgsl_program_hw(info);
7732
7733 return 0;
7734 }
7735
7736 /**
7737 * called by generic HDLC layer to send frame
7738 *
7739 * skb socket buffer containing HDLC frame
7740 * dev pointer to network device structure
7741 *
7742 * returns 0 if success, otherwise error code
7743 */
7744 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
7745 {
7746 struct mgsl_struct *info = dev_to_port(dev);
7747 unsigned long flags;
7748
7749 if (debug_level >= DEBUG_LEVEL_INFO)
7750 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
7751
7752 /* stop sending until this frame completes */
7753 netif_stop_queue(dev);
7754
7755 /* copy data to device buffers */
7756 info->xmit_cnt = skb->len;
7757 mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
7758
7759 /* update network statistics */
7760 dev->stats.tx_packets++;
7761 dev->stats.tx_bytes += skb->len;
7762
7763 /* done with socket buffer, so free it */
7764 dev_kfree_skb(skb);
7765
7766 /* save start time for transmit timeout detection */
7767 dev->trans_start = jiffies;
7768
7769 /* start hardware transmitter if necessary */
7770 spin_lock_irqsave(&info->irq_spinlock,flags);
7771 if (!info->tx_active)
7772 usc_start_transmitter(info);
7773 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7774
7775 return 0;
7776 }
7777
7778 /**
7779 * called by network layer when interface enabled
7780 * claim resources and initialize hardware
7781 *
7782 * dev pointer to network device structure
7783 *
7784 * returns 0 if success, otherwise error code
7785 */
7786 static int hdlcdev_open(struct net_device *dev)
7787 {
7788 struct mgsl_struct *info = dev_to_port(dev);
7789 int rc;
7790 unsigned long flags;
7791
7792 if (debug_level >= DEBUG_LEVEL_INFO)
7793 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
7794
7795 /* generic HDLC layer open processing */
7796 if ((rc = hdlc_open(dev)))
7797 return rc;
7798
7799 /* arbitrate between network and tty opens */
7800 spin_lock_irqsave(&info->netlock, flags);
7801 if (info->port.count != 0 || info->netcount != 0) {
7802 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
7803 spin_unlock_irqrestore(&info->netlock, flags);
7804 return -EBUSY;
7805 }
7806 info->netcount=1;
7807 spin_unlock_irqrestore(&info->netlock, flags);
7808
7809 /* claim resources and init adapter */
7810 if ((rc = startup(info)) != 0) {
7811 spin_lock_irqsave(&info->netlock, flags);
7812 info->netcount=0;
7813 spin_unlock_irqrestore(&info->netlock, flags);
7814 return rc;
7815 }
7816
7817 /* assert DTR and RTS, apply hardware settings */
7818 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
7819 mgsl_program_hw(info);
7820
7821 /* enable network layer transmit */
7822 dev->trans_start = jiffies;
7823 netif_start_queue(dev);
7824
7825 /* inform generic HDLC layer of current DCD status */
7826 spin_lock_irqsave(&info->irq_spinlock, flags);
7827 usc_get_serial_signals(info);
7828 spin_unlock_irqrestore(&info->irq_spinlock, flags);
7829 if (info->serial_signals & SerialSignal_DCD)
7830 netif_carrier_on(dev);
7831 else
7832 netif_carrier_off(dev);
7833 return 0;
7834 }
7835
7836 /**
7837 * called by network layer when interface is disabled
7838 * shutdown hardware and release resources
7839 *
7840 * dev pointer to network device structure
7841 *
7842 * returns 0 if success, otherwise error code
7843 */
7844 static int hdlcdev_close(struct net_device *dev)
7845 {
7846 struct mgsl_struct *info = dev_to_port(dev);
7847 unsigned long flags;
7848
7849 if (debug_level >= DEBUG_LEVEL_INFO)
7850 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
7851
7852 netif_stop_queue(dev);
7853
7854 /* shutdown adapter and release resources */
7855 shutdown(info);
7856
7857 hdlc_close(dev);
7858
7859 spin_lock_irqsave(&info->netlock, flags);
7860 info->netcount=0;
7861 spin_unlock_irqrestore(&info->netlock, flags);
7862
7863 return 0;
7864 }
7865
7866 /**
7867 * called by network layer to process IOCTL call to network device
7868 *
7869 * dev pointer to network device structure
7870 * ifr pointer to network interface request structure
7871 * cmd IOCTL command code
7872 *
7873 * returns 0 if success, otherwise error code
7874 */
7875 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7876 {
7877 const size_t size = sizeof(sync_serial_settings);
7878 sync_serial_settings new_line;
7879 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
7880 struct mgsl_struct *info = dev_to_port(dev);
7881 unsigned int flags;
7882
7883 if (debug_level >= DEBUG_LEVEL_INFO)
7884 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
7885
7886 /* return error if TTY interface open */
7887 if (info->port.count)
7888 return -EBUSY;
7889
7890 if (cmd != SIOCWANDEV)
7891 return hdlc_ioctl(dev, ifr, cmd);
7892
7893 switch(ifr->ifr_settings.type) {
7894 case IF_GET_IFACE: /* return current sync_serial_settings */
7895
7896 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
7897 if (ifr->ifr_settings.size < size) {
7898 ifr->ifr_settings.size = size; /* data size wanted */
7899 return -ENOBUFS;
7900 }
7901
7902 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7903 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7904 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7905 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7906
7907 switch (flags){
7908 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
7909 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
7910 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
7911 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
7912 default: new_line.clock_type = CLOCK_DEFAULT;
7913 }
7914
7915 new_line.clock_rate = info->params.clock_speed;
7916 new_line.loopback = info->params.loopback ? 1:0;
7917
7918 if (copy_to_user(line, &new_line, size))
7919 return -EFAULT;
7920 return 0;
7921
7922 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
7923
7924 if(!capable(CAP_NET_ADMIN))
7925 return -EPERM;
7926 if (copy_from_user(&new_line, line, size))
7927 return -EFAULT;
7928
7929 switch (new_line.clock_type)
7930 {
7931 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
7932 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
7933 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
7934 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
7935 case CLOCK_DEFAULT: flags = info->params.flags &
7936 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7937 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7938 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7939 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
7940 default: return -EINVAL;
7941 }
7942
7943 if (new_line.loopback != 0 && new_line.loopback != 1)
7944 return -EINVAL;
7945
7946 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7947 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7948 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7949 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7950 info->params.flags |= flags;
7951
7952 info->params.loopback = new_line.loopback;
7953
7954 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
7955 info->params.clock_speed = new_line.clock_rate;
7956 else
7957 info->params.clock_speed = 0;
7958
7959 /* if network interface up, reprogram hardware */
7960 if (info->netcount)
7961 mgsl_program_hw(info);
7962 return 0;
7963
7964 default:
7965 return hdlc_ioctl(dev, ifr, cmd);
7966 }
7967 }
7968
7969 /**
7970 * called by network layer when transmit timeout is detected
7971 *
7972 * dev pointer to network device structure
7973 */
7974 static void hdlcdev_tx_timeout(struct net_device *dev)
7975 {
7976 struct mgsl_struct *info = dev_to_port(dev);
7977 unsigned long flags;
7978
7979 if (debug_level >= DEBUG_LEVEL_INFO)
7980 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
7981
7982 dev->stats.tx_errors++;
7983 dev->stats.tx_aborted_errors++;
7984
7985 spin_lock_irqsave(&info->irq_spinlock,flags);
7986 usc_stop_transmitter(info);
7987 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7988
7989 netif_wake_queue(dev);
7990 }
7991
7992 /**
7993 * called by device driver when transmit completes
7994 * reenable network layer transmit if stopped
7995 *
7996 * info pointer to device instance information
7997 */
7998 static void hdlcdev_tx_done(struct mgsl_struct *info)
7999 {
8000 if (netif_queue_stopped(info->netdev))
8001 netif_wake_queue(info->netdev);
8002 }
8003
8004 /**
8005 * called by device driver when frame received
8006 * pass frame to network layer
8007 *
8008 * info pointer to device instance information
8009 * buf pointer to buffer contianing frame data
8010 * size count of data bytes in buf
8011 */
8012 static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
8013 {
8014 struct sk_buff *skb = dev_alloc_skb(size);
8015 struct net_device *dev = info->netdev;
8016
8017 if (debug_level >= DEBUG_LEVEL_INFO)
8018 printk("hdlcdev_rx(%s)\n", dev->name);
8019
8020 if (skb == NULL) {
8021 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
8022 dev->name);
8023 dev->stats.rx_dropped++;
8024 return;
8025 }
8026
8027 memcpy(skb_put(skb, size), buf, size);
8028
8029 skb->protocol = hdlc_type_trans(skb, dev);
8030
8031 dev->stats.rx_packets++;
8032 dev->stats.rx_bytes += size;
8033
8034 netif_rx(skb);
8035
8036 dev->last_rx = jiffies;
8037 }
8038
8039 /**
8040 * called by device driver when adding device instance
8041 * do generic HDLC initialization
8042 *
8043 * info pointer to device instance information
8044 *
8045 * returns 0 if success, otherwise error code
8046 */
8047 static int hdlcdev_init(struct mgsl_struct *info)
8048 {
8049 int rc;
8050 struct net_device *dev;
8051 hdlc_device *hdlc;
8052
8053 /* allocate and initialize network and HDLC layer objects */
8054
8055 if (!(dev = alloc_hdlcdev(info))) {
8056 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
8057 return -ENOMEM;
8058 }
8059
8060 /* for network layer reporting purposes only */
8061 dev->base_addr = info->io_base;
8062 dev->irq = info->irq_level;
8063 dev->dma = info->dma_level;
8064
8065 /* network layer callbacks and settings */
8066 dev->do_ioctl = hdlcdev_ioctl;
8067 dev->open = hdlcdev_open;
8068 dev->stop = hdlcdev_close;
8069 dev->tx_timeout = hdlcdev_tx_timeout;
8070 dev->watchdog_timeo = 10*HZ;
8071 dev->tx_queue_len = 50;
8072
8073 /* generic HDLC layer callbacks and settings */
8074 hdlc = dev_to_hdlc(dev);
8075 hdlc->attach = hdlcdev_attach;
8076 hdlc->xmit = hdlcdev_xmit;
8077
8078 /* register objects with HDLC layer */
8079 if ((rc = register_hdlc_device(dev))) {
8080 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
8081 free_netdev(dev);
8082 return rc;
8083 }
8084
8085 info->netdev = dev;
8086 return 0;
8087 }
8088
8089 /**
8090 * called by device driver when removing device instance
8091 * do generic HDLC cleanup
8092 *
8093 * info pointer to device instance information
8094 */
8095 static void hdlcdev_exit(struct mgsl_struct *info)
8096 {
8097 unregister_hdlc_device(info->netdev);
8098 free_netdev(info->netdev);
8099 info->netdev = NULL;
8100 }
8101
8102 #endif /* CONFIG_HDLC */
8103
8104
8105 static int __devinit synclink_init_one (struct pci_dev *dev,
8106 const struct pci_device_id *ent)
8107 {
8108 struct mgsl_struct *info;
8109
8110 if (pci_enable_device(dev)) {
8111 printk("error enabling pci device %p\n", dev);
8112 return -EIO;
8113 }
8114
8115 if (!(info = mgsl_allocate_device())) {
8116 printk("can't allocate device instance data.\n");
8117 return -EIO;
8118 }
8119
8120 /* Copy user configuration info to device instance data */
8121
8122 info->io_base = pci_resource_start(dev, 2);
8123 info->irq_level = dev->irq;
8124 info->phys_memory_base = pci_resource_start(dev, 3);
8125
8126 /* Because veremap only works on page boundaries we must map
8127 * a larger area than is actually implemented for the LCR
8128 * memory range. We map a full page starting at the page boundary.
8129 */
8130 info->phys_lcr_base = pci_resource_start(dev, 0);
8131 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
8132 info->phys_lcr_base &= ~(PAGE_SIZE-1);
8133
8134 info->bus_type = MGSL_BUS_TYPE_PCI;
8135 info->io_addr_size = 8;
8136 info->irq_flags = IRQF_SHARED;
8137
8138 if (dev->device == 0x0210) {
8139 /* Version 1 PCI9030 based universal PCI adapter */
8140 info->misc_ctrl_value = 0x007c4080;
8141 info->hw_version = 1;
8142 } else {
8143 /* Version 0 PCI9050 based 5V PCI adapter
8144 * A PCI9050 bug prevents reading LCR registers if
8145 * LCR base address bit 7 is set. Maintain shadow
8146 * value so we can write to LCR misc control reg.
8147 */
8148 info->misc_ctrl_value = 0x087e4546;
8149 info->hw_version = 0;
8150 }
8151
8152 mgsl_add_device(info);
8153
8154 return 0;
8155 }
8156
8157 static void __devexit synclink_remove_one (struct pci_dev *dev)
8158 {
8159 }
8160
linux-next