2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through platform_device. Structures which
29 * define the configuration needed by the board are defined in a
30 * board structure in arch/ppc/platforms (though I do not
31 * discount the possibility that other architectures could one
34 * The Gianfar Ethernet Controller uses a ring of buffer
35 * descriptors. The beginning is indicated by a register
36 * pointing to the physical address of the start of the ring.
37 * The end is determined by a "wrap" bit being set in the
38 * last descriptor of the ring.
40 * When a packet is received, the RXF bit in the
41 * IEVENT register is set, triggering an interrupt when the
42 * corresponding bit in the IMASK register is also set (if
43 * interrupt coalescing is active, then the interrupt may not
44 * happen immediately, but will wait until either a set number
45 * of frames or amount of time have passed). In NAPI, the
46 * interrupt handler will signal there is work to be done, and
47 * exit. This method will start at the last known empty
48 * descriptor, and process every subsequent descriptor until there
49 * are none left with data (NAPI will stop after a set number of
50 * packets to give time to other tasks, but will eventually
51 * process all the packets). The data arrives inside a
52 * pre-allocated skb, and so after the skb is passed up to the
53 * stack, a new skb must be allocated, and the address field in
54 * the buffer descriptor must be updated to indicate this new
57 * When the kernel requests that a packet be transmitted, the
58 * driver starts where it left off last time, and points the
59 * descriptor at the buffer which was passed in. The driver
60 * then informs the DMA engine that there are packets ready to
61 * be transmitted. Once the controller is finished transmitting
62 * the packet, an interrupt may be triggered (under the same
63 * conditions as for reception, but depending on the TXF bit).
64 * The driver then cleans up the buffer.
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/init.h>
74 #include <linux/delay.h>
75 #include <linux/netdevice.h>
76 #include <linux/etherdevice.h>
77 #include <linux/skbuff.h>
78 #include <linux/if_vlan.h>
79 #include <linux/spinlock.h>
81 #include <linux/platform_device.h>
83 #include <linux/tcp.h>
84 #include <linux/udp.h>
89 #include <asm/uaccess.h>
90 #include <linux/module.h>
91 #include <linux/dma-mapping.h>
92 #include <linux/crc32.h>
93 #include <linux/mii.h>
94 #include <linux/phy.h>
97 #include "gianfar_mii.h"
99 #define TX_TIMEOUT (1*HZ)
100 #undef BRIEF_GFAR_ERRORS
101 #undef VERBOSE_GFAR_ERRORS
103 const char gfar_driver_name
[] = "Gianfar Ethernet";
104 const char gfar_driver_version
[] = "1.3";
106 static int gfar_enet_open(struct net_device
*dev
);
107 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
108 static void gfar_timeout(struct net_device
*dev
);
109 static int gfar_close(struct net_device
*dev
);
110 struct sk_buff
*gfar_new_skb(struct net_device
*dev
);
111 static void gfar_new_rxbdp(struct net_device
*dev
, struct rxbd8
*bdp
,
112 struct sk_buff
*skb
);
113 static int gfar_set_mac_address(struct net_device
*dev
);
114 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
);
115 static irqreturn_t
gfar_error(int irq
, void *dev_id
);
116 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
);
117 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
);
118 static void adjust_link(struct net_device
*dev
);
119 static void init_registers(struct net_device
*dev
);
120 static int init_phy(struct net_device
*dev
);
121 static int gfar_probe(struct platform_device
*pdev
);
122 static int gfar_remove(struct platform_device
*pdev
);
123 static void free_skb_resources(struct gfar_private
*priv
);
124 static void gfar_set_multi(struct net_device
*dev
);
125 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
);
126 static void gfar_configure_serdes(struct net_device
*dev
);
127 static int gfar_poll(struct napi_struct
*napi
, int budget
);
128 #ifdef CONFIG_NET_POLL_CONTROLLER
129 static void gfar_netpoll(struct net_device
*dev
);
131 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
);
132 static int gfar_clean_tx_ring(struct net_device
*dev
);
133 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
, int length
);
134 static void gfar_vlan_rx_register(struct net_device
*netdev
,
135 struct vlan_group
*grp
);
136 void gfar_halt(struct net_device
*dev
);
138 static void gfar_halt_nodisable(struct net_device
*dev
);
140 void gfar_start(struct net_device
*dev
);
141 static void gfar_clear_exact_match(struct net_device
*dev
);
142 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
);
144 extern const struct ethtool_ops gfar_ethtool_ops
;
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
150 /* Returns 1 if incoming frames use an FCB */
151 static inline int gfar_uses_fcb(struct gfar_private
*priv
)
153 return (priv
->vlan_enable
|| priv
->rx_csum_enable
);
156 /* Set up the ethernet device structure, private data,
157 * and anything else we need before we start */
158 static int gfar_probe(struct platform_device
*pdev
)
161 struct net_device
*dev
= NULL
;
162 struct gfar_private
*priv
= NULL
;
163 struct gianfar_platform_data
*einfo
;
166 DECLARE_MAC_BUF(mac
);
168 einfo
= (struct gianfar_platform_data
*) pdev
->dev
.platform_data
;
171 printk(KERN_ERR
"gfar %d: Missing additional data!\n",
177 /* Create an ethernet device instance */
178 dev
= alloc_etherdev(sizeof (*priv
));
183 priv
= netdev_priv(dev
);
186 /* Set the info in the priv to the current info */
189 /* fill out IRQ fields */
190 if (einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
191 priv
->interruptTransmit
= platform_get_irq_byname(pdev
, "tx");
192 priv
->interruptReceive
= platform_get_irq_byname(pdev
, "rx");
193 priv
->interruptError
= platform_get_irq_byname(pdev
, "error");
194 if (priv
->interruptTransmit
< 0 || priv
->interruptReceive
< 0 || priv
->interruptError
< 0)
197 priv
->interruptTransmit
= platform_get_irq(pdev
, 0);
198 if (priv
->interruptTransmit
< 0)
202 /* get a pointer to the register memory */
203 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
204 priv
->regs
= ioremap(r
->start
, sizeof (struct gfar
));
206 if (NULL
== priv
->regs
) {
211 spin_lock_init(&priv
->txlock
);
212 spin_lock_init(&priv
->rxlock
);
213 spin_lock_init(&priv
->bflock
);
215 platform_set_drvdata(pdev
, dev
);
217 /* Stop the DMA engine now, in case it was running before */
218 /* (The firmware could have used it, and left it running). */
219 /* To do this, we write Graceful Receive Stop and Graceful */
220 /* Transmit Stop, and then wait until the corresponding bits */
221 /* in IEVENT indicate the stops have completed. */
222 tempval
= gfar_read(&priv
->regs
->dmactrl
);
223 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
224 gfar_write(&priv
->regs
->dmactrl
, tempval
);
226 tempval
= gfar_read(&priv
->regs
->dmactrl
);
227 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
228 gfar_write(&priv
->regs
->dmactrl
, tempval
);
230 while (!(gfar_read(&priv
->regs
->ievent
) & (IEVENT_GRSC
| IEVENT_GTSC
)))
233 /* Reset MAC layer */
234 gfar_write(&priv
->regs
->maccfg1
, MACCFG1_SOFT_RESET
);
236 tempval
= (MACCFG1_TX_FLOW
| MACCFG1_RX_FLOW
);
237 gfar_write(&priv
->regs
->maccfg1
, tempval
);
239 /* Initialize MACCFG2. */
240 gfar_write(&priv
->regs
->maccfg2
, MACCFG2_INIT_SETTINGS
);
242 /* Initialize ECNTRL */
243 gfar_write(&priv
->regs
->ecntrl
, ECNTRL_INIT_SETTINGS
);
245 /* Copy the station address into the dev structure, */
246 memcpy(dev
->dev_addr
, einfo
->mac_addr
, MAC_ADDR_LEN
);
248 /* Set the dev->base_addr to the gfar reg region */
249 dev
->base_addr
= (unsigned long) (priv
->regs
);
251 SET_NETDEV_DEV(dev
, &pdev
->dev
);
253 /* Fill in the dev structure */
254 dev
->open
= gfar_enet_open
;
255 dev
->hard_start_xmit
= gfar_start_xmit
;
256 dev
->tx_timeout
= gfar_timeout
;
257 dev
->watchdog_timeo
= TX_TIMEOUT
;
258 netif_napi_add(dev
, &priv
->napi
, gfar_poll
, GFAR_DEV_WEIGHT
);
259 #ifdef CONFIG_NET_POLL_CONTROLLER
260 dev
->poll_controller
= gfar_netpoll
;
262 dev
->stop
= gfar_close
;
263 dev
->change_mtu
= gfar_change_mtu
;
265 dev
->set_multicast_list
= gfar_set_multi
;
267 dev
->ethtool_ops
= &gfar_ethtool_ops
;
269 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_CSUM
) {
270 priv
->rx_csum_enable
= 1;
271 dev
->features
|= NETIF_F_IP_CSUM
;
273 priv
->rx_csum_enable
= 0;
277 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_VLAN
) {
278 dev
->vlan_rx_register
= gfar_vlan_rx_register
;
280 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
282 priv
->vlan_enable
= 1;
285 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
) {
286 priv
->extended_hash
= 1;
287 priv
->hash_width
= 9;
289 priv
->hash_regs
[0] = &priv
->regs
->igaddr0
;
290 priv
->hash_regs
[1] = &priv
->regs
->igaddr1
;
291 priv
->hash_regs
[2] = &priv
->regs
->igaddr2
;
292 priv
->hash_regs
[3] = &priv
->regs
->igaddr3
;
293 priv
->hash_regs
[4] = &priv
->regs
->igaddr4
;
294 priv
->hash_regs
[5] = &priv
->regs
->igaddr5
;
295 priv
->hash_regs
[6] = &priv
->regs
->igaddr6
;
296 priv
->hash_regs
[7] = &priv
->regs
->igaddr7
;
297 priv
->hash_regs
[8] = &priv
->regs
->gaddr0
;
298 priv
->hash_regs
[9] = &priv
->regs
->gaddr1
;
299 priv
->hash_regs
[10] = &priv
->regs
->gaddr2
;
300 priv
->hash_regs
[11] = &priv
->regs
->gaddr3
;
301 priv
->hash_regs
[12] = &priv
->regs
->gaddr4
;
302 priv
->hash_regs
[13] = &priv
->regs
->gaddr5
;
303 priv
->hash_regs
[14] = &priv
->regs
->gaddr6
;
304 priv
->hash_regs
[15] = &priv
->regs
->gaddr7
;
307 priv
->extended_hash
= 0;
308 priv
->hash_width
= 8;
310 priv
->hash_regs
[0] = &priv
->regs
->gaddr0
;
311 priv
->hash_regs
[1] = &priv
->regs
->gaddr1
;
312 priv
->hash_regs
[2] = &priv
->regs
->gaddr2
;
313 priv
->hash_regs
[3] = &priv
->regs
->gaddr3
;
314 priv
->hash_regs
[4] = &priv
->regs
->gaddr4
;
315 priv
->hash_regs
[5] = &priv
->regs
->gaddr5
;
316 priv
->hash_regs
[6] = &priv
->regs
->gaddr6
;
317 priv
->hash_regs
[7] = &priv
->regs
->gaddr7
;
320 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_PADDING
)
321 priv
->padding
= DEFAULT_PADDING
;
325 if (dev
->features
& NETIF_F_IP_CSUM
)
326 dev
->hard_header_len
+= GMAC_FCB_LEN
;
328 priv
->rx_buffer_size
= DEFAULT_RX_BUFFER_SIZE
;
329 priv
->tx_ring_size
= DEFAULT_TX_RING_SIZE
;
330 priv
->rx_ring_size
= DEFAULT_RX_RING_SIZE
;
332 priv
->txcoalescing
= DEFAULT_TX_COALESCE
;
333 priv
->txcount
= DEFAULT_TXCOUNT
;
334 priv
->txtime
= DEFAULT_TXTIME
;
335 priv
->rxcoalescing
= DEFAULT_RX_COALESCE
;
336 priv
->rxcount
= DEFAULT_RXCOUNT
;
337 priv
->rxtime
= DEFAULT_RXTIME
;
339 /* Enable most messages by default */
340 priv
->msg_enable
= (NETIF_MSG_IFUP
<< 1 ) - 1;
342 err
= register_netdev(dev
);
345 printk(KERN_ERR
"%s: Cannot register net device, aborting.\n",
350 /* Create all the sysfs files */
351 gfar_init_sysfs(dev
);
353 /* Print out the device info */
354 printk(KERN_INFO DEVICE_NAME
"%s\n",
355 dev
->name
, print_mac(mac
, dev
->dev_addr
));
357 /* Even more device info helps when determining which kernel */
358 /* provided which set of benchmarks. */
359 printk(KERN_INFO
"%s: Running with NAPI enabled\n", dev
->name
);
360 printk(KERN_INFO
"%s: %d/%d RX/TX BD ring size\n",
361 dev
->name
, priv
->rx_ring_size
, priv
->tx_ring_size
);
372 static int gfar_remove(struct platform_device
*pdev
)
374 struct net_device
*dev
= platform_get_drvdata(pdev
);
375 struct gfar_private
*priv
= netdev_priv(dev
);
377 platform_set_drvdata(pdev
, NULL
);
386 static int gfar_suspend(struct platform_device
*pdev
, pm_message_t state
)
388 struct net_device
*dev
= platform_get_drvdata(pdev
);
389 struct gfar_private
*priv
= netdev_priv(dev
);
393 int magic_packet
= priv
->wol_en
&&
394 (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
396 netif_device_detach(dev
);
398 if (netif_running(dev
)) {
399 spin_lock_irqsave(&priv
->txlock
, flags
);
400 spin_lock(&priv
->rxlock
);
402 gfar_halt_nodisable(dev
);
404 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
405 tempval
= gfar_read(&priv
->regs
->maccfg1
);
407 tempval
&= ~MACCFG1_TX_EN
;
410 tempval
&= ~MACCFG1_RX_EN
;
412 gfar_write(&priv
->regs
->maccfg1
, tempval
);
414 spin_unlock(&priv
->rxlock
);
415 spin_unlock_irqrestore(&priv
->txlock
, flags
);
417 #ifdef CONFIG_GFAR_NAPI
418 napi_disable(&priv
->napi
);
422 /* Enable interrupt on Magic Packet */
423 gfar_write(&priv
->regs
->imask
, IMASK_MAG
);
425 /* Enable Magic Packet mode */
426 tempval
= gfar_read(&priv
->regs
->maccfg2
);
427 tempval
|= MACCFG2_MPEN
;
428 gfar_write(&priv
->regs
->maccfg2
, tempval
);
430 phy_stop(priv
->phydev
);
437 static int gfar_resume(struct platform_device
*pdev
)
439 struct net_device
*dev
= platform_get_drvdata(pdev
);
440 struct gfar_private
*priv
= netdev_priv(dev
);
443 int magic_packet
= priv
->wol_en
&&
444 (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
446 if (!netif_running(dev
)) {
447 netif_device_attach(dev
);
451 if (!magic_packet
&& priv
->phydev
)
452 phy_start(priv
->phydev
);
454 /* Disable Magic Packet mode, in case something
458 spin_lock_irqsave(&priv
->txlock
, flags
);
459 spin_lock(&priv
->rxlock
);
461 tempval
= gfar_read(&priv
->regs
->maccfg2
);
462 tempval
&= ~MACCFG2_MPEN
;
463 gfar_write(&priv
->regs
->maccfg2
, tempval
);
467 spin_unlock(&priv
->rxlock
);
468 spin_unlock_irqrestore(&priv
->txlock
, flags
);
470 netif_device_attach(dev
);
472 #ifdef CONFIG_GFAR_NAPI
473 napi_enable(&priv
->napi
);
479 #define gfar_suspend NULL
480 #define gfar_resume NULL
483 /* Reads the controller's registers to determine what interface
484 * connects it to the PHY.
486 static phy_interface_t
gfar_get_interface(struct net_device
*dev
)
488 struct gfar_private
*priv
= netdev_priv(dev
);
489 u32 ecntrl
= gfar_read(&priv
->regs
->ecntrl
);
491 if (ecntrl
& ECNTRL_SGMII_MODE
)
492 return PHY_INTERFACE_MODE_SGMII
;
494 if (ecntrl
& ECNTRL_TBI_MODE
) {
495 if (ecntrl
& ECNTRL_REDUCED_MODE
)
496 return PHY_INTERFACE_MODE_RTBI
;
498 return PHY_INTERFACE_MODE_TBI
;
501 if (ecntrl
& ECNTRL_REDUCED_MODE
) {
502 if (ecntrl
& ECNTRL_REDUCED_MII_MODE
)
503 return PHY_INTERFACE_MODE_RMII
;
505 phy_interface_t interface
= priv
->einfo
->interface
;
508 * This isn't autodetected right now, so it must
509 * be set by the device tree or platform code.
511 if (interface
== PHY_INTERFACE_MODE_RGMII_ID
)
512 return PHY_INTERFACE_MODE_RGMII_ID
;
514 return PHY_INTERFACE_MODE_RGMII
;
518 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
)
519 return PHY_INTERFACE_MODE_GMII
;
521 return PHY_INTERFACE_MODE_MII
;
525 /* Initializes driver's PHY state, and attaches to the PHY.
526 * Returns 0 on success.
528 static int init_phy(struct net_device
*dev
)
530 struct gfar_private
*priv
= netdev_priv(dev
);
531 uint gigabit_support
=
532 priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
?
533 SUPPORTED_1000baseT_Full
: 0;
534 struct phy_device
*phydev
;
535 char phy_id
[BUS_ID_SIZE
];
536 phy_interface_t interface
;
540 priv
->oldduplex
= -1;
542 snprintf(phy_id
, BUS_ID_SIZE
, PHY_ID_FMT
, priv
->einfo
->bus_id
, priv
->einfo
->phy_id
);
544 interface
= gfar_get_interface(dev
);
546 phydev
= phy_connect(dev
, phy_id
, &adjust_link
, 0, interface
);
548 if (interface
== PHY_INTERFACE_MODE_SGMII
)
549 gfar_configure_serdes(dev
);
551 if (IS_ERR(phydev
)) {
552 printk(KERN_ERR
"%s: Could not attach to PHY\n", dev
->name
);
553 return PTR_ERR(phydev
);
556 /* Remove any features not supported by the controller */
557 phydev
->supported
&= (GFAR_SUPPORTED
| gigabit_support
);
558 phydev
->advertising
= phydev
->supported
;
560 priv
->phydev
= phydev
;
566 * Initialize TBI PHY interface for communicating with the
567 * SERDES lynx PHY on the chip. We communicate with this PHY
568 * through the MDIO bus on each controller, treating it as a
569 * "normal" PHY at the address found in the TBIPA register. We assume
570 * that the TBIPA register is valid. Either the MDIO bus code will set
571 * it to a value that doesn't conflict with other PHYs on the bus, or the
572 * value doesn't matter, as there are no other PHYs on the bus.
574 static void gfar_configure_serdes(struct net_device
*dev
)
576 struct gfar_private
*priv
= netdev_priv(dev
);
577 struct gfar_mii __iomem
*regs
=
578 (void __iomem
*)&priv
->regs
->gfar_mii_regs
;
579 int tbipa
= gfar_read(&priv
->regs
->tbipa
);
581 /* Single clk mode, mii mode off(for serdes communication) */
582 gfar_local_mdio_write(regs
, tbipa
, MII_TBICON
, TBICON_CLK_SELECT
);
584 gfar_local_mdio_write(regs
, tbipa
, MII_ADVERTISE
,
585 ADVERTISE_1000XFULL
| ADVERTISE_1000XPAUSE
|
586 ADVERTISE_1000XPSE_ASYM
);
588 gfar_local_mdio_write(regs
, tbipa
, MII_BMCR
, BMCR_ANENABLE
|
589 BMCR_ANRESTART
| BMCR_FULLDPLX
| BMCR_SPEED1000
);
592 static void init_registers(struct net_device
*dev
)
594 struct gfar_private
*priv
= netdev_priv(dev
);
597 gfar_write(&priv
->regs
->ievent
, IEVENT_INIT_CLEAR
);
599 /* Initialize IMASK */
600 gfar_write(&priv
->regs
->imask
, IMASK_INIT_CLEAR
);
602 /* Init hash registers to zero */
603 gfar_write(&priv
->regs
->igaddr0
, 0);
604 gfar_write(&priv
->regs
->igaddr1
, 0);
605 gfar_write(&priv
->regs
->igaddr2
, 0);
606 gfar_write(&priv
->regs
->igaddr3
, 0);
607 gfar_write(&priv
->regs
->igaddr4
, 0);
608 gfar_write(&priv
->regs
->igaddr5
, 0);
609 gfar_write(&priv
->regs
->igaddr6
, 0);
610 gfar_write(&priv
->regs
->igaddr7
, 0);
612 gfar_write(&priv
->regs
->gaddr0
, 0);
613 gfar_write(&priv
->regs
->gaddr1
, 0);
614 gfar_write(&priv
->regs
->gaddr2
, 0);
615 gfar_write(&priv
->regs
->gaddr3
, 0);
616 gfar_write(&priv
->regs
->gaddr4
, 0);
617 gfar_write(&priv
->regs
->gaddr5
, 0);
618 gfar_write(&priv
->regs
->gaddr6
, 0);
619 gfar_write(&priv
->regs
->gaddr7
, 0);
621 /* Zero out the rmon mib registers if it has them */
622 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_RMON
) {
623 memset_io(&(priv
->regs
->rmon
), 0, sizeof (struct rmon_mib
));
625 /* Mask off the CAM interrupts */
626 gfar_write(&priv
->regs
->rmon
.cam1
, 0xffffffff);
627 gfar_write(&priv
->regs
->rmon
.cam2
, 0xffffffff);
630 /* Initialize the max receive buffer length */
631 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
633 /* Initialize the Minimum Frame Length Register */
634 gfar_write(&priv
->regs
->minflr
, MINFLR_INIT_SETTINGS
);
639 /* Halt the receive and transmit queues */
640 static void gfar_halt_nodisable(struct net_device
*dev
)
642 struct gfar_private
*priv
= netdev_priv(dev
);
643 struct gfar __iomem
*regs
= priv
->regs
;
646 /* Mask all interrupts */
647 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
649 /* Clear all interrupts */
650 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
652 /* Stop the DMA, and wait for it to stop */
653 tempval
= gfar_read(&priv
->regs
->dmactrl
);
654 if ((tempval
& (DMACTRL_GRS
| DMACTRL_GTS
))
655 != (DMACTRL_GRS
| DMACTRL_GTS
)) {
656 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
657 gfar_write(&priv
->regs
->dmactrl
, tempval
);
659 while (!(gfar_read(&priv
->regs
->ievent
) &
660 (IEVENT_GRSC
| IEVENT_GTSC
)))
666 /* Halt the receive and transmit queues */
667 void gfar_halt(struct net_device
*dev
)
669 struct gfar_private
*priv
= netdev_priv(dev
);
670 struct gfar __iomem
*regs
= priv
->regs
;
673 /* Disable Rx and Tx */
674 tempval
= gfar_read(®s
->maccfg1
);
675 tempval
&= ~(MACCFG1_RX_EN
| MACCFG1_TX_EN
);
676 gfar_write(®s
->maccfg1
, tempval
);
679 void stop_gfar(struct net_device
*dev
)
681 struct gfar_private
*priv
= netdev_priv(dev
);
682 struct gfar __iomem
*regs
= priv
->regs
;
685 phy_stop(priv
->phydev
);
688 spin_lock_irqsave(&priv
->txlock
, flags
);
689 spin_lock(&priv
->rxlock
);
693 spin_unlock(&priv
->rxlock
);
694 spin_unlock_irqrestore(&priv
->txlock
, flags
);
697 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
698 free_irq(priv
->interruptError
, dev
);
699 free_irq(priv
->interruptTransmit
, dev
);
700 free_irq(priv
->interruptReceive
, dev
);
702 free_irq(priv
->interruptTransmit
, dev
);
705 free_skb_resources(priv
);
707 dma_free_coherent(&dev
->dev
,
708 sizeof(struct txbd8
)*priv
->tx_ring_size
709 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
711 gfar_read(®s
->tbase0
));
714 /* If there are any tx skbs or rx skbs still around, free them.
715 * Then free tx_skbuff and rx_skbuff */
716 static void free_skb_resources(struct gfar_private
*priv
)
722 /* Go through all the buffer descriptors and free their data buffers */
723 txbdp
= priv
->tx_bd_base
;
725 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
727 if (priv
->tx_skbuff
[i
]) {
728 dma_unmap_single(&priv
->dev
->dev
, txbdp
->bufPtr
,
731 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
732 priv
->tx_skbuff
[i
] = NULL
;
738 kfree(priv
->tx_skbuff
);
740 rxbdp
= priv
->rx_bd_base
;
742 /* rx_skbuff is not guaranteed to be allocated, so only
743 * free it and its contents if it is allocated */
744 if(priv
->rx_skbuff
!= NULL
) {
745 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
746 if (priv
->rx_skbuff
[i
]) {
747 dma_unmap_single(&priv
->dev
->dev
, rxbdp
->bufPtr
,
748 priv
->rx_buffer_size
,
751 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
752 priv
->rx_skbuff
[i
] = NULL
;
762 kfree(priv
->rx_skbuff
);
766 void gfar_start(struct net_device
*dev
)
768 struct gfar_private
*priv
= netdev_priv(dev
);
769 struct gfar __iomem
*regs
= priv
->regs
;
772 /* Enable Rx and Tx in MACCFG1 */
773 tempval
= gfar_read(®s
->maccfg1
);
774 tempval
|= (MACCFG1_RX_EN
| MACCFG1_TX_EN
);
775 gfar_write(®s
->maccfg1
, tempval
);
777 /* Initialize DMACTRL to have WWR and WOP */
778 tempval
= gfar_read(&priv
->regs
->dmactrl
);
779 tempval
|= DMACTRL_INIT_SETTINGS
;
780 gfar_write(&priv
->regs
->dmactrl
, tempval
);
782 /* Make sure we aren't stopped */
783 tempval
= gfar_read(&priv
->regs
->dmactrl
);
784 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
785 gfar_write(&priv
->regs
->dmactrl
, tempval
);
787 /* Clear THLT/RHLT, so that the DMA starts polling now */
788 gfar_write(®s
->tstat
, TSTAT_CLEAR_THALT
);
789 gfar_write(®s
->rstat
, RSTAT_CLEAR_RHALT
);
791 /* Unmask the interrupts we look for */
792 gfar_write(®s
->imask
, IMASK_DEFAULT
);
795 /* Bring the controller up and running */
796 int startup_gfar(struct net_device
*dev
)
803 struct gfar_private
*priv
= netdev_priv(dev
);
804 struct gfar __iomem
*regs
= priv
->regs
;
809 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
811 /* Allocate memory for the buffer descriptors */
812 vaddr
= (unsigned long) dma_alloc_coherent(&dev
->dev
,
813 sizeof (struct txbd8
) * priv
->tx_ring_size
+
814 sizeof (struct rxbd8
) * priv
->rx_ring_size
,
818 if (netif_msg_ifup(priv
))
819 printk(KERN_ERR
"%s: Could not allocate buffer descriptors!\n",
824 priv
->tx_bd_base
= (struct txbd8
*) vaddr
;
826 /* enet DMA only understands physical addresses */
827 gfar_write(®s
->tbase0
, addr
);
829 /* Start the rx descriptor ring where the tx ring leaves off */
830 addr
= addr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
831 vaddr
= vaddr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
832 priv
->rx_bd_base
= (struct rxbd8
*) vaddr
;
833 gfar_write(®s
->rbase0
, addr
);
835 /* Setup the skbuff rings */
837 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
838 priv
->tx_ring_size
, GFP_KERNEL
);
840 if (NULL
== priv
->tx_skbuff
) {
841 if (netif_msg_ifup(priv
))
842 printk(KERN_ERR
"%s: Could not allocate tx_skbuff\n",
848 for (i
= 0; i
< priv
->tx_ring_size
; i
++)
849 priv
->tx_skbuff
[i
] = NULL
;
852 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
853 priv
->rx_ring_size
, GFP_KERNEL
);
855 if (NULL
== priv
->rx_skbuff
) {
856 if (netif_msg_ifup(priv
))
857 printk(KERN_ERR
"%s: Could not allocate rx_skbuff\n",
863 for (i
= 0; i
< priv
->rx_ring_size
; i
++)
864 priv
->rx_skbuff
[i
] = NULL
;
866 /* Initialize some variables in our dev structure */
867 priv
->dirty_tx
= priv
->cur_tx
= priv
->tx_bd_base
;
868 priv
->cur_rx
= priv
->rx_bd_base
;
869 priv
->skb_curtx
= priv
->skb_dirtytx
= 0;
872 /* Initialize Transmit Descriptor Ring */
873 txbdp
= priv
->tx_bd_base
;
874 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
881 /* Set the last descriptor in the ring to indicate wrap */
883 txbdp
->status
|= TXBD_WRAP
;
885 rxbdp
= priv
->rx_bd_base
;
886 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
889 skb
= gfar_new_skb(dev
);
892 printk(KERN_ERR
"%s: Can't allocate RX buffers\n",
895 goto err_rxalloc_fail
;
898 priv
->rx_skbuff
[i
] = skb
;
900 gfar_new_rxbdp(dev
, rxbdp
, skb
);
905 /* Set the last descriptor in the ring to wrap */
907 rxbdp
->status
|= RXBD_WRAP
;
909 /* If the device has multiple interrupts, register for
910 * them. Otherwise, only register for the one */
911 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
912 /* Install our interrupt handlers for Error,
913 * Transmit, and Receive */
914 if (request_irq(priv
->interruptError
, gfar_error
,
915 0, "enet_error", dev
) < 0) {
916 if (netif_msg_intr(priv
))
917 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
918 dev
->name
, priv
->interruptError
);
924 if (request_irq(priv
->interruptTransmit
, gfar_transmit
,
925 0, "enet_tx", dev
) < 0) {
926 if (netif_msg_intr(priv
))
927 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
928 dev
->name
, priv
->interruptTransmit
);
935 if (request_irq(priv
->interruptReceive
, gfar_receive
,
936 0, "enet_rx", dev
) < 0) {
937 if (netif_msg_intr(priv
))
938 printk(KERN_ERR
"%s: Can't get IRQ %d (receive0)\n",
939 dev
->name
, priv
->interruptReceive
);
945 if (request_irq(priv
->interruptTransmit
, gfar_interrupt
,
946 0, "gfar_interrupt", dev
) < 0) {
947 if (netif_msg_intr(priv
))
948 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
949 dev
->name
, priv
->interruptError
);
956 phy_start(priv
->phydev
);
958 /* Configure the coalescing support */
959 if (priv
->txcoalescing
)
960 gfar_write(®s
->txic
,
961 mk_ic_value(priv
->txcount
, priv
->txtime
));
963 gfar_write(®s
->txic
, 0);
965 if (priv
->rxcoalescing
)
966 gfar_write(®s
->rxic
,
967 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
969 gfar_write(®s
->rxic
, 0);
971 if (priv
->rx_csum_enable
)
972 rctrl
|= RCTRL_CHECKSUMMING
;
974 if (priv
->extended_hash
) {
975 rctrl
|= RCTRL_EXTHASH
;
977 gfar_clear_exact_match(dev
);
981 if (priv
->vlan_enable
)
985 rctrl
&= ~RCTRL_PAL_MASK
;
986 rctrl
|= RCTRL_PADDING(priv
->padding
);
989 /* Init rctrl based on our settings */
990 gfar_write(&priv
->regs
->rctrl
, rctrl
);
992 if (dev
->features
& NETIF_F_IP_CSUM
)
993 gfar_write(&priv
->regs
->tctrl
, TCTRL_INIT_CSUM
);
995 /* Set the extraction length and index */
996 attrs
= ATTRELI_EL(priv
->rx_stash_size
) |
997 ATTRELI_EI(priv
->rx_stash_index
);
999 gfar_write(&priv
->regs
->attreli
, attrs
);
1001 /* Start with defaults, and add stashing or locking
1002 * depending on the approprate variables */
1003 attrs
= ATTR_INIT_SETTINGS
;
1005 if (priv
->bd_stash_en
)
1006 attrs
|= ATTR_BDSTASH
;
1008 if (priv
->rx_stash_size
!= 0)
1009 attrs
|= ATTR_BUFSTASH
;
1011 gfar_write(&priv
->regs
->attr
, attrs
);
1013 gfar_write(&priv
->regs
->fifo_tx_thr
, priv
->fifo_threshold
);
1014 gfar_write(&priv
->regs
->fifo_tx_starve
, priv
->fifo_starve
);
1015 gfar_write(&priv
->regs
->fifo_tx_starve_shutoff
, priv
->fifo_starve_off
);
1017 /* Start the controller */
1023 free_irq(priv
->interruptTransmit
, dev
);
1025 free_irq(priv
->interruptError
, dev
);
1029 free_skb_resources(priv
);
1031 dma_free_coherent(&dev
->dev
,
1032 sizeof(struct txbd8
)*priv
->tx_ring_size
1033 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
1035 gfar_read(®s
->tbase0
));
1040 /* Called when something needs to use the ethernet device */
1041 /* Returns 0 for success. */
1042 static int gfar_enet_open(struct net_device
*dev
)
1044 struct gfar_private
*priv
= netdev_priv(dev
);
1047 napi_enable(&priv
->napi
);
1049 /* Initialize a bunch of registers */
1050 init_registers(dev
);
1052 gfar_set_mac_address(dev
);
1054 err
= init_phy(dev
);
1057 napi_disable(&priv
->napi
);
1061 err
= startup_gfar(dev
);
1063 napi_disable(&priv
->napi
);
1067 netif_start_queue(dev
);
1072 static inline struct txfcb
*gfar_add_fcb(struct sk_buff
*skb
, struct txbd8
*bdp
)
1074 struct txfcb
*fcb
= (struct txfcb
*)skb_push (skb
, GMAC_FCB_LEN
);
1076 memset(fcb
, 0, GMAC_FCB_LEN
);
1081 static inline void gfar_tx_checksum(struct sk_buff
*skb
, struct txfcb
*fcb
)
1085 /* If we're here, it's a IP packet with a TCP or UDP
1086 * payload. We set it to checksum, using a pseudo-header
1089 flags
= TXFCB_DEFAULT
;
1091 /* Tell the controller what the protocol is */
1092 /* And provide the already calculated phcs */
1093 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
) {
1095 fcb
->phcs
= udp_hdr(skb
)->check
;
1097 fcb
->phcs
= tcp_hdr(skb
)->check
;
1099 /* l3os is the distance between the start of the
1100 * frame (skb->data) and the start of the IP hdr.
1101 * l4os is the distance between the start of the
1102 * l3 hdr and the l4 hdr */
1103 fcb
->l3os
= (u16
)(skb_network_offset(skb
) - GMAC_FCB_LEN
);
1104 fcb
->l4os
= skb_network_header_len(skb
);
1109 void inline gfar_tx_vlan(struct sk_buff
*skb
, struct txfcb
*fcb
)
1111 fcb
->flags
|= TXFCB_VLN
;
1112 fcb
->vlctl
= vlan_tx_tag_get(skb
);
1115 /* This is called by the kernel when a frame is ready for transmission. */
1116 /* It is pointed to by the dev->hard_start_xmit function pointer */
1117 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1119 struct gfar_private
*priv
= netdev_priv(dev
);
1120 struct txfcb
*fcb
= NULL
;
1121 struct txbd8
*txbdp
;
1123 unsigned long flags
;
1125 /* Update transmit stats */
1126 dev
->stats
.tx_bytes
+= skb
->len
;
1129 spin_lock_irqsave(&priv
->txlock
, flags
);
1131 /* Point at the first free tx descriptor */
1132 txbdp
= priv
->cur_tx
;
1134 /* Clear all but the WRAP status flags */
1135 status
= txbdp
->status
& TXBD_WRAP
;
1137 /* Set up checksumming */
1138 if (likely((dev
->features
& NETIF_F_IP_CSUM
)
1139 && (CHECKSUM_PARTIAL
== skb
->ip_summed
))) {
1140 fcb
= gfar_add_fcb(skb
, txbdp
);
1142 gfar_tx_checksum(skb
, fcb
);
1145 if (priv
->vlan_enable
&&
1146 unlikely(priv
->vlgrp
&& vlan_tx_tag_present(skb
))) {
1147 if (unlikely(NULL
== fcb
)) {
1148 fcb
= gfar_add_fcb(skb
, txbdp
);
1152 gfar_tx_vlan(skb
, fcb
);
1155 /* Set buffer length and pointer */
1156 txbdp
->length
= skb
->len
;
1157 txbdp
->bufPtr
= dma_map_single(&dev
->dev
, skb
->data
,
1158 skb
->len
, DMA_TO_DEVICE
);
1160 /* Save the skb pointer so we can free it later */
1161 priv
->tx_skbuff
[priv
->skb_curtx
] = skb
;
1163 /* Update the current skb pointer (wrapping if this was the last) */
1165 (priv
->skb_curtx
+ 1) & TX_RING_MOD_MASK(priv
->tx_ring_size
);
1167 /* Flag the BD as interrupt-causing */
1168 status
|= TXBD_INTERRUPT
;
1170 /* Flag the BD as ready to go, last in frame, and */
1171 /* in need of CRC */
1172 status
|= (TXBD_READY
| TXBD_LAST
| TXBD_CRC
);
1174 dev
->trans_start
= jiffies
;
1176 /* The powerpc-specific eieio() is used, as wmb() has too strong
1177 * semantics (it requires synchronization between cacheable and
1178 * uncacheable mappings, which eieio doesn't provide and which we
1179 * don't need), thus requiring a more expensive sync instruction. At
1180 * some point, the set of architecture-independent barrier functions
1181 * should be expanded to include weaker barriers.
1185 txbdp
->status
= status
;
1187 /* If this was the last BD in the ring, the next one */
1188 /* is at the beginning of the ring */
1189 if (txbdp
->status
& TXBD_WRAP
)
1190 txbdp
= priv
->tx_bd_base
;
1194 /* If the next BD still needs to be cleaned up, then the bds
1195 are full. We need to tell the kernel to stop sending us stuff. */
1196 if (txbdp
== priv
->dirty_tx
) {
1197 netif_stop_queue(dev
);
1199 dev
->stats
.tx_fifo_errors
++;
1202 /* Update the current txbd to the next one */
1203 priv
->cur_tx
= txbdp
;
1205 /* Tell the DMA to go go go */
1206 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
1209 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1214 /* Stops the kernel queue, and halts the controller */
1215 static int gfar_close(struct net_device
*dev
)
1217 struct gfar_private
*priv
= netdev_priv(dev
);
1219 napi_disable(&priv
->napi
);
1223 /* Disconnect from the PHY */
1224 phy_disconnect(priv
->phydev
);
1225 priv
->phydev
= NULL
;
1227 netif_stop_queue(dev
);
1232 /* Changes the mac address if the controller is not running. */
1233 static int gfar_set_mac_address(struct net_device
*dev
)
1235 gfar_set_mac_for_addr(dev
, 0, dev
->dev_addr
);
1241 /* Enables and disables VLAN insertion/extraction */
1242 static void gfar_vlan_rx_register(struct net_device
*dev
,
1243 struct vlan_group
*grp
)
1245 struct gfar_private
*priv
= netdev_priv(dev
);
1246 unsigned long flags
;
1249 spin_lock_irqsave(&priv
->rxlock
, flags
);
1254 /* Enable VLAN tag insertion */
1255 tempval
= gfar_read(&priv
->regs
->tctrl
);
1256 tempval
|= TCTRL_VLINS
;
1258 gfar_write(&priv
->regs
->tctrl
, tempval
);
1260 /* Enable VLAN tag extraction */
1261 tempval
= gfar_read(&priv
->regs
->rctrl
);
1262 tempval
|= RCTRL_VLEX
;
1263 gfar_write(&priv
->regs
->rctrl
, tempval
);
1265 /* Disable VLAN tag insertion */
1266 tempval
= gfar_read(&priv
->regs
->tctrl
);
1267 tempval
&= ~TCTRL_VLINS
;
1268 gfar_write(&priv
->regs
->tctrl
, tempval
);
1270 /* Disable VLAN tag extraction */
1271 tempval
= gfar_read(&priv
->regs
->rctrl
);
1272 tempval
&= ~RCTRL_VLEX
;
1273 gfar_write(&priv
->regs
->rctrl
, tempval
);
1276 spin_unlock_irqrestore(&priv
->rxlock
, flags
);
1279 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
)
1281 int tempsize
, tempval
;
1282 struct gfar_private
*priv
= netdev_priv(dev
);
1283 int oldsize
= priv
->rx_buffer_size
;
1284 int frame_size
= new_mtu
+ ETH_HLEN
;
1286 if (priv
->vlan_enable
)
1287 frame_size
+= VLAN_HLEN
;
1289 if (gfar_uses_fcb(priv
))
1290 frame_size
+= GMAC_FCB_LEN
;
1292 frame_size
+= priv
->padding
;
1294 if ((frame_size
< 64) || (frame_size
> JUMBO_FRAME_SIZE
)) {
1295 if (netif_msg_drv(priv
))
1296 printk(KERN_ERR
"%s: Invalid MTU setting\n",
1302 (frame_size
& ~(INCREMENTAL_BUFFER_SIZE
- 1)) +
1303 INCREMENTAL_BUFFER_SIZE
;
1305 /* Only stop and start the controller if it isn't already
1306 * stopped, and we changed something */
1307 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1310 priv
->rx_buffer_size
= tempsize
;
1314 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
1315 gfar_write(&priv
->regs
->maxfrm
, priv
->rx_buffer_size
);
1317 /* If the mtu is larger than the max size for standard
1318 * ethernet frames (ie, a jumbo frame), then set maccfg2
1319 * to allow huge frames, and to check the length */
1320 tempval
= gfar_read(&priv
->regs
->maccfg2
);
1322 if (priv
->rx_buffer_size
> DEFAULT_RX_BUFFER_SIZE
)
1323 tempval
|= (MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1325 tempval
&= ~(MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1327 gfar_write(&priv
->regs
->maccfg2
, tempval
);
1329 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1335 /* gfar_timeout gets called when a packet has not been
1336 * transmitted after a set amount of time.
1337 * For now, assume that clearing out all the structures, and
1338 * starting over will fix the problem. */
1339 static void gfar_timeout(struct net_device
*dev
)
1341 dev
->stats
.tx_errors
++;
1343 if (dev
->flags
& IFF_UP
) {
1348 netif_tx_schedule_all(dev
);
1351 /* Interrupt Handler for Transmit complete */
1352 static int gfar_clean_tx_ring(struct net_device
*dev
)
1355 struct gfar_private
*priv
= netdev_priv(dev
);
1358 bdp
= priv
->dirty_tx
;
1359 while ((bdp
->status
& TXBD_READY
) == 0) {
1360 /* If dirty_tx and cur_tx are the same, then either the */
1361 /* ring is empty or full now (it could only be full in the beginning, */
1362 /* obviously). If it is empty, we are done. */
1363 if ((bdp
== priv
->cur_tx
) && (netif_queue_stopped(dev
) == 0))
1368 /* Deferred means some collisions occurred during transmit, */
1369 /* but we eventually sent the packet. */
1370 if (bdp
->status
& TXBD_DEF
)
1371 dev
->stats
.collisions
++;
1373 /* Free the sk buffer associated with this TxBD */
1374 dev_kfree_skb_irq(priv
->tx_skbuff
[priv
->skb_dirtytx
]);
1376 priv
->tx_skbuff
[priv
->skb_dirtytx
] = NULL
;
1378 (priv
->skb_dirtytx
+
1379 1) & TX_RING_MOD_MASK(priv
->tx_ring_size
);
1381 /* Clean BD length for empty detection */
1384 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1385 if (bdp
->status
& TXBD_WRAP
)
1386 bdp
= priv
->tx_bd_base
;
1390 /* Move dirty_tx to be the next bd */
1391 priv
->dirty_tx
= bdp
;
1393 /* We freed a buffer, so now we can restart transmission */
1394 if (netif_queue_stopped(dev
))
1395 netif_wake_queue(dev
);
1396 } /* while ((bdp->status & TXBD_READY) == 0) */
1398 dev
->stats
.tx_packets
+= howmany
;
1403 /* Interrupt Handler for Transmit complete */
1404 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
)
1406 struct net_device
*dev
= (struct net_device
*) dev_id
;
1407 struct gfar_private
*priv
= netdev_priv(dev
);
1410 gfar_write(&priv
->regs
->ievent
, IEVENT_TX_MASK
);
1413 spin_lock(&priv
->txlock
);
1415 gfar_clean_tx_ring(dev
);
1417 /* If we are coalescing the interrupts, reset the timer */
1418 /* Otherwise, clear it */
1419 if (likely(priv
->txcoalescing
)) {
1420 gfar_write(&priv
->regs
->txic
, 0);
1421 gfar_write(&priv
->regs
->txic
,
1422 mk_ic_value(priv
->txcount
, priv
->txtime
));
1425 spin_unlock(&priv
->txlock
);
1430 static void gfar_new_rxbdp(struct net_device
*dev
, struct rxbd8
*bdp
,
1431 struct sk_buff
*skb
)
1433 struct gfar_private
*priv
= netdev_priv(dev
);
1434 u32
* status_len
= (u32
*)bdp
;
1437 bdp
->bufPtr
= dma_map_single(&dev
->dev
, skb
->data
,
1438 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
1440 flags
= RXBD_EMPTY
| RXBD_INTERRUPT
;
1442 if (bdp
== priv
->rx_bd_base
+ priv
->rx_ring_size
- 1)
1447 *status_len
= (u32
)flags
<< 16;
1451 struct sk_buff
* gfar_new_skb(struct net_device
*dev
)
1453 unsigned int alignamount
;
1454 struct gfar_private
*priv
= netdev_priv(dev
);
1455 struct sk_buff
*skb
= NULL
;
1457 /* We have to allocate the skb, so keep trying till we succeed */
1458 skb
= netdev_alloc_skb(dev
, priv
->rx_buffer_size
+ RXBUF_ALIGNMENT
);
1463 alignamount
= RXBUF_ALIGNMENT
-
1464 (((unsigned long) skb
->data
) & (RXBUF_ALIGNMENT
- 1));
1466 /* We need the data buffer to be aligned properly. We will reserve
1467 * as many bytes as needed to align the data properly
1469 skb_reserve(skb
, alignamount
);
1474 static inline void count_errors(unsigned short status
, struct net_device
*dev
)
1476 struct gfar_private
*priv
= netdev_priv(dev
);
1477 struct net_device_stats
*stats
= &dev
->stats
;
1478 struct gfar_extra_stats
*estats
= &priv
->extra_stats
;
1480 /* If the packet was truncated, none of the other errors
1482 if (status
& RXBD_TRUNCATED
) {
1483 stats
->rx_length_errors
++;
1489 /* Count the errors, if there were any */
1490 if (status
& (RXBD_LARGE
| RXBD_SHORT
)) {
1491 stats
->rx_length_errors
++;
1493 if (status
& RXBD_LARGE
)
1498 if (status
& RXBD_NONOCTET
) {
1499 stats
->rx_frame_errors
++;
1500 estats
->rx_nonoctet
++;
1502 if (status
& RXBD_CRCERR
) {
1503 estats
->rx_crcerr
++;
1504 stats
->rx_crc_errors
++;
1506 if (status
& RXBD_OVERRUN
) {
1507 estats
->rx_overrun
++;
1508 stats
->rx_crc_errors
++;
1512 irqreturn_t
gfar_receive(int irq
, void *dev_id
)
1514 struct net_device
*dev
= (struct net_device
*) dev_id
;
1515 struct gfar_private
*priv
= netdev_priv(dev
);
1519 /* Clear IEVENT, so interrupts aren't called again
1520 * because of the packets that have already arrived */
1521 gfar_write(&priv
->regs
->ievent
, IEVENT_RTX_MASK
);
1523 if (netif_rx_schedule_prep(dev
, &priv
->napi
)) {
1524 tempval
= gfar_read(&priv
->regs
->imask
);
1525 tempval
&= IMASK_RTX_DISABLED
;
1526 gfar_write(&priv
->regs
->imask
, tempval
);
1528 __netif_rx_schedule(dev
, &priv
->napi
);
1530 if (netif_msg_rx_err(priv
))
1531 printk(KERN_DEBUG
"%s: receive called twice (%x)[%x]\n",
1532 dev
->name
, gfar_read(&priv
->regs
->ievent
),
1533 gfar_read(&priv
->regs
->imask
));
1539 static inline void gfar_rx_checksum(struct sk_buff
*skb
, struct rxfcb
*fcb
)
1541 /* If valid headers were found, and valid sums
1542 * were verified, then we tell the kernel that no
1543 * checksumming is necessary. Otherwise, it is */
1544 if ((fcb
->flags
& RXFCB_CSUM_MASK
) == (RXFCB_CIP
| RXFCB_CTU
))
1545 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1547 skb
->ip_summed
= CHECKSUM_NONE
;
1551 static inline struct rxfcb
*gfar_get_fcb(struct sk_buff
*skb
)
1553 struct rxfcb
*fcb
= (struct rxfcb
*)skb
->data
;
1555 /* Remove the FCB from the skb */
1556 skb_pull(skb
, GMAC_FCB_LEN
);
1561 /* gfar_process_frame() -- handle one incoming packet if skb
1563 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
1566 struct gfar_private
*priv
= netdev_priv(dev
);
1567 struct rxfcb
*fcb
= NULL
;
1570 if (netif_msg_rx_err(priv
))
1571 printk(KERN_WARNING
"%s: Missing skb!!.\n", dev
->name
);
1572 dev
->stats
.rx_dropped
++;
1573 priv
->extra_stats
.rx_skbmissing
++;
1577 /* Prep the skb for the packet */
1578 skb_put(skb
, length
);
1580 /* Grab the FCB if there is one */
1581 if (gfar_uses_fcb(priv
))
1582 fcb
= gfar_get_fcb(skb
);
1584 /* Remove the padded bytes, if there are any */
1586 skb_pull(skb
, priv
->padding
);
1588 if (priv
->rx_csum_enable
)
1589 gfar_rx_checksum(skb
, fcb
);
1591 /* Tell the skb what kind of packet this is */
1592 skb
->protocol
= eth_type_trans(skb
, dev
);
1594 /* Send the packet up the stack */
1595 if (unlikely(priv
->vlgrp
&& (fcb
->flags
& RXFCB_VLN
))) {
1596 ret
= vlan_hwaccel_receive_skb(skb
, priv
->vlgrp
,
1599 ret
= netif_receive_skb(skb
);
1601 if (NET_RX_DROP
== ret
)
1602 priv
->extra_stats
.kernel_dropped
++;
1608 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1609 * until the budget/quota has been reached. Returns the number
1612 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
)
1615 struct sk_buff
*skb
;
1618 struct gfar_private
*priv
= netdev_priv(dev
);
1620 /* Get the first full descriptor */
1623 while (!((bdp
->status
& RXBD_EMPTY
) || (--rx_work_limit
< 0))) {
1624 struct sk_buff
*newskb
;
1627 /* Add another skb for the future */
1628 newskb
= gfar_new_skb(dev
);
1630 skb
= priv
->rx_skbuff
[priv
->skb_currx
];
1632 /* We drop the frame if we failed to allocate a new buffer */
1633 if (unlikely(!newskb
|| !(bdp
->status
& RXBD_LAST
) ||
1634 bdp
->status
& RXBD_ERR
)) {
1635 count_errors(bdp
->status
, dev
);
1637 if (unlikely(!newskb
))
1641 dma_unmap_single(&priv
->dev
->dev
,
1643 priv
->rx_buffer_size
,
1646 dev_kfree_skb_any(skb
);
1649 /* Increment the number of packets */
1650 dev
->stats
.rx_packets
++;
1653 /* Remove the FCS from the packet length */
1654 pkt_len
= bdp
->length
- 4;
1656 gfar_process_frame(dev
, skb
, pkt_len
);
1658 dev
->stats
.rx_bytes
+= pkt_len
;
1661 dev
->last_rx
= jiffies
;
1663 priv
->rx_skbuff
[priv
->skb_currx
] = newskb
;
1665 /* Setup the new bdp */
1666 gfar_new_rxbdp(dev
, bdp
, newskb
);
1668 /* Update to the next pointer */
1669 if (bdp
->status
& RXBD_WRAP
)
1670 bdp
= priv
->rx_bd_base
;
1674 /* update to point at the next skb */
1676 (priv
->skb_currx
+ 1) &
1677 RX_RING_MOD_MASK(priv
->rx_ring_size
);
1680 /* Update the current rxbd pointer to be the next one */
1686 static int gfar_poll(struct napi_struct
*napi
, int budget
)
1688 struct gfar_private
*priv
= container_of(napi
, struct gfar_private
, napi
);
1689 struct net_device
*dev
= priv
->dev
;
1691 unsigned long flags
;
1693 /* If we fail to get the lock, don't bother with the TX BDs */
1694 if (spin_trylock_irqsave(&priv
->txlock
, flags
)) {
1695 gfar_clean_tx_ring(dev
);
1696 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1699 howmany
= gfar_clean_rx_ring(dev
, budget
);
1701 if (howmany
< budget
) {
1702 netif_rx_complete(dev
, napi
);
1704 /* Clear the halt bit in RSTAT */
1705 gfar_write(&priv
->regs
->rstat
, RSTAT_CLEAR_RHALT
);
1707 gfar_write(&priv
->regs
->imask
, IMASK_DEFAULT
);
1709 /* If we are coalescing interrupts, update the timer */
1710 /* Otherwise, clear it */
1711 if (likely(priv
->rxcoalescing
)) {
1712 gfar_write(&priv
->regs
->rxic
, 0);
1713 gfar_write(&priv
->regs
->rxic
,
1714 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
1721 #ifdef CONFIG_NET_POLL_CONTROLLER
1723 * Polling 'interrupt' - used by things like netconsole to send skbs
1724 * without having to re-enable interrupts. It's not called while
1725 * the interrupt routine is executing.
1727 static void gfar_netpoll(struct net_device
*dev
)
1729 struct gfar_private
*priv
= netdev_priv(dev
);
1731 /* If the device has multiple interrupts, run tx/rx */
1732 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1733 disable_irq(priv
->interruptTransmit
);
1734 disable_irq(priv
->interruptReceive
);
1735 disable_irq(priv
->interruptError
);
1736 gfar_interrupt(priv
->interruptTransmit
, dev
);
1737 enable_irq(priv
->interruptError
);
1738 enable_irq(priv
->interruptReceive
);
1739 enable_irq(priv
->interruptTransmit
);
1741 disable_irq(priv
->interruptTransmit
);
1742 gfar_interrupt(priv
->interruptTransmit
, dev
);
1743 enable_irq(priv
->interruptTransmit
);
1748 /* The interrupt handler for devices with one interrupt */
1749 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
)
1751 struct net_device
*dev
= dev_id
;
1752 struct gfar_private
*priv
= netdev_priv(dev
);
1754 /* Save ievent for future reference */
1755 u32 events
= gfar_read(&priv
->regs
->ievent
);
1757 /* Check for reception */
1758 if (events
& IEVENT_RX_MASK
)
1759 gfar_receive(irq
, dev_id
);
1761 /* Check for transmit completion */
1762 if (events
& IEVENT_TX_MASK
)
1763 gfar_transmit(irq
, dev_id
);
1765 /* Check for errors */
1766 if (events
& IEVENT_ERR_MASK
)
1767 gfar_error(irq
, dev_id
);
1772 /* Called every time the controller might need to be made
1773 * aware of new link state. The PHY code conveys this
1774 * information through variables in the phydev structure, and this
1775 * function converts those variables into the appropriate
1776 * register values, and can bring down the device if needed.
1778 static void adjust_link(struct net_device
*dev
)
1780 struct gfar_private
*priv
= netdev_priv(dev
);
1781 struct gfar __iomem
*regs
= priv
->regs
;
1782 unsigned long flags
;
1783 struct phy_device
*phydev
= priv
->phydev
;
1786 spin_lock_irqsave(&priv
->txlock
, flags
);
1788 u32 tempval
= gfar_read(®s
->maccfg2
);
1789 u32 ecntrl
= gfar_read(®s
->ecntrl
);
1791 /* Now we make sure that we can be in full duplex mode.
1792 * If not, we operate in half-duplex mode. */
1793 if (phydev
->duplex
!= priv
->oldduplex
) {
1795 if (!(phydev
->duplex
))
1796 tempval
&= ~(MACCFG2_FULL_DUPLEX
);
1798 tempval
|= MACCFG2_FULL_DUPLEX
;
1800 priv
->oldduplex
= phydev
->duplex
;
1803 if (phydev
->speed
!= priv
->oldspeed
) {
1805 switch (phydev
->speed
) {
1808 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_GMII
);
1813 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_MII
);
1815 /* Reduced mode distinguishes
1816 * between 10 and 100 */
1817 if (phydev
->speed
== SPEED_100
)
1818 ecntrl
|= ECNTRL_R100
;
1820 ecntrl
&= ~(ECNTRL_R100
);
1823 if (netif_msg_link(priv
))
1825 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
1826 dev
->name
, phydev
->speed
);
1830 priv
->oldspeed
= phydev
->speed
;
1833 gfar_write(®s
->maccfg2
, tempval
);
1834 gfar_write(®s
->ecntrl
, ecntrl
);
1836 if (!priv
->oldlink
) {
1840 } else if (priv
->oldlink
) {
1844 priv
->oldduplex
= -1;
1847 if (new_state
&& netif_msg_link(priv
))
1848 phy_print_status(phydev
);
1850 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1853 /* Update the hash table based on the current list of multicast
1854 * addresses we subscribe to. Also, change the promiscuity of
1855 * the device based on the flags (this function is called
1856 * whenever dev->flags is changed */
1857 static void gfar_set_multi(struct net_device
*dev
)
1859 struct dev_mc_list
*mc_ptr
;
1860 struct gfar_private
*priv
= netdev_priv(dev
);
1861 struct gfar __iomem
*regs
= priv
->regs
;
1864 if(dev
->flags
& IFF_PROMISC
) {
1865 /* Set RCTRL to PROM */
1866 tempval
= gfar_read(®s
->rctrl
);
1867 tempval
|= RCTRL_PROM
;
1868 gfar_write(®s
->rctrl
, tempval
);
1870 /* Set RCTRL to not PROM */
1871 tempval
= gfar_read(®s
->rctrl
);
1872 tempval
&= ~(RCTRL_PROM
);
1873 gfar_write(®s
->rctrl
, tempval
);
1876 if(dev
->flags
& IFF_ALLMULTI
) {
1877 /* Set the hash to rx all multicast frames */
1878 gfar_write(®s
->igaddr0
, 0xffffffff);
1879 gfar_write(®s
->igaddr1
, 0xffffffff);
1880 gfar_write(®s
->igaddr2
, 0xffffffff);
1881 gfar_write(®s
->igaddr3
, 0xffffffff);
1882 gfar_write(®s
->igaddr4
, 0xffffffff);
1883 gfar_write(®s
->igaddr5
, 0xffffffff);
1884 gfar_write(®s
->igaddr6
, 0xffffffff);
1885 gfar_write(®s
->igaddr7
, 0xffffffff);
1886 gfar_write(®s
->gaddr0
, 0xffffffff);
1887 gfar_write(®s
->gaddr1
, 0xffffffff);
1888 gfar_write(®s
->gaddr2
, 0xffffffff);
1889 gfar_write(®s
->gaddr3
, 0xffffffff);
1890 gfar_write(®s
->gaddr4
, 0xffffffff);
1891 gfar_write(®s
->gaddr5
, 0xffffffff);
1892 gfar_write(®s
->gaddr6
, 0xffffffff);
1893 gfar_write(®s
->gaddr7
, 0xffffffff);
1898 /* zero out the hash */
1899 gfar_write(®s
->igaddr0
, 0x0);
1900 gfar_write(®s
->igaddr1
, 0x0);
1901 gfar_write(®s
->igaddr2
, 0x0);
1902 gfar_write(®s
->igaddr3
, 0x0);
1903 gfar_write(®s
->igaddr4
, 0x0);
1904 gfar_write(®s
->igaddr5
, 0x0);
1905 gfar_write(®s
->igaddr6
, 0x0);
1906 gfar_write(®s
->igaddr7
, 0x0);
1907 gfar_write(®s
->gaddr0
, 0x0);
1908 gfar_write(®s
->gaddr1
, 0x0);
1909 gfar_write(®s
->gaddr2
, 0x0);
1910 gfar_write(®s
->gaddr3
, 0x0);
1911 gfar_write(®s
->gaddr4
, 0x0);
1912 gfar_write(®s
->gaddr5
, 0x0);
1913 gfar_write(®s
->gaddr6
, 0x0);
1914 gfar_write(®s
->gaddr7
, 0x0);
1916 /* If we have extended hash tables, we need to
1917 * clear the exact match registers to prepare for
1919 if (priv
->extended_hash
) {
1920 em_num
= GFAR_EM_NUM
+ 1;
1921 gfar_clear_exact_match(dev
);
1928 if(dev
->mc_count
== 0)
1931 /* Parse the list, and set the appropriate bits */
1932 for(mc_ptr
= dev
->mc_list
; mc_ptr
; mc_ptr
= mc_ptr
->next
) {
1934 gfar_set_mac_for_addr(dev
, idx
,
1938 gfar_set_hash_for_addr(dev
, mc_ptr
->dmi_addr
);
1946 /* Clears each of the exact match registers to zero, so they
1947 * don't interfere with normal reception */
1948 static void gfar_clear_exact_match(struct net_device
*dev
)
1951 u8 zero_arr
[MAC_ADDR_LEN
] = {0,0,0,0,0,0};
1953 for(idx
= 1;idx
< GFAR_EM_NUM
+ 1;idx
++)
1954 gfar_set_mac_for_addr(dev
, idx
, (u8
*)zero_arr
);
1957 /* Set the appropriate hash bit for the given addr */
1958 /* The algorithm works like so:
1959 * 1) Take the Destination Address (ie the multicast address), and
1960 * do a CRC on it (little endian), and reverse the bits of the
1962 * 2) Use the 8 most significant bits as a hash into a 256-entry
1963 * table. The table is controlled through 8 32-bit registers:
1964 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1965 * gaddr7. This means that the 3 most significant bits in the
1966 * hash index which gaddr register to use, and the 5 other bits
1967 * indicate which bit (assuming an IBM numbering scheme, which
1968 * for PowerPC (tm) is usually the case) in the register holds
1970 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
)
1973 struct gfar_private
*priv
= netdev_priv(dev
);
1974 u32 result
= ether_crc(MAC_ADDR_LEN
, addr
);
1975 int width
= priv
->hash_width
;
1976 u8 whichbit
= (result
>> (32 - width
)) & 0x1f;
1977 u8 whichreg
= result
>> (32 - width
+ 5);
1978 u32 value
= (1 << (31-whichbit
));
1980 tempval
= gfar_read(priv
->hash_regs
[whichreg
]);
1982 gfar_write(priv
->hash_regs
[whichreg
], tempval
);
1988 /* There are multiple MAC Address register pairs on some controllers
1989 * This function sets the numth pair to a given address
1991 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
)
1993 struct gfar_private
*priv
= netdev_priv(dev
);
1995 char tmpbuf
[MAC_ADDR_LEN
];
1997 u32 __iomem
*macptr
= &priv
->regs
->macstnaddr1
;
2001 /* Now copy it into the mac registers backwards, cuz */
2002 /* little endian is silly */
2003 for (idx
= 0; idx
< MAC_ADDR_LEN
; idx
++)
2004 tmpbuf
[MAC_ADDR_LEN
- 1 - idx
] = addr
[idx
];
2006 gfar_write(macptr
, *((u32
*) (tmpbuf
)));
2008 tempval
= *((u32
*) (tmpbuf
+ 4));
2010 gfar_write(macptr
+1, tempval
);
2013 /* GFAR error interrupt handler */
2014 static irqreturn_t
gfar_error(int irq
, void *dev_id
)
2016 struct net_device
*dev
= dev_id
;
2017 struct gfar_private
*priv
= netdev_priv(dev
);
2019 /* Save ievent for future reference */
2020 u32 events
= gfar_read(&priv
->regs
->ievent
);
2023 gfar_write(&priv
->regs
->ievent
, events
& IEVENT_ERR_MASK
);
2025 /* Magic Packet is not an error. */
2026 if ((priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
) &&
2027 (events
& IEVENT_MAG
))
2028 events
&= ~IEVENT_MAG
;
2031 if (netif_msg_rx_err(priv
) || netif_msg_tx_err(priv
))
2032 printk(KERN_DEBUG
"%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2033 dev
->name
, events
, gfar_read(&priv
->regs
->imask
));
2035 /* Update the error counters */
2036 if (events
& IEVENT_TXE
) {
2037 dev
->stats
.tx_errors
++;
2039 if (events
& IEVENT_LC
)
2040 dev
->stats
.tx_window_errors
++;
2041 if (events
& IEVENT_CRL
)
2042 dev
->stats
.tx_aborted_errors
++;
2043 if (events
& IEVENT_XFUN
) {
2044 if (netif_msg_tx_err(priv
))
2045 printk(KERN_DEBUG
"%s: TX FIFO underrun, "
2046 "packet dropped.\n", dev
->name
);
2047 dev
->stats
.tx_dropped
++;
2048 priv
->extra_stats
.tx_underrun
++;
2050 /* Reactivate the Tx Queues */
2051 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
2053 if (netif_msg_tx_err(priv
))
2054 printk(KERN_DEBUG
"%s: Transmit Error\n", dev
->name
);
2056 if (events
& IEVENT_BSY
) {
2057 dev
->stats
.rx_errors
++;
2058 priv
->extra_stats
.rx_bsy
++;
2060 gfar_receive(irq
, dev_id
);
2062 if (netif_msg_rx_err(priv
))
2063 printk(KERN_DEBUG
"%s: busy error (rstat: %x)\n",
2064 dev
->name
, gfar_read(&priv
->regs
->rstat
));
2066 if (events
& IEVENT_BABR
) {
2067 dev
->stats
.rx_errors
++;
2068 priv
->extra_stats
.rx_babr
++;
2070 if (netif_msg_rx_err(priv
))
2071 printk(KERN_DEBUG
"%s: babbling RX error\n", dev
->name
);
2073 if (events
& IEVENT_EBERR
) {
2074 priv
->extra_stats
.eberr
++;
2075 if (netif_msg_rx_err(priv
))
2076 printk(KERN_DEBUG
"%s: bus error\n", dev
->name
);
2078 if ((events
& IEVENT_RXC
) && netif_msg_rx_status(priv
))
2079 printk(KERN_DEBUG
"%s: control frame\n", dev
->name
);
2081 if (events
& IEVENT_BABT
) {
2082 priv
->extra_stats
.tx_babt
++;
2083 if (netif_msg_tx_err(priv
))
2084 printk(KERN_DEBUG
"%s: babbling TX error\n", dev
->name
);
2089 /* work with hotplug and coldplug */
2090 MODULE_ALIAS("platform:fsl-gianfar");
2092 /* Structure for a device driver */
2093 static struct platform_driver gfar_driver
= {
2094 .probe
= gfar_probe
,
2095 .remove
= gfar_remove
,
2096 .suspend
= gfar_suspend
,
2097 .resume
= gfar_resume
,
2099 .name
= "fsl-gianfar",
2100 .owner
= THIS_MODULE
,
2104 static int __init
gfar_init(void)
2106 int err
= gfar_mdio_init();
2111 err
= platform_driver_register(&gfar_driver
);
2119 static void __exit
gfar_exit(void)
2121 platform_driver_unregister(&gfar_driver
);
2125 module_init(gfar_init
);
2126 module_exit(gfar_exit
);