drivers/atm/nicstar.h

   1 /*
   2  * nicstar.h
   3  *
   4  * Header file for the nicstar device driver.
   5  *
   6  * Author: Rui Prior (rprior@inescn.pt)
   7  * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
   8  *
   9  * (C) INESC 1998
  10  */
  11
  12 #ifndef _LINUX_NICSTAR_H_
  13 #define _LINUX_NICSTAR_H_
  14
  15 /* Includes */
  16
  17 #include <linux/types.h>
  18 #include <linux/pci.h>
  19 #include <linux/idr.h>
  20 #include <linux/uio.h>
  21 #include <linux/skbuff.h>
  22 #include <linux/atmdev.h>
  23 #include <linux/atm_nicstar.h>
  24
  25 /* Options */
  26
  27 #define NS_MAX_CARDS 4          /* Maximum number of NICStAR based cards
  28                                    controlled by the device driver. Must
  29                                    be <= 5 */
  30
  31 #undef RCQ_SUPPORT              /* Do not define this for now */
  32
  33 #define NS_TST_NUM_ENTRIES 2340 /* + 1 for return */
  34 #define NS_TST_RESERVED 340     /* N. entries reserved for UBR/ABR/VBR */
  35
  36 #define NS_SMBUFSIZE 48         /* 48, 96, 240 or 2048 */
  37 #define NS_LGBUFSIZE 16384      /* 2048, 4096, 8192 or 16384 */
  38 #define NS_RSQSIZE 8192         /* 2048, 4096 or 8192 */
  39 #define NS_VPIBITS 2            /* 0, 1, 2, or 8 */
  40
  41 #define NS_MAX_RCTSIZE 4096     /* Number of entries. 4096 or 16384.
  42                                    Define 4096 only if (all) your card(s)
  43                                    have 32K x 32bit SRAM, in which case
  44                                    setting this to 16384 will just waste a
  45                                    lot of memory.
  46                                    Setting this to 4096 for a card with
  47                                    128K x 32bit SRAM will limit the maximum
  48                                    VCI. */
  49
  50                                 /*#define NS_PCI_LATENCY 64*//* Must be a multiple of 32 */
  51
  52         /* Number of buffers initially allocated */
  53 #define NUM_SB 32               /* Must be even */
  54 #define NUM_LB 24               /* Must be even */
  55 #define NUM_HB 8                /* Pre-allocated huge buffers */
  56 #define NUM_IOVB 48             /* Iovec buffers */
  57
  58         /* Lower level for count of buffers */
  59 #define MIN_SB 8                /* Must be even */
  60 #define MIN_LB 8                /* Must be even */
  61 #define MIN_HB 6
  62 #define MIN_IOVB 8
  63
  64         /* Upper level for count of buffers */
  65 #define MAX_SB 64               /* Must be even, <= 508 */
  66 #define MAX_LB 48               /* Must be even, <= 508 */
  67 #define MAX_HB 10
  68 #define MAX_IOVB 80
  69
  70         /* These are the absolute maximum allowed for the ioctl() */
  71 #define TOP_SB 256              /* Must be even, <= 508 */
  72 #define TOP_LB 128              /* Must be even, <= 508 */
  73 #define TOP_HB 64
  74 #define TOP_IOVB 256
  75
  76 #define MAX_TBD_PER_VC 1        /* Number of TBDs before a TSR */
  77 #define MAX_TBD_PER_SCQ 10      /* Only meaningful for variable rate SCQs */
  78
  79 #undef ENABLE_TSQFIE
  80
  81 #define SCQFULL_TIMEOUT (5 * HZ)
  82
  83 #define NS_POLL_PERIOD (HZ)
  84
  85 #define PCR_TOLERANCE (1.0001)
  86
  87 /* ESI stuff */
  88
  89 #define NICSTAR_EPROM_MAC_ADDR_OFFSET 0x6C
  90 #define NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT 0xF6
  91
  92 /* #defines */
  93
  94 #define NS_IOREMAP_SIZE 4096
  95
  96 /*
  97  * BUF_XX distinguish the Rx buffers depending on their (small/large) size.
  98  * BUG_SM and BUG_LG are both used by the driver and the device.
  99  * BUF_NONE is only used by the driver.
 100  */
 101 #define BUF_SM          0x00000000      /* These two are used for push_rxbufs() */
 102 #define BUF_LG          0x00000001      /* CMD, Write_FreeBufQ, LBUF bit */
 103 #define BUF_NONE        0xffffffff      /* Software only: */
 104
 105 #define NS_HBUFSIZE 65568       /* Size of max. AAL5 PDU */
 106 #define NS_MAX_IOVECS (2 + (65568 - NS_SMBUFSIZE) / \
 107                        (NS_LGBUFSIZE - (NS_LGBUFSIZE % 48)))
 108 #define NS_IOVBUFSIZE (NS_MAX_IOVECS * (sizeof(struct iovec)))
 109
 110 #define NS_SMBUFSIZE_USABLE (NS_SMBUFSIZE - NS_SMBUFSIZE % 48)
 111 #define NS_LGBUFSIZE_USABLE (NS_LGBUFSIZE - NS_LGBUFSIZE % 48)
 112
 113 #define NS_AAL0_HEADER (ATM_AAL0_SDU - ATM_CELL_PAYLOAD)        /* 4 bytes */
 114
 115 #define NS_SMSKBSIZE (NS_SMBUFSIZE + NS_AAL0_HEADER)
 116 #define NS_LGSKBSIZE (NS_SMBUFSIZE + NS_LGBUFSIZE)
 117
 118 /* NICStAR structures located in host memory */
 119
 120 /*
 121  * RSQ - Receive Status Queue
 122  *
 123  * Written by the NICStAR, read by the device driver.
 124  */
 125
 126 typedef struct ns_rsqe {
 127         u32 word_1;
 128         u32 buffer_handle;
 129         u32 final_aal5_crc32;
 130         u32 word_4;
 131 } ns_rsqe;
 132
 133 #define ns_rsqe_vpi(ns_rsqep) \
 134         ((le32_to_cpu((ns_rsqep)->word_1) & 0x00FF0000) >> 16)
 135 #define ns_rsqe_vci(ns_rsqep) \
 136         (le32_to_cpu((ns_rsqep)->word_1) & 0x0000FFFF)
 137
 138 #define NS_RSQE_VALID      0x80000000
 139 #define NS_RSQE_NZGFC      0x00004000
 140 #define NS_RSQE_EOPDU      0x00002000
 141 #define NS_RSQE_BUFSIZE    0x00001000
 142 #define NS_RSQE_CONGESTION 0x00000800
 143 #define NS_RSQE_CLP        0x00000400
 144 #define NS_RSQE_CRCERR     0x00000200
 145
 146 #define NS_RSQE_BUFSIZE_SM 0x00000000
 147 #define NS_RSQE_BUFSIZE_LG 0x00001000
 148
 149 #define ns_rsqe_valid(ns_rsqep) \
 150         (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_VALID)
 151 #define ns_rsqe_nzgfc(ns_rsqep) \
 152         (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_NZGFC)
 153 #define ns_rsqe_eopdu(ns_rsqep) \
 154         (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_EOPDU)
 155 #define ns_rsqe_bufsize(ns_rsqep) \
 156         (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_BUFSIZE)
 157 #define ns_rsqe_congestion(ns_rsqep) \
 158         (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CONGESTION)
 159 #define ns_rsqe_clp(ns_rsqep) \
 160         (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CLP)
 161 #define ns_rsqe_crcerr(ns_rsqep) \
 162         (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CRCERR)
 163
 164 #define ns_rsqe_cellcount(ns_rsqep) \
 165         (le32_to_cpu((ns_rsqep)->word_4) & 0x000001FF)
 166 #define ns_rsqe_init(ns_rsqep) \
 167         ((ns_rsqep)->word_4 = cpu_to_le32(0x00000000))
 168
 169 #define NS_RSQ_NUM_ENTRIES (NS_RSQSIZE / 16)
 170 #define NS_RSQ_ALIGNMENT NS_RSQSIZE
 171
 172 /*
 173  * RCQ - Raw Cell Queue
 174  *
 175  * Written by the NICStAR, read by the device driver.
 176  */
 177
 178 typedef struct cell_payload {
 179         u32 word[12];
 180 } cell_payload;
 181
 182 typedef struct ns_rcqe {
 183         u32 word_1;
 184         u32 word_2;
 185         u32 word_3;
 186         u32 word_4;
 187         cell_payload payload;
 188 } ns_rcqe;
 189
 190 #define NS_RCQE_SIZE 64         /* bytes */
 191
 192 #define ns_rcqe_islast(ns_rcqep) \
 193         (le32_to_cpu((ns_rcqep)->word_2) != 0x00000000)
 194 #define ns_rcqe_cellheader(ns_rcqep) \
 195         (le32_to_cpu((ns_rcqep)->word_1))
 196 #define ns_rcqe_nextbufhandle(ns_rcqep) \
 197         (le32_to_cpu((ns_rcqep)->word_2))
 198
 199 /*
 200  * SCQ - Segmentation Channel Queue
 201  *
 202  * Written by the device driver, read by the NICStAR.
 203  */
 204
 205 typedef struct ns_scqe {
 206         u32 word_1;
 207         u32 word_2;
 208         u32 word_3;
 209         u32 word_4;
 210 } ns_scqe;
 211
 212    /* NOTE: SCQ entries can be either a TBD (Transmit Buffer Descriptors)
 213       or TSR (Transmit Status Requests) */
 214
 215 #define NS_SCQE_TYPE_TBD 0x00000000
 216 #define NS_SCQE_TYPE_TSR 0x80000000
 217
 218 #define NS_TBD_EOPDU 0x40000000
 219 #define NS_TBD_AAL0  0x00000000
 220 #define NS_TBD_AAL34 0x04000000
 221 #define NS_TBD_AAL5  0x08000000
 222
 223 #define NS_TBD_VPI_MASK 0x0FF00000
 224 #define NS_TBD_VCI_MASK 0x000FFFF0
 225 #define NS_TBD_VC_MASK (NS_TBD_VPI_MASK | NS_TBD_VCI_MASK)
 226
 227 #define NS_TBD_VPI_SHIFT 20
 228 #define NS_TBD_VCI_SHIFT 4
 229
 230 #define ns_tbd_mkword_1(flags, m, n, buflen) \
 231       (cpu_to_le32((flags) | (m) << 23 | (n) << 16 | (buflen)))
 232 #define ns_tbd_mkword_1_novbr(flags, buflen) \
 233       (cpu_to_le32((flags) | (buflen) | 0x00810000))
 234 #define ns_tbd_mkword_3(control, pdulen) \
 235       (cpu_to_le32((control) << 16 | (pdulen)))
 236 #define ns_tbd_mkword_4(gfc, vpi, vci, pt, clp) \
 237       (cpu_to_le32((gfc) << 28 | (vpi) << 20 | (vci) << 4 | (pt) << 1 | (clp)))
 238
 239 #define NS_TSR_INTENABLE 0x20000000
 240
 241 #define NS_TSR_SCDISVBR 0xFFFF  /* Use as scdi for VBR SCD */
 242
 243 #define ns_tsr_mkword_1(flags) \
 244         (cpu_to_le32(NS_SCQE_TYPE_TSR | (flags)))
 245 #define ns_tsr_mkword_2(scdi, scqi) \
 246         (cpu_to_le32((scdi) << 16 | 0x00008000 | (scqi)))
 247
 248 #define ns_scqe_is_tsr(ns_scqep) \
 249         (le32_to_cpu((ns_scqep)->word_1) & NS_SCQE_TYPE_TSR)
 250
 251 #define VBR_SCQ_NUM_ENTRIES 512
 252 #define VBR_SCQSIZE 8192
 253 #define CBR_SCQ_NUM_ENTRIES 64
 254 #define CBR_SCQSIZE 1024
 255
 256 #define NS_SCQE_SIZE 16
 257
 258 /*
 259  * TSQ - Transmit Status Queue
 260  *
 261  * Written by the NICStAR, read by the device driver.
 262  */
 263
 264 typedef struct ns_tsi {
 265         u32 word_1;
 266         u32 word_2;
 267 } ns_tsi;
 268
 269    /* NOTE: The first word can be a status word copied from the TSR which
 270       originated the TSI, or a timer overflow indicator. In this last
 271       case, the value of the first word is all zeroes. */
 272
 273 #define NS_TSI_EMPTY          0x80000000
 274 #define NS_TSI_TIMESTAMP_MASK 0x00FFFFFF
 275
 276 #define ns_tsi_isempty(ns_tsip) \
 277         (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_EMPTY)
 278 #define ns_tsi_gettimestamp(ns_tsip) \
 279         (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_TIMESTAMP_MASK)
 280
 281 #define ns_tsi_init(ns_tsip) \
 282         ((ns_tsip)->word_2 = cpu_to_le32(NS_TSI_EMPTY))
 283
 284 #define NS_TSQSIZE 8192
 285 #define NS_TSQ_NUM_ENTRIES 1024
 286 #define NS_TSQ_ALIGNMENT 8192
 287
 288 #define NS_TSI_SCDISVBR NS_TSR_SCDISVBR
 289
 290 #define ns_tsi_tmrof(ns_tsip) \
 291         (le32_to_cpu((ns_tsip)->word_1) == 0x00000000)
 292 #define ns_tsi_getscdindex(ns_tsip) \
 293         ((le32_to_cpu((ns_tsip)->word_1) & 0xFFFF0000) >> 16)
 294 #define ns_tsi_getscqpos(ns_tsip) \
 295         (le32_to_cpu((ns_tsip)->word_1) & 0x00007FFF)
 296
 297 /* NICStAR structures located in local SRAM */
 298
 299 /*
 300  * RCT - Receive Connection Table
 301  *
 302  * Written by both the NICStAR and the device driver.
 303  */
 304
 305 typedef struct ns_rcte {
 306         u32 word_1;
 307         u32 buffer_handle;
 308         u32 dma_address;
 309         u32 aal5_crc32;
 310 } ns_rcte;
 311
 312 #define NS_RCTE_BSFB            0x00200000      /* Rev. D only */
 313 #define NS_RCTE_NZGFC           0x00100000
 314 #define NS_RCTE_CONNECTOPEN     0x00080000
 315 #define NS_RCTE_AALMASK         0x00070000
 316 #define NS_RCTE_AAL0            0x00000000
 317 #define NS_RCTE_AAL34           0x00010000
 318 #define NS_RCTE_AAL5            0x00020000
 319 #define NS_RCTE_RCQ             0x00030000
 320 #define NS_RCTE_RAWCELLINTEN    0x00008000
 321 #define NS_RCTE_RXCONSTCELLADDR 0x00004000
 322 #define NS_RCTE_BUFFVALID       0x00002000
 323 #define NS_RCTE_FBDSIZE         0x00001000
 324 #define NS_RCTE_EFCI            0x00000800
 325 #define NS_RCTE_CLP             0x00000400
 326 #define NS_RCTE_CRCERROR        0x00000200
 327 #define NS_RCTE_CELLCOUNT_MASK  0x000001FF
 328
 329 #define NS_RCTE_FBDSIZE_SM 0x00000000
 330 #define NS_RCTE_FBDSIZE_LG 0x00001000
 331
 332 #define NS_RCT_ENTRY_SIZE 4     /* Number of dwords */
 333
 334    /* NOTE: We could make macros to contruct the first word of the RCTE,
 335       but that doesn't seem to make much sense... */
 336
 337 /*
 338  * FBD - Free Buffer Descriptor
 339  *
 340  * Written by the device driver using via the command register.
 341  */
 342
 343 typedef struct ns_fbd {
 344         u32 buffer_handle;
 345         u32 dma_address;
 346 } ns_fbd;
 347
 348 /*
 349  * TST - Transmit Schedule Table
 350  *
 351  * Written by the device driver.
 352  */
 353
 354 typedef u32 ns_tste;
 355
 356 #define NS_TST_OPCODE_MASK 0x60000000
 357
 358 #define NS_TST_OPCODE_NULL     0x00000000       /* Insert null cell */
 359 #define NS_TST_OPCODE_FIXED    0x20000000       /* Cell from a fixed rate channel */
 360 #define NS_TST_OPCODE_VARIABLE 0x40000000
 361 #define NS_TST_OPCODE_END      0x60000000       /* Jump */
 362
 363 #define ns_tste_make(opcode, sramad) (opcode | sramad)
 364
 365    /* NOTE:
 366
 367       - When the opcode is FIXED, sramad specifies the SRAM address of the
 368       SCD for that fixed rate channel.
 369       - When the opcode is END, sramad specifies the SRAM address of the
 370       location of the next TST entry to read.
 371     */
 372
 373 /*
 374  * SCD - Segmentation Channel Descriptor
 375  *
 376  * Written by both the device driver and the NICStAR
 377  */
 378
 379 typedef struct ns_scd {
 380         u32 word_1;
 381         u32 word_2;
 382         u32 partial_aal5_crc;
 383         u32 reserved;
 384         ns_scqe cache_a;
 385         ns_scqe cache_b;
 386 } ns_scd;
 387
 388 #define NS_SCD_BASE_MASK_VAR 0xFFFFE000 /* Variable rate */
 389 #define NS_SCD_BASE_MASK_FIX 0xFFFFFC00 /* Fixed rate */
 390 #define NS_SCD_TAIL_MASK_VAR 0x00001FF0
 391 #define NS_SCD_TAIL_MASK_FIX 0x000003F0
 392 #define NS_SCD_HEAD_MASK_VAR 0x00001FF0
 393 #define NS_SCD_HEAD_MASK_FIX 0x000003F0
 394 #define NS_SCD_XMITFOREVER   0x02000000
 395
 396    /* NOTE: There are other fields in word 2 of the SCD, but as they should
 397       not be needed in the device driver they are not defined here. */
 398
 399 /* NICStAR local SRAM memory map */
 400
 401 #define NS_RCT           0x00000
 402 #define NS_RCT_32_END    0x03FFF
 403 #define NS_RCT_128_END   0x0FFFF
 404 #define NS_UNUSED_32     0x04000
 405 #define NS_UNUSED_128    0x10000
 406 #define NS_UNUSED_END    0x1BFFF
 407 #define NS_TST_FRSCD     0x1C000
 408 #define NS_TST_FRSCD_END 0x1E7DB
 409 #define NS_VRSCD2        0x1E7DC
 410 #define NS_VRSCD2_END    0x1E7E7
 411 #define NS_VRSCD1        0x1E7E8
 412 #define NS_VRSCD1_END    0x1E7F3
 413 #define NS_VRSCD0        0x1E7F4
 414 #define NS_VRSCD0_END    0x1E7FF
 415 #define NS_RXFIFO        0x1E800
 416 #define NS_RXFIFO_END    0x1F7FF
 417 #define NS_SMFBQ         0x1F800
 418 #define NS_SMFBQ_END     0x1FBFF
 419 #define NS_LGFBQ         0x1FC00
 420 #define NS_LGFBQ_END     0x1FFFF
 421
 422 /* NISCtAR operation registers */
 423
 424 /* See Section 3.4 of `IDT77211 NICStAR User Manual' from www.idt.com */
 425
 426 enum ns_regs {
 427         DR0 = 0x00,             /* Data Register 0 R/W */
 428         DR1 = 0x04,             /* Data Register 1 W */
 429         DR2 = 0x08,             /* Data Register 2 W */
 430         DR3 = 0x0C,             /* Data Register 3 W */
 431         CMD = 0x10,             /* Command W */
 432         CFG = 0x14,             /* Configuration R/W */
 433         STAT = 0x18,            /* Status R/W */
 434         RSQB = 0x1C,            /* Receive Status Queue Base W */
 435         RSQT = 0x20,            /* Receive Status Queue Tail R */
 436         RSQH = 0x24,            /* Receive Status Queue Head W */
 437         CDC = 0x28,             /* Cell Drop Counter R/clear */
 438         VPEC = 0x2C,            /* VPI/VCI Lookup Error Count R/clear */
 439         ICC = 0x30,             /* Invalid Cell Count R/clear */
 440         RAWCT = 0x34,           /* Raw Cell Tail R */
 441         TMR = 0x38,             /* Timer R */
 442         TSTB = 0x3C,            /* Transmit Schedule Table Base R/W */
 443         TSQB = 0x40,            /* Transmit Status Queue Base W */
 444         TSQT = 0x44,            /* Transmit Status Queue Tail R */
 445         TSQH = 0x48,            /* Transmit Status Queue Head W */
 446         GP = 0x4C,              /* General Purpose R/W */
 447         VPM = 0x50              /* VPI/VCI Mask W */
 448 };
 449
 450 /* NICStAR commands issued to the CMD register */
 451
 452 /* Top 4 bits are command opcode, lower 28 are parameters. */
 453
 454 #define NS_CMD_NO_OPERATION         0x00000000
 455         /* params always 0 */
 456
 457 #define NS_CMD_OPENCLOSE_CONNECTION 0x20000000
 458         /* b19{1=open,0=close} b18-2{SRAM addr} */
 459
 460 #define NS_CMD_WRITE_SRAM           0x40000000
 461         /* b18-2{SRAM addr} b1-0{burst size} */
 462
 463 #define NS_CMD_READ_SRAM            0x50000000
 464         /* b18-2{SRAM addr} */
 465
 466 #define NS_CMD_WRITE_FREEBUFQ       0x60000000
 467         /* b0{large buf indicator} */
 468
 469 #define NS_CMD_READ_UTILITY         0x80000000
 470         /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */
 471
 472 #define NS_CMD_WRITE_UTILITY        0x90000000
 473         /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */
 474
 475 #define NS_CMD_OPEN_CONNECTION (NS_CMD_OPENCLOSE_CONNECTION | 0x00080000)
 476 #define NS_CMD_CLOSE_CONNECTION NS_CMD_OPENCLOSE_CONNECTION
 477
 478 /* NICStAR configuration bits */
 479
 480 #define NS_CFG_SWRST          0x80000000        /* Software Reset */
 481 #define NS_CFG_RXPATH         0x20000000        /* Receive Path Enable */
 482 #define NS_CFG_SMBUFSIZE_MASK 0x18000000        /* Small Receive Buffer Size */
 483 #define NS_CFG_LGBUFSIZE_MASK 0x06000000        /* Large Receive Buffer Size */
 484 #define NS_CFG_EFBIE          0x01000000        /* Empty Free Buffer Queue
 485                                                    Interrupt Enable */
 486 #define NS_CFG_RSQSIZE_MASK   0x00C00000        /* Receive Status Queue Size */
 487 #define NS_CFG_ICACCEPT       0x00200000        /* Invalid Cell Accept */
 488 #define NS_CFG_IGNOREGFC      0x00100000        /* Ignore General Flow Control */
 489 #define NS_CFG_VPIBITS_MASK   0x000C0000        /* VPI/VCI Bits Size Select */
 490 #define NS_CFG_RCTSIZE_MASK   0x00030000        /* Receive Connection Table Size */
 491 #define NS_CFG_VCERRACCEPT    0x00008000        /* VPI/VCI Error Cell Accept */
 492 #define NS_CFG_RXINT_MASK     0x00007000        /* End of Receive PDU Interrupt
 493                                                    Handling */
 494 #define NS_CFG_RAWIE          0x00000800        /* Raw Cell Qu' Interrupt Enable */
 495 #define NS_CFG_RSQAFIE        0x00000400        /* Receive Queue Almost Full
 496                                                    Interrupt Enable */
 497 #define NS_CFG_RXRM           0x00000200        /* Receive RM Cells */
 498 #define NS_CFG_TMRROIE        0x00000080        /* Timer Roll Over Interrupt
 499                                                    Enable */
 500 #define NS_CFG_TXEN           0x00000020        /* Transmit Operation Enable */
 501 #define NS_CFG_TXIE           0x00000010        /* Transmit Status Interrupt
 502                                                    Enable */
 503 #define NS_CFG_TXURIE         0x00000008        /* Transmit Under-run Interrupt
 504                                                    Enable */
 505 #define NS_CFG_UMODE          0x00000004        /* Utopia Mode (cell/byte) Select */
 506 #define NS_CFG_TSQFIE         0x00000002        /* Transmit Status Queue Full
 507                                                    Interrupt Enable */
 508 #define NS_CFG_PHYIE          0x00000001        /* PHY Interrupt Enable */
 509
 510 #define NS_CFG_SMBUFSIZE_48    0x00000000
 511 #define NS_CFG_SMBUFSIZE_96    0x08000000
 512 #define NS_CFG_SMBUFSIZE_240   0x10000000
 513 #define NS_CFG_SMBUFSIZE_2048  0x18000000
 514
 515 #define NS_CFG_LGBUFSIZE_2048  0x00000000
 516 #define NS_CFG_LGBUFSIZE_4096  0x02000000
 517 #define NS_CFG_LGBUFSIZE_8192  0x04000000
 518 #define NS_CFG_LGBUFSIZE_16384 0x06000000
 519
 520 #define NS_CFG_RSQSIZE_2048 0x00000000
 521 #define NS_CFG_RSQSIZE_4096 0x00400000
 522 #define NS_CFG_RSQSIZE_8192 0x00800000
 523
 524 #define NS_CFG_VPIBITS_0 0x00000000
 525 #define NS_CFG_VPIBITS_1 0x00040000
 526 #define NS_CFG_VPIBITS_2 0x00080000
 527 #define NS_CFG_VPIBITS_8 0x000C0000
 528
 529 #define NS_CFG_RCTSIZE_4096_ENTRIES  0x00000000
 530 #define NS_CFG_RCTSIZE_8192_ENTRIES  0x00010000
 531 #define NS_CFG_RCTSIZE_16384_ENTRIES 0x00020000
 532
 533 #define NS_CFG_RXINT_NOINT   0x00000000
 534 #define NS_CFG_RXINT_NODELAY 0x00001000
 535 #define NS_CFG_RXINT_314US   0x00002000
 536 #define NS_CFG_RXINT_624US   0x00003000
 537 #define NS_CFG_RXINT_899US   0x00004000
 538
 539 /* NICStAR STATus bits */
 540
 541 #define NS_STAT_SFBQC_MASK 0xFF000000   /* hi 8 bits Small Buffer Queue Count */
 542 #define NS_STAT_LFBQC_MASK 0x00FF0000   /* hi 8 bits Large Buffer Queue Count */
 543 #define NS_STAT_TSIF       0x00008000   /* Transmit Status Queue Indicator */
 544 #define NS_STAT_TXICP      0x00004000   /* Transmit Incomplete PDU */
 545 #define NS_STAT_TSQF       0x00001000   /* Transmit Status Queue Full */
 546 #define NS_STAT_TMROF      0x00000800   /* Timer Overflow */
 547 #define NS_STAT_PHYI       0x00000400   /* PHY Device Interrupt */
 548 #define NS_STAT_CMDBZ      0x00000200   /* Command Busy */
 549 #define NS_STAT_SFBQF      0x00000100   /* Small Buffer Queue Full */
 550 #define NS_STAT_LFBQF      0x00000080   /* Large Buffer Queue Full */
 551 #define NS_STAT_RSQF       0x00000040   /* Receive Status Queue Full */
 552 #define NS_STAT_EOPDU      0x00000020   /* End of PDU */
 553 #define NS_STAT_RAWCF      0x00000010   /* Raw Cell Flag */
 554 #define NS_STAT_SFBQE      0x00000008   /* Small Buffer Queue Empty */
 555 #define NS_STAT_LFBQE      0x00000004   /* Large Buffer Queue Empty */
 556 #define NS_STAT_RSQAF      0x00000002   /* Receive Status Queue Almost Full */
 557
 558 #define ns_stat_sfbqc_get(stat) (((stat) & NS_STAT_SFBQC_MASK) >> 23)
 559 #define ns_stat_lfbqc_get(stat) (((stat) & NS_STAT_LFBQC_MASK) >> 15)
 560
 561 /* #defines which depend on other #defines */
 562
 563 #define NS_TST0 NS_TST_FRSCD
 564 #define NS_TST1 (NS_TST_FRSCD + NS_TST_NUM_ENTRIES + 1)
 565
 566 #define NS_FRSCD (NS_TST1 + NS_TST_NUM_ENTRIES + 1)
 567 #define NS_FRSCD_SIZE 12        /* 12 dwords */
 568 #define NS_FRSCD_NUM ((NS_TST_FRSCD_END + 1 - NS_FRSCD) / NS_FRSCD_SIZE)
 569
 570 #if (NS_SMBUFSIZE == 48)
 571 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_48
 572 #elif (NS_SMBUFSIZE == 96)
 573 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_96
 574 #elif (NS_SMBUFSIZE == 240)
 575 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_240
 576 #elif (NS_SMBUFSIZE == 2048)
 577 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_2048
 578 #else
 579 #error NS_SMBUFSIZE is incorrect in nicstar.h
 580 #endif /* NS_SMBUFSIZE */
 581
 582 #if (NS_LGBUFSIZE == 2048)
 583 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_2048
 584 #elif (NS_LGBUFSIZE == 4096)
 585 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_4096
 586 #elif (NS_LGBUFSIZE == 8192)
 587 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_8192
 588 #elif (NS_LGBUFSIZE == 16384)
 589 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_16384
 590 #else
 591 #error NS_LGBUFSIZE is incorrect in nicstar.h
 592 #endif /* NS_LGBUFSIZE */
 593
 594 #if (NS_RSQSIZE == 2048)
 595 #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_2048
 596 #elif (NS_RSQSIZE == 4096)
 597 #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_4096
 598 #elif (NS_RSQSIZE == 8192)
 599 #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_8192
 600 #else
 601 #error NS_RSQSIZE is incorrect in nicstar.h
 602 #endif /* NS_RSQSIZE */
 603
 604 #if (NS_VPIBITS == 0)
 605 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_0
 606 #elif (NS_VPIBITS == 1)
 607 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_1
 608 #elif (NS_VPIBITS == 2)
 609 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_2
 610 #elif (NS_VPIBITS == 8)
 611 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_8
 612 #else
 613 #error NS_VPIBITS is incorrect in nicstar.h
 614 #endif /* NS_VPIBITS */
 615
 616 #ifdef RCQ_SUPPORT
 617 #define NS_CFG_RAWIE_OPT NS_CFG_RAWIE
 618 #else
 619 #define NS_CFG_RAWIE_OPT 0x00000000
 620 #endif /* RCQ_SUPPORT */
 621
 622 #ifdef ENABLE_TSQFIE
 623 #define NS_CFG_TSQFIE_OPT NS_CFG_TSQFIE
 624 #else
 625 #define NS_CFG_TSQFIE_OPT 0x00000000
 626 #endif /* ENABLE_TSQFIE */
 627
 628 /* PCI stuff */
 629
 630 #ifndef PCI_VENDOR_ID_IDT
 631 #define PCI_VENDOR_ID_IDT 0x111D
 632 #endif /* PCI_VENDOR_ID_IDT */
 633
 634 #ifndef PCI_DEVICE_ID_IDT_IDT77201
 635 #define PCI_DEVICE_ID_IDT_IDT77201 0x0001
 636 #endif /* PCI_DEVICE_ID_IDT_IDT77201 */
 637
 638 /* Device driver structures */
 639
 640 struct ns_skb_prv {
 641         u32 buf_type;           /* BUF_SM/BUF_LG/BUF_NONE */
 642         u32 dma;
 643         int iovcnt;
 644 };
 645
 646 #define NS_PRV_BUFTYPE(skb)   \
 647         (((struct ns_skb_prv *)(ATM_SKB(skb)+1))->buf_type)
 648 #define NS_PRV_DMA(skb) \
 649         (((struct ns_skb_prv *)(ATM_SKB(skb)+1))->dma)
 650 #define NS_PRV_IOVCNT(skb) \
 651         (((struct ns_skb_prv *)(ATM_SKB(skb)+1))->iovcnt)
 652
 653 typedef struct tsq_info {
 654         void *org;
 655         dma_addr_t dma;
 656         ns_tsi *base;
 657         ns_tsi *next;
 658         ns_tsi *last;
 659 } tsq_info;
 660
 661 typedef struct scq_info {
 662         void *org;
 663         dma_addr_t dma;
 664         ns_scqe *base;
 665         ns_scqe *last;
 666         ns_scqe *next;
 667         volatile ns_scqe *tail; /* Not related to the nicstar register */
 668         unsigned num_entries;
 669         struct sk_buff **skb;   /* Pointer to an array of pointers
 670                                    to the sk_buffs used for tx */
 671         u32 scd;                /* SRAM address of the corresponding
 672                                    SCD */
 673         int tbd_count;          /* Only meaningful on variable rate */
 674         wait_queue_head_t scqfull_waitq;
 675         volatile char full;     /* SCQ full indicator */
 676         spinlock_t lock;        /* SCQ spinlock */
 677 } scq_info;
 678
 679 typedef struct rsq_info {
 680         void *org;
 681         dma_addr_t dma;
 682         ns_rsqe *base;
 683         ns_rsqe *next;
 684         ns_rsqe *last;
 685 } rsq_info;
 686
 687 typedef struct skb_pool {
 688         volatile int count;     /* number of buffers in the queue */
 689         struct sk_buff_head queue;
 690 } skb_pool;
 691
 692 /* NOTE: for small and large buffer pools, the count is not used, as the
 693          actual value used for buffer management is the one read from the
 694          card. */
 695
 696 typedef struct vc_map {
 697         volatile unsigned int tx:1;     /* TX vc? */
 698         volatile unsigned int rx:1;     /* RX vc? */
 699         struct atm_vcc *tx_vcc, *rx_vcc;
 700         struct sk_buff *rx_iov; /* RX iovector skb */
 701         scq_info *scq;          /* To keep track of the SCQ */
 702         u32 cbr_scd;            /* SRAM address of the corresponding
 703                                    SCD. 0x00000000 for UBR/VBR/ABR */
 704         int tbd_count;
 705 } vc_map;
 706
 707 typedef struct ns_dev {
 708         int index;              /* Card ID to the device driver */
 709         int sram_size;          /* In k x 32bit words. 32 or 128 */
 710         void __iomem *membase;  /* Card's memory base address */
 711         unsigned long max_pcr;
 712         int rct_size;           /* Number of entries */
 713         int vpibits;
 714         int vcibits;
 715         struct pci_dev *pcidev;
 716         struct idr idr;
 717         struct atm_dev *atmdev;
 718         tsq_info tsq;
 719         rsq_info rsq;
 720         scq_info *scq0, *scq1, *scq2;   /* VBR SCQs */
 721         skb_pool sbpool;        /* Small buffers */
 722         skb_pool lbpool;        /* Large buffers */
 723         skb_pool hbpool;        /* Pre-allocated huge buffers */
 724         skb_pool iovpool;       /* iovector buffers */
 725         volatile int efbie;     /* Empty free buf. queue int. enabled */
 726         volatile u32 tst_addr;  /* SRAM address of the TST in use */
 727         volatile int tst_free_entries;
 728         vc_map vcmap[NS_MAX_RCTSIZE];
 729         vc_map *tste2vc[NS_TST_NUM_ENTRIES];
 730         vc_map *scd2vc[NS_FRSCD_NUM];
 731         buf_nr sbnr;
 732         buf_nr lbnr;
 733         buf_nr hbnr;
 734         buf_nr iovnr;
 735         int sbfqc;
 736         int lbfqc;
 737         struct sk_buff *sm_handle;
 738         u32 sm_addr;
 739         struct sk_buff *lg_handle;
 740         u32 lg_addr;
 741         struct sk_buff *rcbuf;  /* Current raw cell buffer */
 742         struct ns_rcqe *rawcell;
 743         u32 rawch;              /* Raw cell queue head */
 744         unsigned intcnt;        /* Interrupt counter */
 745         spinlock_t int_lock;    /* Interrupt lock */
 746         spinlock_t res_lock;    /* Card resource lock */
 747 } ns_dev;
 748
 749    /* NOTE: Each tste2vc entry relates a given TST entry to the corresponding
 750       CBR vc. If the entry is not allocated, it must be NULL.
 751
 752       There are two TSTs so the driver can modify them on the fly
 753       without stopping the transmission.
 754
 755       scd2vc allows us to find out unused fixed rate SCDs, because
 756       they must have a NULL pointer here. */
 757
 758 #endif /* _LINUX_NICSTAR_H_ */