arch/blackfin/mach-common/smp.c

   1 /*
   2  * IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
   3  *
   4  * Copyright 2007-2009 Analog Devices Inc.
   5  *                         Philippe Gerum <rpm@xenomai.org>
   6  *
   7  * Licensed under the GPL-2.
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/delay.h>
  12 #include <linux/init.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/sched.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/cache.h>
  17 #include <linux/profile.h>
  18 #include <linux/errno.h>
  19 #include <linux/mm.h>
  20 #include <linux/cpu.h>
  21 #include <linux/smp.h>
  22 #include <linux/cpumask.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/irq.h>
  25 #include <linux/slab.h>
  26 #include <asm/atomic.h>
  27 #include <asm/cacheflush.h>
  28 #include <asm/mmu_context.h>
  29 #include <asm/pgtable.h>
  30 #include <asm/pgalloc.h>
  31 #include <asm/processor.h>
  32 #include <asm/ptrace.h>
  33 #include <asm/cpu.h>
  34 #include <asm/time.h>
  35 #include <linux/err.h>
  36
  37 /*
  38  * Anomaly notes:
  39  * 05000120 - we always define corelock as 32-bit integer in L2
  40  */
  41 struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
  42
  43 #ifdef CONFIG_ICACHE_FLUSH_L1
  44 unsigned long blackfin_iflush_l1_entry[NR_CPUS];
  45 #endif
  46
  47 void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb,
  48         *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
  49         *init_saved_dcplb_fault_addr_coreb;
  50
  51 #define BFIN_IPI_RESCHEDULE   0
  52 #define BFIN_IPI_CALL_FUNC    1
  53 #define BFIN_IPI_CPU_STOP     2
  54
  55 struct blackfin_flush_data {
  56         unsigned long start;
  57         unsigned long end;
  58 };
  59
  60 void *secondary_stack;
  61
  62
  63 struct smp_call_struct {
  64         void (*func)(void *info);
  65         void *info;
  66         int wait;
  67         cpumask_t *waitmask;
  68 };
  69
  70 static struct blackfin_flush_data smp_flush_data;
  71
  72 static DEFINE_SPINLOCK(stop_lock);
  73
  74 struct ipi_message {
  75         unsigned long type;
  76         struct smp_call_struct call_struct;
  77 };
  78
  79 /* A magic number - stress test shows this is safe for common cases */
  80 #define BFIN_IPI_MSGQ_LEN 5
  81
  82 /* Simple FIFO buffer, overflow leads to panic */
  83 struct ipi_message_queue {
  84         spinlock_t lock;
  85         unsigned long count;
  86         unsigned long head; /* head of the queue */
  87         struct ipi_message ipi_message[BFIN_IPI_MSGQ_LEN];
  88 };
  89
  90 static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);
  91
  92 static void ipi_cpu_stop(unsigned int cpu)
  93 {
  94         spin_lock(&stop_lock);
  95         printk(KERN_CRIT "CPU%u: stopping\n", cpu);
  96         dump_stack();
  97         spin_unlock(&stop_lock);
  98
  99         cpu_clear(cpu, cpu_online_map);
 100
 101         local_irq_disable();
 102
 103         while (1)
 104                 SSYNC();
 105 }
 106
 107 static void ipi_flush_icache(void *info)
 108 {
 109         struct blackfin_flush_data *fdata = info;
 110
 111         /* Invalidate the memory holding the bounds of the flushed region. */
 112         blackfin_dcache_invalidate_range((unsigned long)fdata,
 113                                          (unsigned long)fdata + sizeof(*fdata));
 114
 115         /* Make sure all write buffers in the data side of the core
 116          * are flushed before trying to invalidate the icache.  This
 117          * needs to be after the data flush and before the icache
 118          * flush so that the SSYNC does the right thing in preventing
 119          * the instruction prefetcher from hitting things in cached
 120          * memory at the wrong time -- it runs much further ahead than
 121          * the pipeline.
 122          */
 123         SSYNC();
 124
 125         /* ipi_flaush_icache is invoked by generic flush_icache_range,
 126          * so call blackfin arch icache flush directly here.
 127          */
 128         blackfin_icache_flush_range(fdata->start, fdata->end);
 129 }
 130
 131 static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
 132 {
 133         int wait;
 134         void (*func)(void *info);
 135         void *info;
 136         func = msg->call_struct.func;
 137         info = msg->call_struct.info;
 138         wait = msg->call_struct.wait;
 139         func(info);
 140         if (wait) {
 141 #ifdef __ARCH_SYNC_CORE_DCACHE
 142                 /*
 143                  * 'wait' usually means synchronization between CPUs.
 144                  * Invalidate D cache in case shared data was changed
 145                  * by func() to ensure cache coherence.
 146                  */
 147                 resync_core_dcache();
 148 #endif
 149                 cpu_clear(cpu, *msg->call_struct.waitmask);
 150         }
 151 }
 152
 153 /* Use IRQ_SUPPLE_0 to request reschedule.
 154  * When returning from interrupt to user space,
 155  * there is chance to reschedule */
 156 static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
 157 {
 158         unsigned int cpu = smp_processor_id();
 159
 160         platform_clear_ipi(cpu, IRQ_SUPPLE_0);
 161         return IRQ_HANDLED;
 162 }
 163
 164 static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
 165 {
 166         struct ipi_message *msg;
 167         struct ipi_message_queue *msg_queue;
 168         unsigned int cpu = smp_processor_id();
 169         unsigned long flags;
 170
 171         platform_clear_ipi(cpu, IRQ_SUPPLE_1);
 172
 173         msg_queue = &__get_cpu_var(ipi_msg_queue);
 174
 175         spin_lock_irqsave(&msg_queue->lock, flags);
 176
 177         while (msg_queue->count) {
 178                 msg = &msg_queue->ipi_message[msg_queue->head];
 179                 switch (msg->type) {
 180                 case BFIN_IPI_CALL_FUNC:
 181                         spin_unlock_irqrestore(&msg_queue->lock, flags);
 182                         ipi_call_function(cpu, msg);
 183                         spin_lock_irqsave(&msg_queue->lock, flags);
 184                         break;
 185                 case BFIN_IPI_CPU_STOP:
 186                         spin_unlock_irqrestore(&msg_queue->lock, flags);
 187                         ipi_cpu_stop(cpu);
 188                         spin_lock_irqsave(&msg_queue->lock, flags);
 189                         break;
 190                 default:
 191                         printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n",
 192                                cpu, msg->type);
 193                         break;
 194                 }
 195                 msg_queue->head++;
 196                 msg_queue->head %= BFIN_IPI_MSGQ_LEN;
 197                 msg_queue->count--;
 198         }
 199         spin_unlock_irqrestore(&msg_queue->lock, flags);
 200         return IRQ_HANDLED;
 201 }
 202
 203 static void ipi_queue_init(void)
 204 {
 205         unsigned int cpu;
 206         struct ipi_message_queue *msg_queue;
 207         for_each_possible_cpu(cpu) {
 208                 msg_queue = &per_cpu(ipi_msg_queue, cpu);
 209                 spin_lock_init(&msg_queue->lock);
 210                 msg_queue->count = 0;
 211                 msg_queue->head = 0;
 212         }
 213 }
 214
 215 static inline void smp_send_message(cpumask_t callmap, unsigned long type,
 216                                         void (*func) (void *info), void *info, int wait)
 217 {
 218         unsigned int cpu;
 219         struct ipi_message_queue *msg_queue;
 220         struct ipi_message *msg;
 221         unsigned long flags, next_msg;
 222         cpumask_t waitmask = callmap; /* waitmask is shared by all cpus */
 223
 224         for_each_cpu_mask(cpu, callmap) {
 225                 msg_queue = &per_cpu(ipi_msg_queue, cpu);
 226                 spin_lock_irqsave(&msg_queue->lock, flags);
 227                 if (msg_queue->count < BFIN_IPI_MSGQ_LEN) {
 228                         next_msg = (msg_queue->head + msg_queue->count)
 229                                         % BFIN_IPI_MSGQ_LEN;
 230                         msg = &msg_queue->ipi_message[next_msg];
 231                         msg->type = type;
 232                         if (type == BFIN_IPI_CALL_FUNC) {
 233                                 msg->call_struct.func = func;
 234                                 msg->call_struct.info = info;
 235                                 msg->call_struct.wait = wait;
 236                                 msg->call_struct.waitmask = &waitmask;
 237                         }
 238                         msg_queue->count++;
 239                 } else
 240                         panic("IPI message queue overflow\n");
 241                 spin_unlock_irqrestore(&msg_queue->lock, flags);
 242                 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
 243         }
 244
 245         if (wait) {
 246                 while (!cpus_empty(waitmask))
 247                         blackfin_dcache_invalidate_range(
 248                                 (unsigned long)(&waitmask),
 249                                 (unsigned long)(&waitmask));
 250 #ifdef __ARCH_SYNC_CORE_DCACHE
 251                 /*
 252                  * Invalidate D cache in case shared data was changed by
 253                  * other processors to ensure cache coherence.
 254                  */
 255                 resync_core_dcache();
 256 #endif
 257         }
 258 }
 259
 260 int smp_call_function(void (*func)(void *info), void *info, int wait)
 261 {
 262         cpumask_t callmap;
 263
 264         preempt_disable();
 265         callmap = cpu_online_map;
 266         cpu_clear(smp_processor_id(), callmap);
 267         if (!cpus_empty(callmap))
 268                 smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
 269
 270         preempt_enable();
 271
 272         return 0;
 273 }
 274 EXPORT_SYMBOL_GPL(smp_call_function);
 275
 276 int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
 277                                 int wait)
 278 {
 279         unsigned int cpu = cpuid;
 280         cpumask_t callmap;
 281
 282         if (cpu_is_offline(cpu))
 283                 return 0;
 284         cpus_clear(callmap);
 285         cpu_set(cpu, callmap);
 286
 287         smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
 288
 289         return 0;
 290 }
 291 EXPORT_SYMBOL_GPL(smp_call_function_single);
 292
 293 void smp_send_reschedule(int cpu)
 294 {
 295         /* simply trigger an ipi */
 296         if (cpu_is_offline(cpu))
 297                 return;
 298         platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
 299
 300         return;
 301 }
 302
 303 void smp_send_stop(void)
 304 {
 305         cpumask_t callmap;
 306
 307         preempt_disable();
 308         callmap = cpu_online_map;
 309         cpu_clear(smp_processor_id(), callmap);
 310         if (!cpus_empty(callmap))
 311                 smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0);
 312
 313         preempt_enable();
 314
 315         return;
 316 }
 317
 318 int __cpuinit __cpu_up(unsigned int cpu)
 319 {
 320         int ret;
 321         static struct task_struct *idle;
 322
 323         if (idle)
 324                 free_task(idle);
 325
 326         idle = fork_idle(cpu);
 327         if (IS_ERR(idle)) {
 328                 printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
 329                 return PTR_ERR(idle);
 330         }
 331
 332         secondary_stack = task_stack_page(idle) + THREAD_SIZE;
 333
 334         ret = platform_boot_secondary(cpu, idle);
 335
 336         secondary_stack = NULL;
 337
 338         return ret;
 339 }
 340
 341 static void __cpuinit setup_secondary(unsigned int cpu)
 342 {
 343         unsigned long ilat;
 344
 345         bfin_write_IMASK(0);
 346         CSYNC();
 347         ilat = bfin_read_ILAT();
 348         CSYNC();
 349         bfin_write_ILAT(ilat);
 350         CSYNC();
 351
 352         /* Enable interrupt levels IVG7-15. IARs have been already
 353          * programmed by the boot CPU.  */
 354         bfin_irq_flags |= IMASK_IVG15 |
 355             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
 356             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
 357 }
 358
 359 void __cpuinit secondary_start_kernel(void)
 360 {
 361         unsigned int cpu = smp_processor_id();
 362         struct mm_struct *mm = &init_mm;
 363
 364         if (_bfin_swrst & SWRST_DBL_FAULT_B) {
 365                 printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
 366 #ifdef CONFIG_DEBUG_DOUBLEFAULT
 367                 printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
 368                         (int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb);
 369                 printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb);
 370                 printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb);
 371 #endif
 372                 printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
 373                         init_retx_coreb);
 374         }
 375
 376         /*
 377          * We want the D-cache to be enabled early, in case the atomic
 378          * support code emulates cache coherence (see
 379          * __ARCH_SYNC_CORE_DCACHE).
 380          */
 381         init_exception_vectors();
 382
 383         local_irq_disable();
 384
 385         /* Attach the new idle task to the global mm. */
 386         atomic_inc(&mm->mm_users);
 387         atomic_inc(&mm->mm_count);
 388         current->active_mm = mm;
 389
 390         preempt_disable();
 391
 392         setup_secondary(cpu);
 393
 394         platform_secondary_init(cpu);
 395
 396         /* setup local core timer */
 397         bfin_local_timer_setup();
 398
 399         local_irq_enable();
 400
 401         bfin_setup_caches(cpu);
 402
 403         /*
 404          * Calibrate loops per jiffy value.
 405          * IRQs need to be enabled here - D-cache can be invalidated
 406          * in timer irq handler, so core B can read correct jiffies.
 407          */
 408         calibrate_delay();
 409
 410         cpu_idle();
 411 }
 412
 413 void __init smp_prepare_boot_cpu(void)
 414 {
 415 }
 416
 417 void __init smp_prepare_cpus(unsigned int max_cpus)
 418 {
 419         platform_prepare_cpus(max_cpus);
 420         ipi_queue_init();
 421         platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
 422         platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
 423 }
 424
 425 void __init smp_cpus_done(unsigned int max_cpus)
 426 {
 427         unsigned long bogosum = 0;
 428         unsigned int cpu;
 429
 430         for_each_online_cpu(cpu)
 431                 bogosum += loops_per_jiffy;
 432
 433         printk(KERN_INFO "SMP: Total of %d processors activated "
 434                "(%lu.%02lu BogoMIPS).\n",
 435                num_online_cpus(),
 436                bogosum / (500000/HZ),
 437                (bogosum / (5000/HZ)) % 100);
 438 }
 439
 440 void smp_icache_flush_range_others(unsigned long start, unsigned long end)
 441 {
 442         smp_flush_data.start = start;
 443         smp_flush_data.end = end;
 444
 445         if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0))
 446                 printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
 447 }
 448 EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
 449
 450 #ifdef __ARCH_SYNC_CORE_ICACHE
 451 unsigned long icache_invld_count[NR_CPUS];
 452 void resync_core_icache(void)
 453 {
 454         unsigned int cpu = get_cpu();
 455         blackfin_invalidate_entire_icache();
 456         icache_invld_count[cpu]++;
 457         put_cpu();
 458 }
 459 EXPORT_SYMBOL(resync_core_icache);
 460 #endif
 461
 462 #ifdef __ARCH_SYNC_CORE_DCACHE
 463 unsigned long dcache_invld_count[NR_CPUS];
 464 unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
 465
 466 void resync_core_dcache(void)
 467 {
 468         unsigned int cpu = get_cpu();
 469         blackfin_invalidate_entire_dcache();
 470         dcache_invld_count[cpu]++;
 471         put_cpu();
 472 }
 473 EXPORT_SYMBOL(resync_core_dcache);
 474 #endif
 475
 476 #ifdef CONFIG_HOTPLUG_CPU
 477 int __cpuexit __cpu_disable(void)
 478 {
 479         unsigned int cpu = smp_processor_id();
 480
 481         if (cpu == 0)
 482                 return -EPERM;
 483
 484         set_cpu_online(cpu, false);
 485         return 0;
 486 }
 487
 488 static DECLARE_COMPLETION(cpu_killed);
 489
 490 int __cpuexit __cpu_die(unsigned int cpu)
 491 {
 492         return wait_for_completion_timeout(&cpu_killed, 5000);
 493 }
 494
 495 void cpu_die(void)
 496 {
 497         complete(&cpu_killed);
 498
 499         atomic_dec(&init_mm.mm_users);
 500         atomic_dec(&init_mm.mm_count);
 501
 502         local_irq_disable();
 503         platform_cpu_die();
 504 }
 505 #endif