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writeback: split writeback_inodes_wb
[linux-2.6/next.git] / drivers / i2c / busses / i2c-davinci.c
blob4523364e67221d3930cb3fd5c6ceb65b7fab7d4e
1 /*
2 * TI DAVINCI I2C adapter driver.
3 *
4 * Copyright (C) 2006 Texas Instruments.
5 * Copyright (C) 2007 MontaVista Software Inc.
6 *
7 * Updated by Vinod & Sudhakar Feb 2005
8 *
9 * ----------------------------------------------------------------------------
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * ----------------------------------------------------------------------------
25 *
26 */
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/delay.h>
30 #include <linux/i2c.h>
31 #include <linux/clk.h>
32 #include <linux/errno.h>
33 #include <linux/sched.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/platform_device.h>
37 #include <linux/io.h>
38 #include <linux/slab.h>
39
40 #include <mach/hardware.h>
41
42 #include <mach/i2c.h>
43
44 /* ----- global defines ----------------------------------------------- */
45
46 #define DAVINCI_I2C_TIMEOUT (1*HZ)
47 #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_AAS | \
48 DAVINCI_I2C_IMR_SCD | \
49 DAVINCI_I2C_IMR_ARDY | \
50 DAVINCI_I2C_IMR_NACK | \
51 DAVINCI_I2C_IMR_AL)
52
53 #define DAVINCI_I2C_OAR_REG 0x00
54 #define DAVINCI_I2C_IMR_REG 0x04
55 #define DAVINCI_I2C_STR_REG 0x08
56 #define DAVINCI_I2C_CLKL_REG 0x0c
57 #define DAVINCI_I2C_CLKH_REG 0x10
58 #define DAVINCI_I2C_CNT_REG 0x14
59 #define DAVINCI_I2C_DRR_REG 0x18
60 #define DAVINCI_I2C_SAR_REG 0x1c
61 #define DAVINCI_I2C_DXR_REG 0x20
62 #define DAVINCI_I2C_MDR_REG 0x24
63 #define DAVINCI_I2C_IVR_REG 0x28
64 #define DAVINCI_I2C_EMDR_REG 0x2c
65 #define DAVINCI_I2C_PSC_REG 0x30
66
67 #define DAVINCI_I2C_IVR_AAS 0x07
68 #define DAVINCI_I2C_IVR_SCD 0x06
69 #define DAVINCI_I2C_IVR_XRDY 0x05
70 #define DAVINCI_I2C_IVR_RDR 0x04
71 #define DAVINCI_I2C_IVR_ARDY 0x03
72 #define DAVINCI_I2C_IVR_NACK 0x02
73 #define DAVINCI_I2C_IVR_AL 0x01
74
75 #define DAVINCI_I2C_STR_BB (1 << 12)
76 #define DAVINCI_I2C_STR_RSFULL (1 << 11)
77 #define DAVINCI_I2C_STR_SCD (1 << 5)
78 #define DAVINCI_I2C_STR_ARDY (1 << 2)
79 #define DAVINCI_I2C_STR_NACK (1 << 1)
80 #define DAVINCI_I2C_STR_AL (1 << 0)
81
82 #define DAVINCI_I2C_MDR_NACK (1 << 15)
83 #define DAVINCI_I2C_MDR_STT (1 << 13)
84 #define DAVINCI_I2C_MDR_STP (1 << 11)
85 #define DAVINCI_I2C_MDR_MST (1 << 10)
86 #define DAVINCI_I2C_MDR_TRX (1 << 9)
87 #define DAVINCI_I2C_MDR_XA (1 << 8)
88 #define DAVINCI_I2C_MDR_RM (1 << 7)
89 #define DAVINCI_I2C_MDR_IRS (1 << 5)
90
91 #define DAVINCI_I2C_IMR_AAS (1 << 6)
92 #define DAVINCI_I2C_IMR_SCD (1 << 5)
93 #define DAVINCI_I2C_IMR_XRDY (1 << 4)
94 #define DAVINCI_I2C_IMR_RRDY (1 << 3)
95 #define DAVINCI_I2C_IMR_ARDY (1 << 2)
96 #define DAVINCI_I2C_IMR_NACK (1 << 1)
97 #define DAVINCI_I2C_IMR_AL (1 << 0)
98
99 #define MOD_REG_BIT(val, mask, set) do { \
100 if (set) { \
101 val |= mask; \
102 } else { \
103 val &= ~mask; \
104 } \
105 } while (0)
106
107 struct davinci_i2c_dev {
108 struct device *dev;
109 void __iomem *base;
110 struct completion cmd_complete;
111 struct clk *clk;
112 int cmd_err;
113 u8 *buf;
114 size_t buf_len;
115 int irq;
116 u8 terminate;
117 struct i2c_adapter adapter;
118 };
119
120 /* default platform data to use if not supplied in the platform_device */
121 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
122 .bus_freq = 100,
123 .bus_delay = 0,
124 };
125
126 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
127 int reg, u16 val)
128 {
129 __raw_writew(val, i2c_dev->base + reg);
130 }
131
132 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
133 {
134 return __raw_readw(i2c_dev->base + reg);
135 }
136
137 /*
138 * This functions configures I2C and brings I2C out of reset.
139 * This function is called during I2C init function. This function
140 * also gets called if I2C encounters any errors.
141 */
142 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
143 {
144 struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
145 u16 psc;
146 u32 clk;
147 u32 d;
148 u32 clkh;
149 u32 clkl;
150 u32 input_clock = clk_get_rate(dev->clk);
151 u16 w;
152
153 if (!pdata)
154 pdata = &davinci_i2c_platform_data_default;
155
156 /* put I2C into reset */
157 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
158 MOD_REG_BIT(w, DAVINCI_I2C_MDR_IRS, 0);
159 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
160
161 /* NOTE: I2C Clock divider programming info
162 * As per I2C specs the following formulas provide prescaler
163 * and low/high divider values
164 * input clk --> PSC Div -----------> ICCL/H Div --> output clock
165 * module clk
166 *
167 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
168 *
169 * Thus,
170 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
171 *
172 * where if PSC == 0, d = 7,
173 * if PSC == 1, d = 6
174 * if PSC > 1 , d = 5
175 */
176
177 /* get minimum of 7 MHz clock, but max of 12 MHz */
178 psc = (input_clock / 7000000) - 1;
179 if ((input_clock / (psc + 1)) > 12000000)
180 psc++; /* better to run under spec than over */
181 d = (psc >= 2) ? 5 : 7 - psc;
182
183 clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1);
184 clkh = clk >> 1;
185 clkl = clk - clkh;
186
187 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
188 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
189 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
190
191 /* Respond at reserved "SMBus Host" slave address" (and zero);
192 * we seem to have no option to not respond...
193 */
194 davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08);
195
196 dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
197 dev_dbg(dev->dev, "PSC = %d\n",
198 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
199 dev_dbg(dev->dev, "CLKL = %d\n",
200 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
201 dev_dbg(dev->dev, "CLKH = %d\n",
202 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
203 dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
204 pdata->bus_freq, pdata->bus_delay);
205
206 /* Take the I2C module out of reset: */
207 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
208 MOD_REG_BIT(w, DAVINCI_I2C_MDR_IRS, 1);
209 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
210
211 /* Enable interrupts */
212 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
213
214 return 0;
215 }
216
217 /*
218 * Waiting for bus not busy
219 */
220 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
221 char allow_sleep)
222 {
223 unsigned long timeout;
224
225 timeout = jiffies + dev->adapter.timeout;
226 while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
227 & DAVINCI_I2C_STR_BB) {
228 if (time_after(jiffies, timeout)) {
229 dev_warn(dev->dev,
230 "timeout waiting for bus ready\n");
231 return -ETIMEDOUT;
232 }
233 if (allow_sleep)
234 schedule_timeout(1);
235 }
236
237 return 0;
238 }
239
240 /*
241 * Low level master read/write transaction. This function is called
242 * from i2c_davinci_xfer.
243 */
244 static int
245 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
246 {
247 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
248 struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
249 u32 flag;
250 u16 w;
251 int r;
252
253 if (msg->len == 0)
254 return -EINVAL;
255
256 if (!pdata)
257 pdata = &davinci_i2c_platform_data_default;
258 /* Introduce a delay, required for some boards (e.g Davinci EVM) */
259 if (pdata->bus_delay)
260 udelay(pdata->bus_delay);
261
262 /* set the slave address */
263 davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
264
265 dev->buf = msg->buf;
266 dev->buf_len = msg->len;
267
268 davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
269
270 INIT_COMPLETION(dev->cmd_complete);
271 dev->cmd_err = 0;
272
273 /* Take I2C out of reset, configure it as master and set the
274 * start bit */
275 flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST | DAVINCI_I2C_MDR_STT;
276
277 /* if the slave address is ten bit address, enable XA bit */
278 if (msg->flags & I2C_M_TEN)
279 flag |= DAVINCI_I2C_MDR_XA;
280 if (!(msg->flags & I2C_M_RD))
281 flag |= DAVINCI_I2C_MDR_TRX;
282 if (stop)
283 flag |= DAVINCI_I2C_MDR_STP;
284
285 /* Enable receive or transmit interrupts */
286 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
287 if (msg->flags & I2C_M_RD)
288 MOD_REG_BIT(w, DAVINCI_I2C_IMR_RRDY, 1);
289 else
290 MOD_REG_BIT(w, DAVINCI_I2C_IMR_XRDY, 1);
291 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
292
293 dev->terminate = 0;
294 /* write the data into mode register */
295 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
296
297 r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
298 dev->adapter.timeout);
299 if (r == 0) {
300 dev_err(dev->dev, "controller timed out\n");
301 i2c_davinci_init(dev);
302 dev->buf_len = 0;
303 return -ETIMEDOUT;
304 }
305 if (dev->buf_len) {
306 /* This should be 0 if all bytes were transferred
307 * or dev->cmd_err denotes an error.
308 * A signal may have aborted the transfer.
309 */
310 if (r >= 0) {
311 dev_err(dev->dev, "abnormal termination buf_len=%i\n",
312 dev->buf_len);
313 r = -EREMOTEIO;
314 }
315 dev->terminate = 1;
316 wmb();
317 dev->buf_len = 0;
318 }
319 if (r < 0)
320 return r;
321
322 /* no error */
323 if (likely(!dev->cmd_err))
324 return msg->len;
325
326 /* We have an error */
327 if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
328 i2c_davinci_init(dev);
329 return -EIO;
330 }
331
332 if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
333 if (msg->flags & I2C_M_IGNORE_NAK)
334 return msg->len;
335 if (stop) {
336 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
337 MOD_REG_BIT(w, DAVINCI_I2C_MDR_STP, 1);
338 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
339 }
340 return -EREMOTEIO;
341 }
342 return -EIO;
343 }
344
345 /*
346 * Prepare controller for a transaction and call i2c_davinci_xfer_msg
347 */
348 static int
349 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
350 {
351 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
352 int i;
353 int ret;
354
355 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
356
357 ret = i2c_davinci_wait_bus_not_busy(dev, 1);
358 if (ret < 0) {
359 dev_warn(dev->dev, "timeout waiting for bus ready\n");
360 return ret;
361 }
362
363 for (i = 0; i < num; i++) {
364 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
365 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
366 ret);
367 if (ret < 0)
368 return ret;
369 }
370 return num;
371 }
372
373 static u32 i2c_davinci_func(struct i2c_adapter *adap)
374 {
375 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
376 }
377
378 static void terminate_read(struct davinci_i2c_dev *dev)
379 {
380 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
381 w |= DAVINCI_I2C_MDR_NACK;
382 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
383
384 /* Throw away data */
385 davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
386 if (!dev->terminate)
387 dev_err(dev->dev, "RDR IRQ while no data requested\n");
388 }
389 static void terminate_write(struct davinci_i2c_dev *dev)
390 {
391 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
392 w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
393 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
394
395 if (!dev->terminate)
396 dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
397 }
398
399 /*
400 * Interrupt service routine. This gets called whenever an I2C interrupt
401 * occurs.
402 */
403 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
404 {
405 struct davinci_i2c_dev *dev = dev_id;
406 u32 stat;
407 int count = 0;
408 u16 w;
409
410 while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
411 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
412 if (count++ == 100) {
413 dev_warn(dev->dev, "Too much work in one IRQ\n");
414 break;
415 }
416
417 switch (stat) {
418 case DAVINCI_I2C_IVR_AL:
419 /* Arbitration lost, must retry */
420 dev->cmd_err |= DAVINCI_I2C_STR_AL;
421 dev->buf_len = 0;
422 complete(&dev->cmd_complete);
423 break;
424
425 case DAVINCI_I2C_IVR_NACK:
426 dev->cmd_err |= DAVINCI_I2C_STR_NACK;
427 dev->buf_len = 0;
428 complete(&dev->cmd_complete);
429 break;
430
431 case DAVINCI_I2C_IVR_ARDY:
432 davinci_i2c_write_reg(dev,
433 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
434 complete(&dev->cmd_complete);
435 break;
436
437 case DAVINCI_I2C_IVR_RDR:
438 if (dev->buf_len) {
439 *dev->buf++ =
440 davinci_i2c_read_reg(dev,
441 DAVINCI_I2C_DRR_REG);
442 dev->buf_len--;
443 if (dev->buf_len)
444 continue;
445
446 davinci_i2c_write_reg(dev,
447 DAVINCI_I2C_STR_REG,
448 DAVINCI_I2C_IMR_RRDY);
449 } else {
450 /* signal can terminate transfer */
451 terminate_read(dev);
452 }
453 break;
454
455 case DAVINCI_I2C_IVR_XRDY:
456 if (dev->buf_len) {
457 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
458 *dev->buf++);
459 dev->buf_len--;
460 if (dev->buf_len)
461 continue;
462
463 w = davinci_i2c_read_reg(dev,
464 DAVINCI_I2C_IMR_REG);
465 MOD_REG_BIT(w, DAVINCI_I2C_IMR_XRDY, 0);
466 davinci_i2c_write_reg(dev,
467 DAVINCI_I2C_IMR_REG,
468 w);
469 } else {
470 /* signal can terminate transfer */
471 terminate_write(dev);
472 }
473 break;
474
475 case DAVINCI_I2C_IVR_SCD:
476 davinci_i2c_write_reg(dev,
477 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
478 complete(&dev->cmd_complete);
479 break;
480
481 case DAVINCI_I2C_IVR_AAS:
482 dev_dbg(dev->dev, "Address as slave interrupt\n");
483 break;
484
485 default:
486 dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
487 break;
488 }
489 }
490
491 return count ? IRQ_HANDLED : IRQ_NONE;
492 }
493
494 static struct i2c_algorithm i2c_davinci_algo = {
495 .master_xfer = i2c_davinci_xfer,
496 .functionality = i2c_davinci_func,
497 };
498
499 static int davinci_i2c_probe(struct platform_device *pdev)
500 {
501 struct davinci_i2c_dev *dev;
502 struct i2c_adapter *adap;
503 struct resource *mem, *irq, *ioarea;
504 int r;
505
506 /* NOTE: driver uses the static register mapping */
507 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
508 if (!mem) {
509 dev_err(&pdev->dev, "no mem resource?\n");
510 return -ENODEV;
511 }
512
513 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
514 if (!irq) {
515 dev_err(&pdev->dev, "no irq resource?\n");
516 return -ENODEV;
517 }
518
519 ioarea = request_mem_region(mem->start, resource_size(mem),
520 pdev->name);
521 if (!ioarea) {
522 dev_err(&pdev->dev, "I2C region already claimed\n");
523 return -EBUSY;
524 }
525
526 dev = kzalloc(sizeof(struct davinci_i2c_dev), GFP_KERNEL);
527 if (!dev) {
528 r = -ENOMEM;
529 goto err_release_region;
530 }
531
532 init_completion(&dev->cmd_complete);
533 dev->dev = get_device(&pdev->dev);
534 dev->irq = irq->start;
535 platform_set_drvdata(pdev, dev);
536
537 dev->clk = clk_get(&pdev->dev, NULL);
538 if (IS_ERR(dev->clk)) {
539 r = -ENODEV;
540 goto err_free_mem;
541 }
542 clk_enable(dev->clk);
543
544 dev->base = (void __iomem *)IO_ADDRESS(mem->start);
545 i2c_davinci_init(dev);
546
547 r = request_irq(dev->irq, i2c_davinci_isr, 0, pdev->name, dev);
548 if (r) {
549 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
550 goto err_unuse_clocks;
551 }
552
553 adap = &dev->adapter;
554 i2c_set_adapdata(adap, dev);
555 adap->owner = THIS_MODULE;
556 adap->class = I2C_CLASS_HWMON;
557 strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
558 adap->algo = &i2c_davinci_algo;
559 adap->dev.parent = &pdev->dev;
560 adap->timeout = DAVINCI_I2C_TIMEOUT;
561
562 adap->nr = pdev->id;
563 r = i2c_add_numbered_adapter(adap);
564 if (r) {
565 dev_err(&pdev->dev, "failure adding adapter\n");
566 goto err_free_irq;
567 }
568
569 return 0;
570
571 err_free_irq:
572 free_irq(dev->irq, dev);
573 err_unuse_clocks:
574 clk_disable(dev->clk);
575 clk_put(dev->clk);
576 dev->clk = NULL;
577 err_free_mem:
578 platform_set_drvdata(pdev, NULL);
579 put_device(&pdev->dev);
580 kfree(dev);
581 err_release_region:
582 release_mem_region(mem->start, resource_size(mem));
583
584 return r;
585 }
586
587 static int davinci_i2c_remove(struct platform_device *pdev)
588 {
589 struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
590 struct resource *mem;
591
592 platform_set_drvdata(pdev, NULL);
593 i2c_del_adapter(&dev->adapter);
594 put_device(&pdev->dev);
595
596 clk_disable(dev->clk);
597 clk_put(dev->clk);
598 dev->clk = NULL;
599
600 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
601 free_irq(IRQ_I2C, dev);
602 kfree(dev);
603
604 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
605 release_mem_region(mem->start, resource_size(mem));
606 return 0;
607 }
608
609 /* work with hotplug and coldplug */
610 MODULE_ALIAS("platform:i2c_davinci");
611
612 static struct platform_driver davinci_i2c_driver = {
613 .probe = davinci_i2c_probe,
614 .remove = davinci_i2c_remove,
615 .driver = {
616 .name = "i2c_davinci",
617 .owner = THIS_MODULE,
618 },
619 };
620
621 /* I2C may be needed to bring up other drivers */
622 static int __init davinci_i2c_init_driver(void)
623 {
624 return platform_driver_register(&davinci_i2c_driver);
625 }
626 subsys_initcall(davinci_i2c_init_driver);
627
628 static void __exit davinci_i2c_exit_driver(void)
629 {
630 platform_driver_unregister(&davinci_i2c_driver);
631 }
632 module_exit(davinci_i2c_exit_driver);
633
634 MODULE_AUTHOR("Texas Instruments India");
635 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
636 MODULE_LICENSE("GPL");
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