include/linux/dmaengine.h

   1 /*
   2  * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc., 59
  16  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called COPYING.
  20  */
  21 #ifndef DMAENGINE_H
  22 #define DMAENGINE_H
  23
  24 #include <linux/device.h>
  25 #include <linux/uio.h>
  26 #include <linux/dma-mapping.h>
  27
  28 /**
  29  * typedef dma_cookie_t - an opaque DMA cookie
  30  *
  31  * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
  32  */
  33 typedef s32 dma_cookie_t;
  34 #define DMA_MIN_COOKIE  1
  35 #define DMA_MAX_COOKIE  INT_MAX
  36
  37 #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
  38
  39 /**
  40  * enum dma_status - DMA transaction status
  41  * @DMA_SUCCESS: transaction completed successfully
  42  * @DMA_IN_PROGRESS: transaction not yet processed
  43  * @DMA_PAUSED: transaction is paused
  44  * @DMA_ERROR: transaction failed
  45  */
  46 enum dma_status {
  47         DMA_SUCCESS,
  48         DMA_IN_PROGRESS,
  49         DMA_PAUSED,
  50         DMA_ERROR,
  51 };
  52
  53 /**
  54  * enum dma_transaction_type - DMA transaction types/indexes
  55  *
  56  * Note: The DMA_ASYNC_TX capability is not to be set by drivers.  It is
  57  * automatically set as dma devices are registered.
  58  */
  59 enum dma_transaction_type {
  60         DMA_MEMCPY,
  61         DMA_XOR,
  62         DMA_PQ,
  63         DMA_XOR_VAL,
  64         DMA_PQ_VAL,
  65         DMA_MEMSET,
  66         DMA_INTERRUPT,
  67         DMA_PRIVATE,
  68         DMA_ASYNC_TX,
  69         DMA_SLAVE,
  70 };
  71
  72 /* last transaction type for creation of the capabilities mask */
  73 #define DMA_TX_TYPE_END (DMA_SLAVE + 1)
  74
  75
  76 /**
  77  * enum dma_ctrl_flags - DMA flags to augment operation preparation,
  78  *  control completion, and communicate status.
  79  * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
  80  *  this transaction
  81  * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
  82  *  acknowledges receipt, i.e. has has a chance to establish any dependency
  83  *  chains
  84  * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
  85  * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
  86  * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single
  87  *      (if not set, do the source dma-unmapping as page)
  88  * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single
  89  *      (if not set, do the destination dma-unmapping as page)
  90  * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
  91  * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
  92  * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
  93  *  sources that were the result of a previous operation, in the case of a PQ
  94  *  operation it continues the calculation with new sources
  95  * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
  96  *  on the result of this operation
  97  */
  98 enum dma_ctrl_flags {
  99         DMA_PREP_INTERRUPT = (1 << 0),
 100         DMA_CTRL_ACK = (1 << 1),
 101         DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
 102         DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
 103         DMA_COMPL_SRC_UNMAP_SINGLE = (1 << 4),
 104         DMA_COMPL_DEST_UNMAP_SINGLE = (1 << 5),
 105         DMA_PREP_PQ_DISABLE_P = (1 << 6),
 106         DMA_PREP_PQ_DISABLE_Q = (1 << 7),
 107         DMA_PREP_CONTINUE = (1 << 8),
 108         DMA_PREP_FENCE = (1 << 9),
 109 };
 110
 111 /**
 112  * enum dma_ctrl_cmd - DMA operations that can optionally be exercised
 113  * on a running channel.
 114  * @DMA_TERMINATE_ALL: terminate all ongoing transfers
 115  * @DMA_PAUSE: pause ongoing transfers
 116  * @DMA_RESUME: resume paused transfer
 117  */
 118 enum dma_ctrl_cmd {
 119         DMA_TERMINATE_ALL,
 120         DMA_PAUSE,
 121         DMA_RESUME,
 122 };
 123
 124 /**
 125  * enum sum_check_bits - bit position of pq_check_flags
 126  */
 127 enum sum_check_bits {
 128         SUM_CHECK_P = 0,
 129         SUM_CHECK_Q = 1,
 130 };
 131
 132 /**
 133  * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
 134  * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
 135  * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
 136  */
 137 enum sum_check_flags {
 138         SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
 139         SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
 140 };
 141
 142
 143 /**
 144  * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
 145  * See linux/cpumask.h
 146  */
 147 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
 148
 149 /**
 150  * struct dma_chan_percpu - the per-CPU part of struct dma_chan
 151  * @memcpy_count: transaction counter
 152  * @bytes_transferred: byte counter
 153  */
 154
 155 struct dma_chan_percpu {
 156         /* stats */
 157         unsigned long memcpy_count;
 158         unsigned long bytes_transferred;
 159 };
 160
 161 /**
 162  * struct dma_chan - devices supply DMA channels, clients use them
 163  * @device: ptr to the dma device who supplies this channel, always !%NULL
 164  * @cookie: last cookie value returned to client
 165  * @chan_id: channel ID for sysfs
 166  * @dev: class device for sysfs
 167  * @device_node: used to add this to the device chan list
 168  * @local: per-cpu pointer to a struct dma_chan_percpu
 169  * @client-count: how many clients are using this channel
 170  * @table_count: number of appearances in the mem-to-mem allocation table
 171  * @private: private data for certain client-channel associations
 172  */
 173 struct dma_chan {
 174         struct dma_device *device;
 175         dma_cookie_t cookie;
 176
 177         /* sysfs */
 178         int chan_id;
 179         struct dma_chan_dev *dev;
 180
 181         struct list_head device_node;
 182         struct dma_chan_percpu __percpu *local;
 183         int client_count;
 184         int table_count;
 185         void *private;
 186 };
 187
 188 /**
 189  * struct dma_chan_dev - relate sysfs device node to backing channel device
 190  * @chan - driver channel device
 191  * @device - sysfs device
 192  * @dev_id - parent dma_device dev_id
 193  * @idr_ref - reference count to gate release of dma_device dev_id
 194  */
 195 struct dma_chan_dev {
 196         struct dma_chan *chan;
 197         struct device device;
 198         int dev_id;
 199         atomic_t *idr_ref;
 200 };
 201
 202 static inline const char *dma_chan_name(struct dma_chan *chan)
 203 {
 204         return dev_name(&chan->dev->device);
 205 }
 206
 207 void dma_chan_cleanup(struct kref *kref);
 208
 209 /**
 210  * typedef dma_filter_fn - callback filter for dma_request_channel
 211  * @chan: channel to be reviewed
 212  * @filter_param: opaque parameter passed through dma_request_channel
 213  *
 214  * When this optional parameter is specified in a call to dma_request_channel a
 215  * suitable channel is passed to this routine for further dispositioning before
 216  * being returned.  Where 'suitable' indicates a non-busy channel that
 217  * satisfies the given capability mask.  It returns 'true' to indicate that the
 218  * channel is suitable.
 219  */
 220 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
 221
 222 typedef void (*dma_async_tx_callback)(void *dma_async_param);
 223 /**
 224  * struct dma_async_tx_descriptor - async transaction descriptor
 225  * ---dma generic offload fields---
 226  * @cookie: tracking cookie for this transaction, set to -EBUSY if
 227  *      this tx is sitting on a dependency list
 228  * @flags: flags to augment operation preparation, control completion, and
 229  *      communicate status
 230  * @phys: physical address of the descriptor
 231  * @chan: target channel for this operation
 232  * @tx_submit: set the prepared descriptor(s) to be executed by the engine
 233  * @callback: routine to call after this operation is complete
 234  * @callback_param: general parameter to pass to the callback routine
 235  * ---async_tx api specific fields---
 236  * @next: at completion submit this descriptor
 237  * @parent: pointer to the next level up in the dependency chain
 238  * @lock: protect the parent and next pointers
 239  */
 240 struct dma_async_tx_descriptor {
 241         dma_cookie_t cookie;
 242         enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
 243         dma_addr_t phys;
 244         struct dma_chan *chan;
 245         dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
 246         dma_async_tx_callback callback;
 247         void *callback_param;
 248 #ifndef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH
 249         struct dma_async_tx_descriptor *next;
 250         struct dma_async_tx_descriptor *parent;
 251         spinlock_t lock;
 252 #endif
 253 };
 254
 255 #ifdef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH
 256 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
 257 {
 258 }
 259 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
 260 {
 261 }
 262 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
 263 {
 264         BUG();
 265 }
 266 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
 267 {
 268 }
 269 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
 270 {
 271 }
 272 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
 273 {
 274         return NULL;
 275 }
 276 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
 277 {
 278         return NULL;
 279 }
 280
 281 #else
 282 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
 283 {
 284         spin_lock_bh(&txd->lock);
 285 }
 286 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
 287 {
 288         spin_unlock_bh(&txd->lock);
 289 }
 290 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
 291 {
 292         txd->next = next;
 293         next->parent = txd;
 294 }
 295 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
 296 {
 297         txd->parent = NULL;
 298 }
 299 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
 300 {
 301         txd->next = NULL;
 302 }
 303 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
 304 {
 305         return txd->parent;
 306 }
 307 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
 308 {
 309         return txd->next;
 310 }
 311 #endif
 312
 313 /**
 314  * struct dma_tx_state - filled in to report the status of
 315  * a transfer.
 316  * @last: last completed DMA cookie
 317  * @used: last issued DMA cookie (i.e. the one in progress)
 318  * @residue: the remaining number of bytes left to transmit
 319  *      on the selected transfer for states DMA_IN_PROGRESS and
 320  *      DMA_PAUSED if this is implemented in the driver, else 0
 321  */
 322 struct dma_tx_state {
 323         dma_cookie_t last;
 324         dma_cookie_t used;
 325         u32 residue;
 326 };
 327
 328 /**
 329  * struct dma_device - info on the entity supplying DMA services
 330  * @chancnt: how many DMA channels are supported
 331  * @privatecnt: how many DMA channels are requested by dma_request_channel
 332  * @channels: the list of struct dma_chan
 333  * @global_node: list_head for global dma_device_list
 334  * @cap_mask: one or more dma_capability flags
 335  * @max_xor: maximum number of xor sources, 0 if no capability
 336  * @max_pq: maximum number of PQ sources and PQ-continue capability
 337  * @copy_align: alignment shift for memcpy operations
 338  * @xor_align: alignment shift for xor operations
 339  * @pq_align: alignment shift for pq operations
 340  * @fill_align: alignment shift for memset operations
 341  * @dev_id: unique device ID
 342  * @dev: struct device reference for dma mapping api
 343  * @device_alloc_chan_resources: allocate resources and return the
 344  *      number of allocated descriptors
 345  * @device_free_chan_resources: release DMA channel's resources
 346  * @device_prep_dma_memcpy: prepares a memcpy operation
 347  * @device_prep_dma_xor: prepares a xor operation
 348  * @device_prep_dma_xor_val: prepares a xor validation operation
 349  * @device_prep_dma_pq: prepares a pq operation
 350  * @device_prep_dma_pq_val: prepares a pqzero_sum operation
 351  * @device_prep_dma_memset: prepares a memset operation
 352  * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
 353  * @device_prep_slave_sg: prepares a slave dma operation
 354  * @device_control: manipulate all pending operations on a channel, returns
 355  *      zero or error code
 356  * @device_tx_status: poll for transaction completion, the optional
 357  *      txstate parameter can be supplied with a pointer to get a
 358  *      struct with auxilary transfer status information, otherwise the call
 359  *      will just return a simple status code
 360  * @device_issue_pending: push pending transactions to hardware
 361  */
 362 struct dma_device {
 363
 364         unsigned int chancnt;
 365         unsigned int privatecnt;
 366         struct list_head channels;
 367         struct list_head global_node;
 368         dma_cap_mask_t  cap_mask;
 369         unsigned short max_xor;
 370         unsigned short max_pq;
 371         u8 copy_align;
 372         u8 xor_align;
 373         u8 pq_align;
 374         u8 fill_align;
 375         #define DMA_HAS_PQ_CONTINUE (1 << 15)
 376
 377         int dev_id;
 378         struct device *dev;
 379
 380         int (*device_alloc_chan_resources)(struct dma_chan *chan);
 381         void (*device_free_chan_resources)(struct dma_chan *chan);
 382
 383         struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
 384                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 385                 size_t len, unsigned long flags);
 386         struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
 387                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
 388                 unsigned int src_cnt, size_t len, unsigned long flags);
 389         struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
 390                 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
 391                 size_t len, enum sum_check_flags *result, unsigned long flags);
 392         struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
 393                 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
 394                 unsigned int src_cnt, const unsigned char *scf,
 395                 size_t len, unsigned long flags);
 396         struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
 397                 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
 398                 unsigned int src_cnt, const unsigned char *scf, size_t len,
 399                 enum sum_check_flags *pqres, unsigned long flags);
 400         struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
 401                 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
 402                 unsigned long flags);
 403         struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
 404                 struct dma_chan *chan, unsigned long flags);
 405
 406         struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
 407                 struct dma_chan *chan, struct scatterlist *sgl,
 408                 unsigned int sg_len, enum dma_data_direction direction,
 409                 unsigned long flags);
 410         int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 411                 unsigned long arg);
 412
 413         enum dma_status (*device_tx_status)(struct dma_chan *chan,
 414                                             dma_cookie_t cookie,
 415                                             struct dma_tx_state *txstate);
 416         void (*device_issue_pending)(struct dma_chan *chan);
 417 };
 418
 419 static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len)
 420 {
 421         size_t mask;
 422
 423         if (!align)
 424                 return true;
 425         mask = (1 << align) - 1;
 426         if (mask & (off1 | off2 | len))
 427                 return false;
 428         return true;
 429 }
 430
 431 static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
 432                                        size_t off2, size_t len)
 433 {
 434         return dmaengine_check_align(dev->copy_align, off1, off2, len);
 435 }
 436
 437 static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
 438                                       size_t off2, size_t len)
 439 {
 440         return dmaengine_check_align(dev->xor_align, off1, off2, len);
 441 }
 442
 443 static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
 444                                      size_t off2, size_t len)
 445 {
 446         return dmaengine_check_align(dev->pq_align, off1, off2, len);
 447 }
 448
 449 static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
 450                                        size_t off2, size_t len)
 451 {
 452         return dmaengine_check_align(dev->fill_align, off1, off2, len);
 453 }
 454
 455 static inline void
 456 dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
 457 {
 458         dma->max_pq = maxpq;
 459         if (has_pq_continue)
 460                 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
 461 }
 462
 463 static inline bool dmaf_continue(enum dma_ctrl_flags flags)
 464 {
 465         return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
 466 }
 467
 468 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
 469 {
 470         enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
 471
 472         return (flags & mask) == mask;
 473 }
 474
 475 static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
 476 {
 477         return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
 478 }
 479
 480 static unsigned short dma_dev_to_maxpq(struct dma_device *dma)
 481 {
 482         return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
 483 }
 484
 485 /* dma_maxpq - reduce maxpq in the face of continued operations
 486  * @dma - dma device with PQ capability
 487  * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
 488  *
 489  * When an engine does not support native continuation we need 3 extra
 490  * source slots to reuse P and Q with the following coefficients:
 491  * 1/ {00} * P : remove P from Q', but use it as a source for P'
 492  * 2/ {01} * Q : use Q to continue Q' calculation
 493  * 3/ {00} * Q : subtract Q from P' to cancel (2)
 494  *
 495  * In the case where P is disabled we only need 1 extra source:
 496  * 1/ {01} * Q : use Q to continue Q' calculation
 497  */
 498 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
 499 {
 500         if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
 501                 return dma_dev_to_maxpq(dma);
 502         else if (dmaf_p_disabled_continue(flags))
 503                 return dma_dev_to_maxpq(dma) - 1;
 504         else if (dmaf_continue(flags))
 505                 return dma_dev_to_maxpq(dma) - 3;
 506         BUG();
 507 }
 508
 509 /* --- public DMA engine API --- */
 510
 511 #ifdef CONFIG_DMA_ENGINE
 512 void dmaengine_get(void);
 513 void dmaengine_put(void);
 514 #else
 515 static inline void dmaengine_get(void)
 516 {
 517 }
 518 static inline void dmaengine_put(void)
 519 {
 520 }
 521 #endif
 522
 523 #ifdef CONFIG_NET_DMA
 524 #define net_dmaengine_get()     dmaengine_get()
 525 #define net_dmaengine_put()     dmaengine_put()
 526 #else
 527 static inline void net_dmaengine_get(void)
 528 {
 529 }
 530 static inline void net_dmaengine_put(void)
 531 {
 532 }
 533 #endif
 534
 535 #ifdef CONFIG_ASYNC_TX_DMA
 536 #define async_dmaengine_get()   dmaengine_get()
 537 #define async_dmaengine_put()   dmaengine_put()
 538 #ifdef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH
 539 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
 540 #else
 541 #define async_dma_find_channel(type) dma_find_channel(type)
 542 #endif /* CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH */
 543 #else
 544 static inline void async_dmaengine_get(void)
 545 {
 546 }
 547 static inline void async_dmaengine_put(void)
 548 {
 549 }
 550 static inline struct dma_chan *
 551 async_dma_find_channel(enum dma_transaction_type type)
 552 {
 553         return NULL;
 554 }
 555 #endif /* CONFIG_ASYNC_TX_DMA */
 556
 557 dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
 558         void *dest, void *src, size_t len);
 559 dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
 560         struct page *page, unsigned int offset, void *kdata, size_t len);
 561 dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
 562         struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
 563         unsigned int src_off, size_t len);
 564 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
 565         struct dma_chan *chan);
 566
 567 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
 568 {
 569         tx->flags |= DMA_CTRL_ACK;
 570 }
 571
 572 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
 573 {
 574         tx->flags &= ~DMA_CTRL_ACK;
 575 }
 576
 577 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
 578 {
 579         return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
 580 }
 581
 582 #define first_dma_cap(mask) __first_dma_cap(&(mask))
 583 static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
 584 {
 585         return min_t(int, DMA_TX_TYPE_END,
 586                 find_first_bit(srcp->bits, DMA_TX_TYPE_END));
 587 }
 588
 589 #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
 590 static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
 591 {
 592         return min_t(int, DMA_TX_TYPE_END,
 593                 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
 594 }
 595
 596 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
 597 static inline void
 598 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
 599 {
 600         set_bit(tx_type, dstp->bits);
 601 }
 602
 603 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
 604 static inline void
 605 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
 606 {
 607         clear_bit(tx_type, dstp->bits);
 608 }
 609
 610 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
 611 static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
 612 {
 613         bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
 614 }
 615
 616 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
 617 static inline int
 618 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
 619 {
 620         return test_bit(tx_type, srcp->bits);
 621 }
 622
 623 #define for_each_dma_cap_mask(cap, mask) \
 624         for ((cap) = first_dma_cap(mask);       \
 625                 (cap) < DMA_TX_TYPE_END;        \
 626                 (cap) = next_dma_cap((cap), (mask)))
 627
 628 /**
 629  * dma_async_issue_pending - flush pending transactions to HW
 630  * @chan: target DMA channel
 631  *
 632  * This allows drivers to push copies to HW in batches,
 633  * reducing MMIO writes where possible.
 634  */
 635 static inline void dma_async_issue_pending(struct dma_chan *chan)
 636 {
 637         chan->device->device_issue_pending(chan);
 638 }
 639
 640 #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
 641
 642 /**
 643  * dma_async_is_tx_complete - poll for transaction completion
 644  * @chan: DMA channel
 645  * @cookie: transaction identifier to check status of
 646  * @last: returns last completed cookie, can be NULL
 647  * @used: returns last issued cookie, can be NULL
 648  *
 649  * If @last and @used are passed in, upon return they reflect the driver
 650  * internal state and can be used with dma_async_is_complete() to check
 651  * the status of multiple cookies without re-checking hardware state.
 652  */
 653 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
 654         dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
 655 {
 656         struct dma_tx_state state;
 657         enum dma_status status;
 658
 659         status = chan->device->device_tx_status(chan, cookie, &state);
 660         if (last)
 661                 *last = state.last;
 662         if (used)
 663                 *used = state.used;
 664         return status;
 665 }
 666
 667 #define dma_async_memcpy_complete(chan, cookie, last, used)\
 668         dma_async_is_tx_complete(chan, cookie, last, used)
 669
 670 /**
 671  * dma_async_is_complete - test a cookie against chan state
 672  * @cookie: transaction identifier to test status of
 673  * @last_complete: last know completed transaction
 674  * @last_used: last cookie value handed out
 675  *
 676  * dma_async_is_complete() is used in dma_async_memcpy_complete()
 677  * the test logic is separated for lightweight testing of multiple cookies
 678  */
 679 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
 680                         dma_cookie_t last_complete, dma_cookie_t last_used)
 681 {
 682         if (last_complete <= last_used) {
 683                 if ((cookie <= last_complete) || (cookie > last_used))
 684                         return DMA_SUCCESS;
 685         } else {
 686                 if ((cookie <= last_complete) && (cookie > last_used))
 687                         return DMA_SUCCESS;
 688         }
 689         return DMA_IN_PROGRESS;
 690 }
 691
 692 static inline void
 693 dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
 694 {
 695         if (st) {
 696                 st->last = last;
 697                 st->used = used;
 698                 st->residue = residue;
 699         }
 700 }
 701
 702 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
 703 #ifdef CONFIG_DMA_ENGINE
 704 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
 705 void dma_issue_pending_all(void);
 706 #else
 707 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
 708 {
 709         return DMA_SUCCESS;
 710 }
 711 static inline void dma_issue_pending_all(void)
 712 {
 713         do { } while (0);
 714 }
 715 #endif
 716
 717 /* --- DMA device --- */
 718
 719 int dma_async_device_register(struct dma_device *device);
 720 void dma_async_device_unregister(struct dma_device *device);
 721 void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
 722 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
 723 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
 724 struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
 725 void dma_release_channel(struct dma_chan *chan);
 726
 727 /* --- Helper iov-locking functions --- */
 728
 729 struct dma_page_list {
 730         char __user *base_address;
 731         int nr_pages;
 732         struct page **pages;
 733 };
 734
 735 struct dma_pinned_list {
 736         int nr_iovecs;
 737         struct dma_page_list page_list[0];
 738 };
 739
 740 struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
 741 void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
 742
 743 dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
 744         struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
 745 dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
 746         struct dma_pinned_list *pinned_list, struct page *page,
 747         unsigned int offset, size_t len);
 748
 749 #endif /* DMAENGINE_H */