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ath5k: fix values for bus error bits in ISR2
[linux-2.6/next.git] / drivers / media / video / cx23885 / cx23885-dvb.c
blob48a975134ac5fba0c3d2ab05a85ca0d035a3eb80
1 /*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/device.h>
25 #include <linux/fs.h>
26 #include <linux/kthread.h>
27 #include <linux/file.h>
28 #include <linux/suspend.h>
29
30 #include "cx23885.h"
31 #include <media/v4l2-common.h>
32
33 #include "dvb_ca_en50221.h"
34 #include "s5h1409.h"
35 #include "s5h1411.h"
36 #include "mt2131.h"
37 #include "tda8290.h"
38 #include "tda18271.h"
39 #include "lgdt330x.h"
40 #include "xc5000.h"
41 #include "tda10048.h"
42 #include "tuner-xc2028.h"
43 #include "tuner-simple.h"
44 #include "dib7000p.h"
45 #include "dibx000_common.h"
46 #include "zl10353.h"
47 #include "stv0900.h"
48 #include "stv0900_reg.h"
49 #include "stv6110.h"
50 #include "lnbh24.h"
51 #include "cx24116.h"
52 #include "cimax2.h"
53 #include "lgs8gxx.h"
54 #include "netup-eeprom.h"
55 #include "netup-init.h"
56 #include "lgdt3305.h"
57
58 static unsigned int debug;
59
60 #define dprintk(level, fmt, arg...)\
61 do { if (debug >= level)\
62 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
63 } while (0)
64
65 /* ------------------------------------------------------------------ */
66
67 static unsigned int alt_tuner;
68 module_param(alt_tuner, int, 0644);
69 MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
70
71 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
72
73 /* ------------------------------------------------------------------ */
74
75 static int dvb_buf_setup(struct videobuf_queue *q,
76 unsigned int *count, unsigned int *size)
77 {
78 struct cx23885_tsport *port = q->priv_data;
79
80 port->ts_packet_size = 188 * 4;
81 port->ts_packet_count = 32;
82
83 *size = port->ts_packet_size * port->ts_packet_count;
84 *count = 32;
85 return 0;
86 }
87
88 static int dvb_buf_prepare(struct videobuf_queue *q,
89 struct videobuf_buffer *vb, enum v4l2_field field)
90 {
91 struct cx23885_tsport *port = q->priv_data;
92 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
93 }
94
95 static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
96 {
97 struct cx23885_tsport *port = q->priv_data;
98 cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
99 }
100
101 static void dvb_buf_release(struct videobuf_queue *q,
102 struct videobuf_buffer *vb)
103 {
104 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
105 }
106
107 static struct videobuf_queue_ops dvb_qops = {
108 .buf_setup = dvb_buf_setup,
109 .buf_prepare = dvb_buf_prepare,
110 .buf_queue = dvb_buf_queue,
111 .buf_release = dvb_buf_release,
112 };
113
114 static struct s5h1409_config hauppauge_generic_config = {
115 .demod_address = 0x32 >> 1,
116 .output_mode = S5H1409_SERIAL_OUTPUT,
117 .gpio = S5H1409_GPIO_ON,
118 .qam_if = 44000,
119 .inversion = S5H1409_INVERSION_OFF,
120 .status_mode = S5H1409_DEMODLOCKING,
121 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
122 };
123
124 static struct tda10048_config hauppauge_hvr1200_config = {
125 .demod_address = 0x10 >> 1,
126 .output_mode = TDA10048_SERIAL_OUTPUT,
127 .fwbulkwritelen = TDA10048_BULKWRITE_200,
128 .inversion = TDA10048_INVERSION_ON,
129 .dtv6_if_freq_khz = TDA10048_IF_3300,
130 .dtv7_if_freq_khz = TDA10048_IF_3800,
131 .dtv8_if_freq_khz = TDA10048_IF_4300,
132 .clk_freq_khz = TDA10048_CLK_16000,
133 };
134
135 static struct tda10048_config hauppauge_hvr1210_config = {
136 .demod_address = 0x10 >> 1,
137 .output_mode = TDA10048_SERIAL_OUTPUT,
138 .fwbulkwritelen = TDA10048_BULKWRITE_200,
139 .inversion = TDA10048_INVERSION_ON,
140 .dtv6_if_freq_khz = TDA10048_IF_3300,
141 .dtv7_if_freq_khz = TDA10048_IF_3500,
142 .dtv8_if_freq_khz = TDA10048_IF_4000,
143 .clk_freq_khz = TDA10048_CLK_16000,
144 };
145
146 static struct s5h1409_config hauppauge_ezqam_config = {
147 .demod_address = 0x32 >> 1,
148 .output_mode = S5H1409_SERIAL_OUTPUT,
149 .gpio = S5H1409_GPIO_OFF,
150 .qam_if = 4000,
151 .inversion = S5H1409_INVERSION_ON,
152 .status_mode = S5H1409_DEMODLOCKING,
153 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
154 };
155
156 static struct s5h1409_config hauppauge_hvr1800lp_config = {
157 .demod_address = 0x32 >> 1,
158 .output_mode = S5H1409_SERIAL_OUTPUT,
159 .gpio = S5H1409_GPIO_OFF,
160 .qam_if = 44000,
161 .inversion = S5H1409_INVERSION_OFF,
162 .status_mode = S5H1409_DEMODLOCKING,
163 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
164 };
165
166 static struct s5h1409_config hauppauge_hvr1500_config = {
167 .demod_address = 0x32 >> 1,
168 .output_mode = S5H1409_SERIAL_OUTPUT,
169 .gpio = S5H1409_GPIO_OFF,
170 .inversion = S5H1409_INVERSION_OFF,
171 .status_mode = S5H1409_DEMODLOCKING,
172 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
173 };
174
175 static struct mt2131_config hauppauge_generic_tunerconfig = {
176 0x61
177 };
178
179 static struct lgdt330x_config fusionhdtv_5_express = {
180 .demod_address = 0x0e,
181 .demod_chip = LGDT3303,
182 .serial_mpeg = 0x40,
183 };
184
185 static struct s5h1409_config hauppauge_hvr1500q_config = {
186 .demod_address = 0x32 >> 1,
187 .output_mode = S5H1409_SERIAL_OUTPUT,
188 .gpio = S5H1409_GPIO_ON,
189 .qam_if = 44000,
190 .inversion = S5H1409_INVERSION_OFF,
191 .status_mode = S5H1409_DEMODLOCKING,
192 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
193 };
194
195 static struct s5h1409_config dvico_s5h1409_config = {
196 .demod_address = 0x32 >> 1,
197 .output_mode = S5H1409_SERIAL_OUTPUT,
198 .gpio = S5H1409_GPIO_ON,
199 .qam_if = 44000,
200 .inversion = S5H1409_INVERSION_OFF,
201 .status_mode = S5H1409_DEMODLOCKING,
202 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
203 };
204
205 static struct s5h1411_config dvico_s5h1411_config = {
206 .output_mode = S5H1411_SERIAL_OUTPUT,
207 .gpio = S5H1411_GPIO_ON,
208 .qam_if = S5H1411_IF_44000,
209 .vsb_if = S5H1411_IF_44000,
210 .inversion = S5H1411_INVERSION_OFF,
211 .status_mode = S5H1411_DEMODLOCKING,
212 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
213 };
214
215 static struct s5h1411_config hcw_s5h1411_config = {
216 .output_mode = S5H1411_SERIAL_OUTPUT,
217 .gpio = S5H1411_GPIO_OFF,
218 .vsb_if = S5H1411_IF_44000,
219 .qam_if = S5H1411_IF_4000,
220 .inversion = S5H1411_INVERSION_ON,
221 .status_mode = S5H1411_DEMODLOCKING,
222 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
223 };
224
225 static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
226 .i2c_address = 0x61,
227 .if_khz = 5380,
228 };
229
230 static struct xc5000_config dvico_xc5000_tunerconfig = {
231 .i2c_address = 0x64,
232 .if_khz = 5380,
233 };
234
235 static struct tda829x_config tda829x_no_probe = {
236 .probe_tuner = TDA829X_DONT_PROBE,
237 };
238
239 static struct tda18271_std_map hauppauge_tda18271_std_map = {
240 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
241 .if_lvl = 6, .rfagc_top = 0x37 },
242 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
243 .if_lvl = 6, .rfagc_top = 0x37 },
244 };
245
246 static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
247 .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
248 .if_lvl = 1, .rfagc_top = 0x37, },
249 .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
250 .if_lvl = 1, .rfagc_top = 0x37, },
251 .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
252 .if_lvl = 1, .rfagc_top = 0x37, },
253 };
254
255 static struct tda18271_config hauppauge_tda18271_config = {
256 .std_map = &hauppauge_tda18271_std_map,
257 .gate = TDA18271_GATE_ANALOG,
258 };
259
260 static struct tda18271_config hauppauge_hvr1200_tuner_config = {
261 .std_map = &hauppauge_hvr1200_tda18271_std_map,
262 .gate = TDA18271_GATE_ANALOG,
263 };
264
265 static struct tda18271_config hauppauge_hvr1210_tuner_config = {
266 .gate = TDA18271_GATE_DIGITAL,
267 };
268
269 static struct tda18271_std_map hauppauge_hvr127x_std_map = {
270 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
271 .if_lvl = 1, .rfagc_top = 0x58 },
272 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
273 .if_lvl = 1, .rfagc_top = 0x58 },
274 };
275
276 static struct tda18271_config hauppauge_hvr127x_config = {
277 .std_map = &hauppauge_hvr127x_std_map,
278 };
279
280 static struct lgdt3305_config hauppauge_lgdt3305_config = {
281 .i2c_addr = 0x0e,
282 .mpeg_mode = LGDT3305_MPEG_SERIAL,
283 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
284 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
285 .deny_i2c_rptr = 1,
286 .spectral_inversion = 1,
287 .qam_if_khz = 4000,
288 .vsb_if_khz = 3250,
289 };
290
291 static struct dibx000_agc_config xc3028_agc_config = {
292 BAND_VHF | BAND_UHF, /* band_caps */
293
294 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
295 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
296 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
297 * P_agc_nb_est=2, P_agc_write=0
298 */
299 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
300 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
301
302 712, /* inv_gain */
303 21, /* time_stabiliz */
304
305 0, /* alpha_level */
306 118, /* thlock */
307
308 0, /* wbd_inv */
309 2867, /* wbd_ref */
310 0, /* wbd_sel */
311 2, /* wbd_alpha */
312
313 0, /* agc1_max */
314 0, /* agc1_min */
315 39718, /* agc2_max */
316 9930, /* agc2_min */
317 0, /* agc1_pt1 */
318 0, /* agc1_pt2 */
319 0, /* agc1_pt3 */
320 0, /* agc1_slope1 */
321 0, /* agc1_slope2 */
322 0, /* agc2_pt1 */
323 128, /* agc2_pt2 */
324 29, /* agc2_slope1 */
325 29, /* agc2_slope2 */
326
327 17, /* alpha_mant */
328 27, /* alpha_exp */
329 23, /* beta_mant */
330 51, /* beta_exp */
331
332 1, /* perform_agc_softsplit */
333 };
334
335 /* PLL Configuration for COFDM BW_MHz = 8.000000
336 * With external clock = 30.000000 */
337 static struct dibx000_bandwidth_config xc3028_bw_config = {
338 60000, /* internal */
339 30000, /* sampling */
340 1, /* pll_cfg: prediv */
341 8, /* pll_cfg: ratio */
342 3, /* pll_cfg: range */
343 1, /* pll_cfg: reset */
344 0, /* pll_cfg: bypass */
345 0, /* misc: refdiv */
346 0, /* misc: bypclk_div */
347 1, /* misc: IO_CLK_en_core */
348 1, /* misc: ADClkSrc */
349 0, /* misc: modulo */
350 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
351 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
352 20452225, /* timf */
353 30000000 /* xtal_hz */
354 };
355
356 static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
357 .output_mpeg2_in_188_bytes = 1,
358 .hostbus_diversity = 1,
359 .tuner_is_baseband = 0,
360 .update_lna = NULL,
361
362 .agc_config_count = 1,
363 .agc = &xc3028_agc_config,
364 .bw = &xc3028_bw_config,
365
366 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
367 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
368 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
369
370 .pwm_freq_div = 0,
371 .agc_control = NULL,
372 .spur_protect = 0,
373
374 .output_mode = OUTMODE_MPEG2_SERIAL,
375 };
376
377 static struct zl10353_config dvico_fusionhdtv_xc3028 = {
378 .demod_address = 0x0f,
379 .if2 = 45600,
380 .no_tuner = 1,
381 .disable_i2c_gate_ctrl = 1,
382 };
383
384 static struct stv0900_reg stv0900_ts_regs[] = {
385 { R0900_TSGENERAL, 0x00 },
386 { R0900_P1_TSSPEED, 0x40 },
387 { R0900_P2_TSSPEED, 0x40 },
388 { R0900_P1_TSCFGM, 0xc0 },
389 { R0900_P2_TSCFGM, 0xc0 },
390 { R0900_P1_TSCFGH, 0xe0 },
391 { R0900_P2_TSCFGH, 0xe0 },
392 { R0900_P1_TSCFGL, 0x20 },
393 { R0900_P2_TSCFGL, 0x20 },
394 { 0xffff, 0xff }, /* terminate */
395 };
396
397 static struct stv0900_config netup_stv0900_config = {
398 .demod_address = 0x68,
399 .xtal = 27000000,
400 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
401 .diseqc_mode = 2,/* 2/3 PWM */
402 .ts_config_regs = stv0900_ts_regs,
403 .tun1_maddress = 0,/* 0x60 */
404 .tun2_maddress = 3,/* 0x63 */
405 .tun1_adc = 1,/* 1 Vpp */
406 .tun2_adc = 1,/* 1 Vpp */
407 };
408
409 static struct stv6110_config netup_stv6110_tunerconfig_a = {
410 .i2c_address = 0x60,
411 .mclk = 27000000,
412 .iq_wiring = 0,
413 };
414
415 static struct stv6110_config netup_stv6110_tunerconfig_b = {
416 .i2c_address = 0x63,
417 .mclk = 27000000,
418 .iq_wiring = 1,
419 };
420
421 static int tbs_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
422 {
423 struct cx23885_tsport *port = fe->dvb->priv;
424 struct cx23885_dev *dev = port->dev;
425
426 if (voltage == SEC_VOLTAGE_18)
427 cx_write(MC417_RWD, 0x00001e00);/* GPIO-13 high */
428 else if (voltage == SEC_VOLTAGE_13)
429 cx_write(MC417_RWD, 0x00001a00);/* GPIO-13 low */
430 else
431 cx_write(MC417_RWD, 0x00001800);/* GPIO-12 low */
432 return 0;
433 }
434
435 static struct cx24116_config tbs_cx24116_config = {
436 .demod_address = 0x05,
437 };
438
439 static struct cx24116_config tevii_cx24116_config = {
440 .demod_address = 0x55,
441 };
442
443 static struct cx24116_config dvbworld_cx24116_config = {
444 .demod_address = 0x05,
445 };
446
447 static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
448 .prod = LGS8GXX_PROD_LGS8GL5,
449 .demod_address = 0x19,
450 .serial_ts = 0,
451 .ts_clk_pol = 1,
452 .ts_clk_gated = 1,
453 .if_clk_freq = 30400, /* 30.4 MHz */
454 .if_freq = 5380, /* 5.38 MHz */
455 .if_neg_center = 1,
456 .ext_adc = 0,
457 .adc_signed = 0,
458 .if_neg_edge = 0,
459 };
460
461 static struct xc5000_config mygica_x8506_xc5000_config = {
462 .i2c_address = 0x61,
463 .if_khz = 5380,
464 };
465
466 static int dvb_register(struct cx23885_tsport *port)
467 {
468 struct cx23885_dev *dev = port->dev;
469 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
470 struct videobuf_dvb_frontend *fe0;
471 int ret;
472
473 /* Get the first frontend */
474 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
475 if (!fe0)
476 return -EINVAL;
477
478 /* init struct videobuf_dvb */
479 fe0->dvb.name = dev->name;
480
481 /* init frontend */
482 switch (dev->board) {
483 case CX23885_BOARD_HAUPPAUGE_HVR1250:
484 i2c_bus = &dev->i2c_bus[0];
485 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
486 &hauppauge_generic_config,
487 &i2c_bus->i2c_adap);
488 if (fe0->dvb.frontend != NULL) {
489 dvb_attach(mt2131_attach, fe0->dvb.frontend,
490 &i2c_bus->i2c_adap,
491 &hauppauge_generic_tunerconfig, 0);
492 }
493 break;
494 case CX23885_BOARD_HAUPPAUGE_HVR1270:
495 case CX23885_BOARD_HAUPPAUGE_HVR1275:
496 i2c_bus = &dev->i2c_bus[0];
497 fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
498 &hauppauge_lgdt3305_config,
499 &i2c_bus->i2c_adap);
500 if (fe0->dvb.frontend != NULL) {
501 dvb_attach(tda18271_attach, fe0->dvb.frontend,
502 0x60, &dev->i2c_bus[1].i2c_adap,
503 &hauppauge_hvr127x_config);
504 }
505 break;
506 case CX23885_BOARD_HAUPPAUGE_HVR1255:
507 i2c_bus = &dev->i2c_bus[0];
508 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
509 &hcw_s5h1411_config,
510 &i2c_bus->i2c_adap);
511 if (fe0->dvb.frontend != NULL) {
512 dvb_attach(tda18271_attach, fe0->dvb.frontend,
513 0x60, &dev->i2c_bus[1].i2c_adap,
514 &hauppauge_tda18271_config);
515 }
516 break;
517 case CX23885_BOARD_HAUPPAUGE_HVR1800:
518 i2c_bus = &dev->i2c_bus[0];
519 switch (alt_tuner) {
520 case 1:
521 fe0->dvb.frontend =
522 dvb_attach(s5h1409_attach,
523 &hauppauge_ezqam_config,
524 &i2c_bus->i2c_adap);
525 if (fe0->dvb.frontend != NULL) {
526 dvb_attach(tda829x_attach, fe0->dvb.frontend,
527 &dev->i2c_bus[1].i2c_adap, 0x42,
528 &tda829x_no_probe);
529 dvb_attach(tda18271_attach, fe0->dvb.frontend,
530 0x60, &dev->i2c_bus[1].i2c_adap,
531 &hauppauge_tda18271_config);
532 }
533 break;
534 case 0:
535 default:
536 fe0->dvb.frontend =
537 dvb_attach(s5h1409_attach,
538 &hauppauge_generic_config,
539 &i2c_bus->i2c_adap);
540 if (fe0->dvb.frontend != NULL)
541 dvb_attach(mt2131_attach, fe0->dvb.frontend,
542 &i2c_bus->i2c_adap,
543 &hauppauge_generic_tunerconfig, 0);
544 break;
545 }
546 break;
547 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
548 i2c_bus = &dev->i2c_bus[0];
549 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
550 &hauppauge_hvr1800lp_config,
551 &i2c_bus->i2c_adap);
552 if (fe0->dvb.frontend != NULL) {
553 dvb_attach(mt2131_attach, fe0->dvb.frontend,
554 &i2c_bus->i2c_adap,
555 &hauppauge_generic_tunerconfig, 0);
556 }
557 break;
558 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
559 i2c_bus = &dev->i2c_bus[0];
560 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
561 &fusionhdtv_5_express,
562 &i2c_bus->i2c_adap);
563 if (fe0->dvb.frontend != NULL) {
564 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
565 &i2c_bus->i2c_adap, 0x61,
566 TUNER_LG_TDVS_H06XF);
567 }
568 break;
569 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
570 i2c_bus = &dev->i2c_bus[1];
571 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
572 &hauppauge_hvr1500q_config,
573 &dev->i2c_bus[0].i2c_adap);
574 if (fe0->dvb.frontend != NULL)
575 dvb_attach(xc5000_attach, fe0->dvb.frontend,
576 &i2c_bus->i2c_adap,
577 &hauppauge_hvr1500q_tunerconfig);
578 break;
579 case CX23885_BOARD_HAUPPAUGE_HVR1500:
580 i2c_bus = &dev->i2c_bus[1];
581 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
582 &hauppauge_hvr1500_config,
583 &dev->i2c_bus[0].i2c_adap);
584 if (fe0->dvb.frontend != NULL) {
585 struct dvb_frontend *fe;
586 struct xc2028_config cfg = {
587 .i2c_adap = &i2c_bus->i2c_adap,
588 .i2c_addr = 0x61,
589 };
590 static struct xc2028_ctrl ctl = {
591 .fname = XC2028_DEFAULT_FIRMWARE,
592 .max_len = 64,
593 .demod = XC3028_FE_OREN538,
594 };
595
596 fe = dvb_attach(xc2028_attach,
597 fe0->dvb.frontend, &cfg);
598 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
599 fe->ops.tuner_ops.set_config(fe, &ctl);
600 }
601 break;
602 case CX23885_BOARD_HAUPPAUGE_HVR1200:
603 case CX23885_BOARD_HAUPPAUGE_HVR1700:
604 i2c_bus = &dev->i2c_bus[0];
605 fe0->dvb.frontend = dvb_attach(tda10048_attach,
606 &hauppauge_hvr1200_config,
607 &i2c_bus->i2c_adap);
608 if (fe0->dvb.frontend != NULL) {
609 dvb_attach(tda829x_attach, fe0->dvb.frontend,
610 &dev->i2c_bus[1].i2c_adap, 0x42,
611 &tda829x_no_probe);
612 dvb_attach(tda18271_attach, fe0->dvb.frontend,
613 0x60, &dev->i2c_bus[1].i2c_adap,
614 &hauppauge_hvr1200_tuner_config);
615 }
616 break;
617 case CX23885_BOARD_HAUPPAUGE_HVR1210:
618 i2c_bus = &dev->i2c_bus[0];
619 fe0->dvb.frontend = dvb_attach(tda10048_attach,
620 &hauppauge_hvr1210_config,
621 &i2c_bus->i2c_adap);
622 if (fe0->dvb.frontend != NULL) {
623 dvb_attach(tda18271_attach, fe0->dvb.frontend,
624 0x60, &dev->i2c_bus[1].i2c_adap,
625 &hauppauge_hvr1210_tuner_config);
626 }
627 break;
628 case CX23885_BOARD_HAUPPAUGE_HVR1400:
629 i2c_bus = &dev->i2c_bus[0];
630 fe0->dvb.frontend = dvb_attach(dib7000p_attach,
631 &i2c_bus->i2c_adap,
632 0x12, &hauppauge_hvr1400_dib7000_config);
633 if (fe0->dvb.frontend != NULL) {
634 struct dvb_frontend *fe;
635 struct xc2028_config cfg = {
636 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
637 .i2c_addr = 0x64,
638 };
639 static struct xc2028_ctrl ctl = {
640 .fname = XC3028L_DEFAULT_FIRMWARE,
641 .max_len = 64,
642 .demod = 5000,
643 /* This is true for all demods with
644 v36 firmware? */
645 .type = XC2028_D2633,
646 };
647
648 fe = dvb_attach(xc2028_attach,
649 fe0->dvb.frontend, &cfg);
650 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
651 fe->ops.tuner_ops.set_config(fe, &ctl);
652 }
653 break;
654 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
655 i2c_bus = &dev->i2c_bus[port->nr - 1];
656
657 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
658 &dvico_s5h1409_config,
659 &i2c_bus->i2c_adap);
660 if (fe0->dvb.frontend == NULL)
661 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
662 &dvico_s5h1411_config,
663 &i2c_bus->i2c_adap);
664 if (fe0->dvb.frontend != NULL)
665 dvb_attach(xc5000_attach, fe0->dvb.frontend,
666 &i2c_bus->i2c_adap,
667 &dvico_xc5000_tunerconfig);
668 break;
669 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
670 i2c_bus = &dev->i2c_bus[port->nr - 1];
671
672 fe0->dvb.frontend = dvb_attach(zl10353_attach,
673 &dvico_fusionhdtv_xc3028,
674 &i2c_bus->i2c_adap);
675 if (fe0->dvb.frontend != NULL) {
676 struct dvb_frontend *fe;
677 struct xc2028_config cfg = {
678 .i2c_adap = &i2c_bus->i2c_adap,
679 .i2c_addr = 0x61,
680 };
681 static struct xc2028_ctrl ctl = {
682 .fname = XC2028_DEFAULT_FIRMWARE,
683 .max_len = 64,
684 .demod = XC3028_FE_ZARLINK456,
685 };
686
687 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
688 &cfg);
689 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
690 fe->ops.tuner_ops.set_config(fe, &ctl);
691 }
692 break;
693 }
694 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
695 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
696 i2c_bus = &dev->i2c_bus[0];
697
698 fe0->dvb.frontend = dvb_attach(zl10353_attach,
699 &dvico_fusionhdtv_xc3028,
700 &i2c_bus->i2c_adap);
701 if (fe0->dvb.frontend != NULL) {
702 struct dvb_frontend *fe;
703 struct xc2028_config cfg = {
704 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
705 .i2c_addr = 0x61,
706 };
707 static struct xc2028_ctrl ctl = {
708 .fname = XC2028_DEFAULT_FIRMWARE,
709 .max_len = 64,
710 .demod = XC3028_FE_ZARLINK456,
711 };
712
713 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
714 &cfg);
715 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
716 fe->ops.tuner_ops.set_config(fe, &ctl);
717 }
718 break;
719 case CX23885_BOARD_TBS_6920:
720 i2c_bus = &dev->i2c_bus[0];
721
722 fe0->dvb.frontend = dvb_attach(cx24116_attach,
723 &tbs_cx24116_config,
724 &i2c_bus->i2c_adap);
725 if (fe0->dvb.frontend != NULL)
726 fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
727
728 break;
729 case CX23885_BOARD_TEVII_S470:
730 i2c_bus = &dev->i2c_bus[1];
731
732 fe0->dvb.frontend = dvb_attach(cx24116_attach,
733 &tevii_cx24116_config,
734 &i2c_bus->i2c_adap);
735 if (fe0->dvb.frontend != NULL)
736 fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
737
738 break;
739 case CX23885_BOARD_DVBWORLD_2005:
740 i2c_bus = &dev->i2c_bus[1];
741
742 fe0->dvb.frontend = dvb_attach(cx24116_attach,
743 &dvbworld_cx24116_config,
744 &i2c_bus->i2c_adap);
745 break;
746 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
747 i2c_bus = &dev->i2c_bus[0];
748 switch (port->nr) {
749 /* port B */
750 case 1:
751 fe0->dvb.frontend = dvb_attach(stv0900_attach,
752 &netup_stv0900_config,
753 &i2c_bus->i2c_adap, 0);
754 if (fe0->dvb.frontend != NULL) {
755 if (dvb_attach(stv6110_attach,
756 fe0->dvb.frontend,
757 &netup_stv6110_tunerconfig_a,
758 &i2c_bus->i2c_adap)) {
759 if (!dvb_attach(lnbh24_attach,
760 fe0->dvb.frontend,
761 &i2c_bus->i2c_adap,
762 LNBH24_PCL,
763 LNBH24_TTX, 0x09))
764 printk(KERN_ERR
765 "No LNBH24 found!\n");
766
767 }
768 }
769 break;
770 /* port C */
771 case 2:
772 fe0->dvb.frontend = dvb_attach(stv0900_attach,
773 &netup_stv0900_config,
774 &i2c_bus->i2c_adap, 1);
775 if (fe0->dvb.frontend != NULL) {
776 if (dvb_attach(stv6110_attach,
777 fe0->dvb.frontend,
778 &netup_stv6110_tunerconfig_b,
779 &i2c_bus->i2c_adap)) {
780 if (!dvb_attach(lnbh24_attach,
781 fe0->dvb.frontend,
782 &i2c_bus->i2c_adap,
783 LNBH24_PCL,
784 LNBH24_TTX, 0x0a))
785 printk(KERN_ERR
786 "No LNBH24 found!\n");
787
788 }
789 }
790 break;
791 }
792 break;
793 case CX23885_BOARD_MYGICA_X8506:
794 i2c_bus = &dev->i2c_bus[0];
795 i2c_bus2 = &dev->i2c_bus[1];
796 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
797 &mygica_x8506_lgs8gl5_config,
798 &i2c_bus->i2c_adap);
799 if (fe0->dvb.frontend != NULL) {
800 dvb_attach(xc5000_attach,
801 fe0->dvb.frontend,
802 &i2c_bus2->i2c_adap,
803 &mygica_x8506_xc5000_config);
804 }
805 break;
806 default:
807 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
808 " isn't supported yet\n",
809 dev->name);
810 break;
811 }
812 if (NULL == fe0->dvb.frontend) {
813 printk(KERN_ERR "%s: frontend initialization failed\n",
814 dev->name);
815 return -1;
816 }
817 /* define general-purpose callback pointer */
818 fe0->dvb.frontend->callback = cx23885_tuner_callback;
819
820 /* Put the analog decoder in standby to keep it quiet */
821 call_all(dev, tuner, s_standby);
822
823 if (fe0->dvb.frontend->ops.analog_ops.standby)
824 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
825
826 /* register everything */
827 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
828 &dev->pci->dev, adapter_nr, 0);
829
830 /* init CI & MAC */
831 switch (dev->board) {
832 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
833 static struct netup_card_info cinfo;
834
835 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
836 memcpy(port->frontends.adapter.proposed_mac,
837 cinfo.port[port->nr - 1].mac, 6);
838 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC="
839 "%02X:%02X:%02X:%02X:%02X:%02X\n",
840 port->nr,
841 port->frontends.adapter.proposed_mac[0],
842 port->frontends.adapter.proposed_mac[1],
843 port->frontends.adapter.proposed_mac[2],
844 port->frontends.adapter.proposed_mac[3],
845 port->frontends.adapter.proposed_mac[4],
846 port->frontends.adapter.proposed_mac[5]);
847
848 netup_ci_init(port);
849 break;
850 }
851 }
852
853 return ret;
854 }
855
856 int cx23885_dvb_register(struct cx23885_tsport *port)
857 {
858
859 struct videobuf_dvb_frontend *fe0;
860 struct cx23885_dev *dev = port->dev;
861 int err, i;
862
863 /* Here we need to allocate the correct number of frontends,
864 * as reflected in the cards struct. The reality is that currrently
865 * no cx23885 boards support this - yet. But, if we don't modify this
866 * code then the second frontend would never be allocated (later)
867 * and fail with error before the attach in dvb_register().
868 * Without these changes we risk an OOPS later. The changes here
869 * are for safety, and should provide a good foundation for the
870 * future addition of any multi-frontend cx23885 based boards.
871 */
872 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
873 port->num_frontends);
874
875 for (i = 1; i <= port->num_frontends; i++) {
876 if (videobuf_dvb_alloc_frontend(
877 &port->frontends, i) == NULL) {
878 printk(KERN_ERR "%s() failed to alloc\n", __func__);
879 return -ENOMEM;
880 }
881
882 fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
883 if (!fe0)
884 err = -EINVAL;
885
886 dprintk(1, "%s\n", __func__);
887 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
888 dev->board,
889 dev->name,
890 dev->pci_bus,
891 dev->pci_slot);
892
893 err = -ENODEV;
894
895 /* dvb stuff */
896 /* We have to init the queue for each frontend on a port. */
897 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
898 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
899 &dev->pci->dev, &port->slock,
900 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
901 sizeof(struct cx23885_buffer), port);
902 }
903 err = dvb_register(port);
904 if (err != 0)
905 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
906 __func__, err);
907
908 return err;
909 }
910
911 int cx23885_dvb_unregister(struct cx23885_tsport *port)
912 {
913 struct videobuf_dvb_frontend *fe0;
914
915 /* FIXME: in an error condition where the we have
916 * an expected number of frontends (attach problem)
917 * then this might not clean up correctly, if 1
918 * is invalid.
919 * This comment only applies to future boards IF they
920 * implement MFE support.
921 */
922 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
923 if (fe0->dvb.frontend)
924 videobuf_dvb_unregister_bus(&port->frontends);
925
926 switch (port->dev->board) {
927 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
928 netup_ci_exit(port);
929 break;
930 }
931
932 return 0;
933 }
934
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