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ath5k: fix values for bus error bits in ISR2
[linux-2.6/next.git] / drivers / net / atl1e / atl1e_main.c
blob9fc6d6d9060ec7bfe8293b08c02d10e90d9228c9
1 /*
2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22 #include "atl1e.h"
23
24 #define DRV_VERSION "1.0.0.7-NAPI"
25
26 char atl1e_driver_name[] = "ATL1E";
27 char atl1e_driver_version[] = DRV_VERSION;
28 #define PCI_DEVICE_ID_ATTANSIC_L1E 0x1026
29 /*
30 * atl1e_pci_tbl - PCI Device ID Table
31 *
32 * Wildcard entries (PCI_ANY_ID) should come last
33 * Last entry must be all 0s
34 *
35 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
36 * Class, Class Mask, private data (not used) }
37 */
38 static struct pci_device_id atl1e_pci_tbl[] = {
39 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1E)},
40 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, 0x1066)},
41 /* required last entry */
42 { 0 }
43 };
44 MODULE_DEVICE_TABLE(pci, atl1e_pci_tbl);
45
46 MODULE_AUTHOR("Atheros Corporation, <xiong.huang@atheros.com>, Jie Yang <jie.yang@atheros.com>");
47 MODULE_DESCRIPTION("Atheros 1000M Ethernet Network Driver");
48 MODULE_LICENSE("GPL");
49 MODULE_VERSION(DRV_VERSION);
50
51 static void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter);
52
53 static const u16
54 atl1e_rx_page_vld_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
55 {
56 {REG_HOST_RXF0_PAGE0_VLD, REG_HOST_RXF0_PAGE1_VLD},
57 {REG_HOST_RXF1_PAGE0_VLD, REG_HOST_RXF1_PAGE1_VLD},
58 {REG_HOST_RXF2_PAGE0_VLD, REG_HOST_RXF2_PAGE1_VLD},
59 {REG_HOST_RXF3_PAGE0_VLD, REG_HOST_RXF3_PAGE1_VLD}
60 };
61
62 static const u16 atl1e_rx_page_hi_addr_regs[AT_MAX_RECEIVE_QUEUE] =
63 {
64 REG_RXF0_BASE_ADDR_HI,
65 REG_RXF1_BASE_ADDR_HI,
66 REG_RXF2_BASE_ADDR_HI,
67 REG_RXF3_BASE_ADDR_HI
68 };
69
70 static const u16
71 atl1e_rx_page_lo_addr_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
72 {
73 {REG_HOST_RXF0_PAGE0_LO, REG_HOST_RXF0_PAGE1_LO},
74 {REG_HOST_RXF1_PAGE0_LO, REG_HOST_RXF1_PAGE1_LO},
75 {REG_HOST_RXF2_PAGE0_LO, REG_HOST_RXF2_PAGE1_LO},
76 {REG_HOST_RXF3_PAGE0_LO, REG_HOST_RXF3_PAGE1_LO}
77 };
78
79 static const u16
80 atl1e_rx_page_write_offset_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
81 {
82 {REG_HOST_RXF0_MB0_LO, REG_HOST_RXF0_MB1_LO},
83 {REG_HOST_RXF1_MB0_LO, REG_HOST_RXF1_MB1_LO},
84 {REG_HOST_RXF2_MB0_LO, REG_HOST_RXF2_MB1_LO},
85 {REG_HOST_RXF3_MB0_LO, REG_HOST_RXF3_MB1_LO}
86 };
87
88 static const u16 atl1e_pay_load_size[] = {
89 128, 256, 512, 1024, 2048, 4096,
90 };
91
92 /*
93 * atl1e_irq_enable - Enable default interrupt generation settings
94 * @adapter: board private structure
95 */
96 static inline void atl1e_irq_enable(struct atl1e_adapter *adapter)
97 {
98 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
99 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
100 AT_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
101 AT_WRITE_FLUSH(&adapter->hw);
102 }
103 }
104
105 /*
106 * atl1e_irq_disable - Mask off interrupt generation on the NIC
107 * @adapter: board private structure
108 */
109 static inline void atl1e_irq_disable(struct atl1e_adapter *adapter)
110 {
111 atomic_inc(&adapter->irq_sem);
112 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
113 AT_WRITE_FLUSH(&adapter->hw);
114 synchronize_irq(adapter->pdev->irq);
115 }
116
117 /*
118 * atl1e_irq_reset - reset interrupt confiure on the NIC
119 * @adapter: board private structure
120 */
121 static inline void atl1e_irq_reset(struct atl1e_adapter *adapter)
122 {
123 atomic_set(&adapter->irq_sem, 0);
124 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
125 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
126 AT_WRITE_FLUSH(&adapter->hw);
127 }
128
129 /*
130 * atl1e_phy_config - Timer Call-back
131 * @data: pointer to netdev cast into an unsigned long
132 */
133 static void atl1e_phy_config(unsigned long data)
134 {
135 struct atl1e_adapter *adapter = (struct atl1e_adapter *) data;
136 struct atl1e_hw *hw = &adapter->hw;
137 unsigned long flags;
138
139 spin_lock_irqsave(&adapter->mdio_lock, flags);
140 atl1e_restart_autoneg(hw);
141 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
142 }
143
144 void atl1e_reinit_locked(struct atl1e_adapter *adapter)
145 {
146
147 WARN_ON(in_interrupt());
148 while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
149 msleep(1);
150 atl1e_down(adapter);
151 atl1e_up(adapter);
152 clear_bit(__AT_RESETTING, &adapter->flags);
153 }
154
155 static void atl1e_reset_task(struct work_struct *work)
156 {
157 struct atl1e_adapter *adapter;
158 adapter = container_of(work, struct atl1e_adapter, reset_task);
159
160 atl1e_reinit_locked(adapter);
161 }
162
163 static int atl1e_check_link(struct atl1e_adapter *adapter)
164 {
165 struct atl1e_hw *hw = &adapter->hw;
166 struct net_device *netdev = adapter->netdev;
167 struct pci_dev *pdev = adapter->pdev;
168 int err = 0;
169 u16 speed, duplex, phy_data;
170
171 /* MII_BMSR must read twise */
172 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
173 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
174 if ((phy_data & BMSR_LSTATUS) == 0) {
175 /* link down */
176 if (netif_carrier_ok(netdev)) { /* old link state: Up */
177 u32 value;
178 /* disable rx */
179 value = AT_READ_REG(hw, REG_MAC_CTRL);
180 value &= ~MAC_CTRL_RX_EN;
181 AT_WRITE_REG(hw, REG_MAC_CTRL, value);
182 adapter->link_speed = SPEED_0;
183 netif_carrier_off(netdev);
184 netif_stop_queue(netdev);
185 }
186 } else {
187 /* Link Up */
188 err = atl1e_get_speed_and_duplex(hw, &speed, &duplex);
189 if (unlikely(err))
190 return err;
191
192 /* link result is our setting */
193 if (adapter->link_speed != speed ||
194 adapter->link_duplex != duplex) {
195 adapter->link_speed = speed;
196 adapter->link_duplex = duplex;
197 atl1e_setup_mac_ctrl(adapter);
198 dev_info(&pdev->dev,
199 "%s: %s NIC Link is Up<%d Mbps %s>\n",
200 atl1e_driver_name, netdev->name,
201 adapter->link_speed,
202 adapter->link_duplex == FULL_DUPLEX ?
203 "Full Duplex" : "Half Duplex");
204 }
205
206 if (!netif_carrier_ok(netdev)) {
207 /* Link down -> Up */
208 netif_carrier_on(netdev);
209 netif_wake_queue(netdev);
210 }
211 }
212 return 0;
213 }
214
215 /*
216 * atl1e_link_chg_task - deal with link change event Out of interrupt context
217 * @netdev: network interface device structure
218 */
219 static void atl1e_link_chg_task(struct work_struct *work)
220 {
221 struct atl1e_adapter *adapter;
222 unsigned long flags;
223
224 adapter = container_of(work, struct atl1e_adapter, link_chg_task);
225 spin_lock_irqsave(&adapter->mdio_lock, flags);
226 atl1e_check_link(adapter);
227 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
228 }
229
230 static void atl1e_link_chg_event(struct atl1e_adapter *adapter)
231 {
232 struct net_device *netdev = adapter->netdev;
233 struct pci_dev *pdev = adapter->pdev;
234 u16 phy_data = 0;
235 u16 link_up = 0;
236
237 spin_lock(&adapter->mdio_lock);
238 atl1e_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
239 atl1e_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
240 spin_unlock(&adapter->mdio_lock);
241 link_up = phy_data & BMSR_LSTATUS;
242 /* notify upper layer link down ASAP */
243 if (!link_up) {
244 if (netif_carrier_ok(netdev)) {
245 /* old link state: Up */
246 dev_info(&pdev->dev, "%s: %s NIC Link is Down\n",
247 atl1e_driver_name, netdev->name);
248 adapter->link_speed = SPEED_0;
249 netif_stop_queue(netdev);
250 }
251 }
252 schedule_work(&adapter->link_chg_task);
253 }
254
255 static void atl1e_del_timer(struct atl1e_adapter *adapter)
256 {
257 del_timer_sync(&adapter->phy_config_timer);
258 }
259
260 static void atl1e_cancel_work(struct atl1e_adapter *adapter)
261 {
262 cancel_work_sync(&adapter->reset_task);
263 cancel_work_sync(&adapter->link_chg_task);
264 }
265
266 /*
267 * atl1e_tx_timeout - Respond to a Tx Hang
268 * @netdev: network interface device structure
269 */
270 static void atl1e_tx_timeout(struct net_device *netdev)
271 {
272 struct atl1e_adapter *adapter = netdev_priv(netdev);
273
274 /* Do the reset outside of interrupt context */
275 schedule_work(&adapter->reset_task);
276 }
277
278 /*
279 * atl1e_set_multi - Multicast and Promiscuous mode set
280 * @netdev: network interface device structure
281 *
282 * The set_multi entry point is called whenever the multicast address
283 * list or the network interface flags are updated. This routine is
284 * responsible for configuring the hardware for proper multicast,
285 * promiscuous mode, and all-multi behavior.
286 */
287 static void atl1e_set_multi(struct net_device *netdev)
288 {
289 struct atl1e_adapter *adapter = netdev_priv(netdev);
290 struct atl1e_hw *hw = &adapter->hw;
291 struct dev_mc_list *mc_ptr;
292 u32 mac_ctrl_data = 0;
293 u32 hash_value;
294
295 /* Check for Promiscuous and All Multicast modes */
296 mac_ctrl_data = AT_READ_REG(hw, REG_MAC_CTRL);
297
298 if (netdev->flags & IFF_PROMISC) {
299 mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
300 } else if (netdev->flags & IFF_ALLMULTI) {
301 mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
302 mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
303 } else {
304 mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
305 }
306
307 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
308
309 /* clear the old settings from the multicast hash table */
310 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
311 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
312
313 /* comoute mc addresses' hash value ,and put it into hash table */
314 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
315 hash_value = atl1e_hash_mc_addr(hw, mc_ptr->dmi_addr);
316 atl1e_hash_set(hw, hash_value);
317 }
318 }
319
320 static void atl1e_vlan_rx_register(struct net_device *netdev,
321 struct vlan_group *grp)
322 {
323 struct atl1e_adapter *adapter = netdev_priv(netdev);
324 struct pci_dev *pdev = adapter->pdev;
325 u32 mac_ctrl_data = 0;
326
327 dev_dbg(&pdev->dev, "atl1e_vlan_rx_register\n");
328
329 atl1e_irq_disable(adapter);
330
331 adapter->vlgrp = grp;
332 mac_ctrl_data = AT_READ_REG(&adapter->hw, REG_MAC_CTRL);
333
334 if (grp) {
335 /* enable VLAN tag insert/strip */
336 mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
337 } else {
338 /* disable VLAN tag insert/strip */
339 mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
340 }
341
342 AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
343 atl1e_irq_enable(adapter);
344 }
345
346 static void atl1e_restore_vlan(struct atl1e_adapter *adapter)
347 {
348 struct pci_dev *pdev = adapter->pdev;
349
350 dev_dbg(&pdev->dev, "atl1e_restore_vlan !");
351 atl1e_vlan_rx_register(adapter->netdev, adapter->vlgrp);
352 }
353 /*
354 * atl1e_set_mac - Change the Ethernet Address of the NIC
355 * @netdev: network interface device structure
356 * @p: pointer to an address structure
357 *
358 * Returns 0 on success, negative on failure
359 */
360 static int atl1e_set_mac_addr(struct net_device *netdev, void *p)
361 {
362 struct atl1e_adapter *adapter = netdev_priv(netdev);
363 struct sockaddr *addr = p;
364
365 if (!is_valid_ether_addr(addr->sa_data))
366 return -EADDRNOTAVAIL;
367
368 if (netif_running(netdev))
369 return -EBUSY;
370
371 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
372 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
373
374 atl1e_hw_set_mac_addr(&adapter->hw);
375
376 return 0;
377 }
378
379 /*
380 * atl1e_change_mtu - Change the Maximum Transfer Unit
381 * @netdev: network interface device structure
382 * @new_mtu: new value for maximum frame size
383 *
384 * Returns 0 on success, negative on failure
385 */
386 static int atl1e_change_mtu(struct net_device *netdev, int new_mtu)
387 {
388 struct atl1e_adapter *adapter = netdev_priv(netdev);
389 int old_mtu = netdev->mtu;
390 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
391
392 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
393 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
394 dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
395 return -EINVAL;
396 }
397 /* set MTU */
398 if (old_mtu != new_mtu && netif_running(netdev)) {
399 while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
400 msleep(1);
401 netdev->mtu = new_mtu;
402 adapter->hw.max_frame_size = new_mtu;
403 adapter->hw.rx_jumbo_th = (max_frame + 7) >> 3;
404 atl1e_down(adapter);
405 atl1e_up(adapter);
406 clear_bit(__AT_RESETTING, &adapter->flags);
407 }
408 return 0;
409 }
410
411 /*
412 * caller should hold mdio_lock
413 */
414 static int atl1e_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
415 {
416 struct atl1e_adapter *adapter = netdev_priv(netdev);
417 u16 result;
418
419 atl1e_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result);
420 return result;
421 }
422
423 static void atl1e_mdio_write(struct net_device *netdev, int phy_id,
424 int reg_num, int val)
425 {
426 struct atl1e_adapter *adapter = netdev_priv(netdev);
427
428 atl1e_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val);
429 }
430
431 /*
432 * atl1e_mii_ioctl -
433 * @netdev:
434 * @ifreq:
435 * @cmd:
436 */
437 static int atl1e_mii_ioctl(struct net_device *netdev,
438 struct ifreq *ifr, int cmd)
439 {
440 struct atl1e_adapter *adapter = netdev_priv(netdev);
441 struct pci_dev *pdev = adapter->pdev;
442 struct mii_ioctl_data *data = if_mii(ifr);
443 unsigned long flags;
444 int retval = 0;
445
446 if (!netif_running(netdev))
447 return -EINVAL;
448
449 spin_lock_irqsave(&adapter->mdio_lock, flags);
450 switch (cmd) {
451 case SIOCGMIIPHY:
452 data->phy_id = 0;
453 break;
454
455 case SIOCGMIIREG:
456 if (!capable(CAP_NET_ADMIN)) {
457 retval = -EPERM;
458 goto out;
459 }
460 if (atl1e_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
461 &data->val_out)) {
462 retval = -EIO;
463 goto out;
464 }
465 break;
466
467 case SIOCSMIIREG:
468 if (!capable(CAP_NET_ADMIN)) {
469 retval = -EPERM;
470 goto out;
471 }
472 if (data->reg_num & ~(0x1F)) {
473 retval = -EFAULT;
474 goto out;
475 }
476
477 dev_dbg(&pdev->dev, "<atl1e_mii_ioctl> write %x %x",
478 data->reg_num, data->val_in);
479 if (atl1e_write_phy_reg(&adapter->hw,
480 data->reg_num, data->val_in)) {
481 retval = -EIO;
482 goto out;
483 }
484 break;
485
486 default:
487 retval = -EOPNOTSUPP;
488 break;
489 }
490 out:
491 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
492 return retval;
493
494 }
495
496 /*
497 * atl1e_ioctl -
498 * @netdev:
499 * @ifreq:
500 * @cmd:
501 */
502 static int atl1e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
503 {
504 switch (cmd) {
505 case SIOCGMIIPHY:
506 case SIOCGMIIREG:
507 case SIOCSMIIREG:
508 return atl1e_mii_ioctl(netdev, ifr, cmd);
509 default:
510 return -EOPNOTSUPP;
511 }
512 }
513
514 static void atl1e_setup_pcicmd(struct pci_dev *pdev)
515 {
516 u16 cmd;
517
518 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
519 cmd &= ~(PCI_COMMAND_INTX_DISABLE | PCI_COMMAND_IO);
520 cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
521 pci_write_config_word(pdev, PCI_COMMAND, cmd);
522
523 /*
524 * some motherboards BIOS(PXE/EFI) driver may set PME
525 * while they transfer control to OS (Windows/Linux)
526 * so we should clear this bit before NIC work normally
527 */
528 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
529 msleep(1);
530 }
531
532 /*
533 * atl1e_alloc_queues - Allocate memory for all rings
534 * @adapter: board private structure to initialize
535 *
536 */
537 static int __devinit atl1e_alloc_queues(struct atl1e_adapter *adapter)
538 {
539 return 0;
540 }
541
542 /*
543 * atl1e_sw_init - Initialize general software structures (struct atl1e_adapter)
544 * @adapter: board private structure to initialize
545 *
546 * atl1e_sw_init initializes the Adapter private data structure.
547 * Fields are initialized based on PCI device information and
548 * OS network device settings (MTU size).
549 */
550 static int __devinit atl1e_sw_init(struct atl1e_adapter *adapter)
551 {
552 struct atl1e_hw *hw = &adapter->hw;
553 struct pci_dev *pdev = adapter->pdev;
554 u32 phy_status_data = 0;
555
556 adapter->wol = 0;
557 adapter->link_speed = SPEED_0; /* hardware init */
558 adapter->link_duplex = FULL_DUPLEX;
559 adapter->num_rx_queues = 1;
560
561 /* PCI config space info */
562 hw->vendor_id = pdev->vendor;
563 hw->device_id = pdev->device;
564 hw->subsystem_vendor_id = pdev->subsystem_vendor;
565 hw->subsystem_id = pdev->subsystem_device;
566
567 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
568 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
569
570 phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
571 /* nic type */
572 if (hw->revision_id >= 0xF0) {
573 hw->nic_type = athr_l2e_revB;
574 } else {
575 if (phy_status_data & PHY_STATUS_100M)
576 hw->nic_type = athr_l1e;
577 else
578 hw->nic_type = athr_l2e_revA;
579 }
580
581 phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
582
583 if (phy_status_data & PHY_STATUS_EMI_CA)
584 hw->emi_ca = true;
585 else
586 hw->emi_ca = false;
587
588 hw->phy_configured = false;
589 hw->preamble_len = 7;
590 hw->max_frame_size = adapter->netdev->mtu;
591 hw->rx_jumbo_th = (hw->max_frame_size + ETH_HLEN +
592 VLAN_HLEN + ETH_FCS_LEN + 7) >> 3;
593
594 hw->rrs_type = atl1e_rrs_disable;
595 hw->indirect_tab = 0;
596 hw->base_cpu = 0;
597
598 /* need confirm */
599
600 hw->ict = 50000; /* 100ms */
601 hw->smb_timer = 200000; /* 200ms */
602 hw->tpd_burst = 5;
603 hw->rrd_thresh = 1;
604 hw->tpd_thresh = adapter->tx_ring.count / 2;
605 hw->rx_count_down = 4; /* 2us resolution */
606 hw->tx_count_down = hw->imt * 4 / 3;
607 hw->dmar_block = atl1e_dma_req_1024;
608 hw->dmaw_block = atl1e_dma_req_1024;
609 hw->dmar_dly_cnt = 15;
610 hw->dmaw_dly_cnt = 4;
611
612 if (atl1e_alloc_queues(adapter)) {
613 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
614 return -ENOMEM;
615 }
616
617 atomic_set(&adapter->irq_sem, 1);
618 spin_lock_init(&adapter->mdio_lock);
619 spin_lock_init(&adapter->tx_lock);
620
621 set_bit(__AT_DOWN, &adapter->flags);
622
623 return 0;
624 }
625
626 /*
627 * atl1e_clean_tx_ring - Free Tx-skb
628 * @adapter: board private structure
629 */
630 static void atl1e_clean_tx_ring(struct atl1e_adapter *adapter)
631 {
632 struct atl1e_tx_ring *tx_ring = (struct atl1e_tx_ring *)
633 &adapter->tx_ring;
634 struct atl1e_tx_buffer *tx_buffer = NULL;
635 struct pci_dev *pdev = adapter->pdev;
636 u16 index, ring_count;
637
638 if (tx_ring->desc == NULL || tx_ring->tx_buffer == NULL)
639 return;
640
641 ring_count = tx_ring->count;
642 /* first unmmap dma */
643 for (index = 0; index < ring_count; index++) {
644 tx_buffer = &tx_ring->tx_buffer[index];
645 if (tx_buffer->dma) {
646 pci_unmap_page(pdev, tx_buffer->dma,
647 tx_buffer->length, PCI_DMA_TODEVICE);
648 tx_buffer->dma = 0;
649 }
650 }
651 /* second free skb */
652 for (index = 0; index < ring_count; index++) {
653 tx_buffer = &tx_ring->tx_buffer[index];
654 if (tx_buffer->skb) {
655 dev_kfree_skb_any(tx_buffer->skb);
656 tx_buffer->skb = NULL;
657 }
658 }
659 /* Zero out Tx-buffers */
660 memset(tx_ring->desc, 0, sizeof(struct atl1e_tpd_desc) *
661 ring_count);
662 memset(tx_ring->tx_buffer, 0, sizeof(struct atl1e_tx_buffer) *
663 ring_count);
664 }
665
666 /*
667 * atl1e_clean_rx_ring - Free rx-reservation skbs
668 * @adapter: board private structure
669 */
670 static void atl1e_clean_rx_ring(struct atl1e_adapter *adapter)
671 {
672 struct atl1e_rx_ring *rx_ring =
673 (struct atl1e_rx_ring *)&adapter->rx_ring;
674 struct atl1e_rx_page_desc *rx_page_desc = rx_ring->rx_page_desc;
675 u16 i, j;
676
677
678 if (adapter->ring_vir_addr == NULL)
679 return;
680 /* Zero out the descriptor ring */
681 for (i = 0; i < adapter->num_rx_queues; i++) {
682 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
683 if (rx_page_desc[i].rx_page[j].addr != NULL) {
684 memset(rx_page_desc[i].rx_page[j].addr, 0,
685 rx_ring->real_page_size);
686 }
687 }
688 }
689 }
690
691 static void atl1e_cal_ring_size(struct atl1e_adapter *adapter, u32 *ring_size)
692 {
693 *ring_size = ((u32)(adapter->tx_ring.count *
694 sizeof(struct atl1e_tpd_desc) + 7
695 /* tx ring, qword align */
696 + adapter->rx_ring.real_page_size * AT_PAGE_NUM_PER_QUEUE *
697 adapter->num_rx_queues + 31
698 /* rx ring, 32 bytes align */
699 + (1 + AT_PAGE_NUM_PER_QUEUE * adapter->num_rx_queues) *
700 sizeof(u32) + 3));
701 /* tx, rx cmd, dword align */
702 }
703
704 static void atl1e_init_ring_resources(struct atl1e_adapter *adapter)
705 {
706 struct atl1e_tx_ring *tx_ring = NULL;
707 struct atl1e_rx_ring *rx_ring = NULL;
708
709 tx_ring = &adapter->tx_ring;
710 rx_ring = &adapter->rx_ring;
711
712 rx_ring->real_page_size = adapter->rx_ring.page_size
713 + adapter->hw.max_frame_size
714 + ETH_HLEN + VLAN_HLEN
715 + ETH_FCS_LEN;
716 rx_ring->real_page_size = roundup(rx_ring->real_page_size, 32);
717 atl1e_cal_ring_size(adapter, &adapter->ring_size);
718
719 adapter->ring_vir_addr = NULL;
720 adapter->rx_ring.desc = NULL;
721 rwlock_init(&adapter->tx_ring.tx_lock);
722
723 return;
724 }
725
726 /*
727 * Read / Write Ptr Initialize:
728 */
729 static void atl1e_init_ring_ptrs(struct atl1e_adapter *adapter)
730 {
731 struct atl1e_tx_ring *tx_ring = NULL;
732 struct atl1e_rx_ring *rx_ring = NULL;
733 struct atl1e_rx_page_desc *rx_page_desc = NULL;
734 int i, j;
735
736 tx_ring = &adapter->tx_ring;
737 rx_ring = &adapter->rx_ring;
738 rx_page_desc = rx_ring->rx_page_desc;
739
740 tx_ring->next_to_use = 0;
741 atomic_set(&tx_ring->next_to_clean, 0);
742
743 for (i = 0; i < adapter->num_rx_queues; i++) {
744 rx_page_desc[i].rx_using = 0;
745 rx_page_desc[i].rx_nxseq = 0;
746 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
747 *rx_page_desc[i].rx_page[j].write_offset_addr = 0;
748 rx_page_desc[i].rx_page[j].read_offset = 0;
749 }
750 }
751 }
752
753 /*
754 * atl1e_free_ring_resources - Free Tx / RX descriptor Resources
755 * @adapter: board private structure
756 *
757 * Free all transmit software resources
758 */
759 static void atl1e_free_ring_resources(struct atl1e_adapter *adapter)
760 {
761 struct pci_dev *pdev = adapter->pdev;
762
763 atl1e_clean_tx_ring(adapter);
764 atl1e_clean_rx_ring(adapter);
765
766 if (adapter->ring_vir_addr) {
767 pci_free_consistent(pdev, adapter->ring_size,
768 adapter->ring_vir_addr, adapter->ring_dma);
769 adapter->ring_vir_addr = NULL;
770 }
771
772 if (adapter->tx_ring.tx_buffer) {
773 kfree(adapter->tx_ring.tx_buffer);
774 adapter->tx_ring.tx_buffer = NULL;
775 }
776 }
777
778 /*
779 * atl1e_setup_mem_resources - allocate Tx / RX descriptor resources
780 * @adapter: board private structure
781 *
782 * Return 0 on success, negative on failure
783 */
784 static int atl1e_setup_ring_resources(struct atl1e_adapter *adapter)
785 {
786 struct pci_dev *pdev = adapter->pdev;
787 struct atl1e_tx_ring *tx_ring;
788 struct atl1e_rx_ring *rx_ring;
789 struct atl1e_rx_page_desc *rx_page_desc;
790 int size, i, j;
791 u32 offset = 0;
792 int err = 0;
793
794 if (adapter->ring_vir_addr != NULL)
795 return 0; /* alloced already */
796
797 tx_ring = &adapter->tx_ring;
798 rx_ring = &adapter->rx_ring;
799
800 /* real ring DMA buffer */
801
802 size = adapter->ring_size;
803 adapter->ring_vir_addr = pci_alloc_consistent(pdev,
804 adapter->ring_size, &adapter->ring_dma);
805
806 if (adapter->ring_vir_addr == NULL) {
807 dev_err(&pdev->dev, "pci_alloc_consistent failed, "
808 "size = D%d", size);
809 return -ENOMEM;
810 }
811
812 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
813
814 rx_page_desc = rx_ring->rx_page_desc;
815
816 /* Init TPD Ring */
817 tx_ring->dma = roundup(adapter->ring_dma, 8);
818 offset = tx_ring->dma - adapter->ring_dma;
819 tx_ring->desc = (struct atl1e_tpd_desc *)
820 (adapter->ring_vir_addr + offset);
821 size = sizeof(struct atl1e_tx_buffer) * (tx_ring->count);
822 tx_ring->tx_buffer = kzalloc(size, GFP_KERNEL);
823 if (tx_ring->tx_buffer == NULL) {
824 dev_err(&pdev->dev, "kzalloc failed , size = D%d", size);
825 err = -ENOMEM;
826 goto failed;
827 }
828
829 /* Init RXF-Pages */
830 offset += (sizeof(struct atl1e_tpd_desc) * tx_ring->count);
831 offset = roundup(offset, 32);
832
833 for (i = 0; i < adapter->num_rx_queues; i++) {
834 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
835 rx_page_desc[i].rx_page[j].dma =
836 adapter->ring_dma + offset;
837 rx_page_desc[i].rx_page[j].addr =
838 adapter->ring_vir_addr + offset;
839 offset += rx_ring->real_page_size;
840 }
841 }
842
843 /* Init CMB dma address */
844 tx_ring->cmb_dma = adapter->ring_dma + offset;
845 tx_ring->cmb = (u32 *)(adapter->ring_vir_addr + offset);
846 offset += sizeof(u32);
847
848 for (i = 0; i < adapter->num_rx_queues; i++) {
849 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
850 rx_page_desc[i].rx_page[j].write_offset_dma =
851 adapter->ring_dma + offset;
852 rx_page_desc[i].rx_page[j].write_offset_addr =
853 adapter->ring_vir_addr + offset;
854 offset += sizeof(u32);
855 }
856 }
857
858 if (unlikely(offset > adapter->ring_size)) {
859 dev_err(&pdev->dev, "offset(%d) > ring size(%d) !!\n",
860 offset, adapter->ring_size);
861 err = -1;
862 goto failed;
863 }
864
865 return 0;
866 failed:
867 if (adapter->ring_vir_addr != NULL) {
868 pci_free_consistent(pdev, adapter->ring_size,
869 adapter->ring_vir_addr, adapter->ring_dma);
870 adapter->ring_vir_addr = NULL;
871 }
872 return err;
873 }
874
875 static inline void atl1e_configure_des_ring(const struct atl1e_adapter *adapter)
876 {
877
878 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
879 struct atl1e_rx_ring *rx_ring =
880 (struct atl1e_rx_ring *)&adapter->rx_ring;
881 struct atl1e_tx_ring *tx_ring =
882 (struct atl1e_tx_ring *)&adapter->tx_ring;
883 struct atl1e_rx_page_desc *rx_page_desc = NULL;
884 int i, j;
885
886 AT_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
887 (u32)((adapter->ring_dma & AT_DMA_HI_ADDR_MASK) >> 32));
888 AT_WRITE_REG(hw, REG_TPD_BASE_ADDR_LO,
889 (u32)((tx_ring->dma) & AT_DMA_LO_ADDR_MASK));
890 AT_WRITE_REG(hw, REG_TPD_RING_SIZE, (u16)(tx_ring->count));
891 AT_WRITE_REG(hw, REG_HOST_TX_CMB_LO,
892 (u32)((tx_ring->cmb_dma) & AT_DMA_LO_ADDR_MASK));
893
894 rx_page_desc = rx_ring->rx_page_desc;
895 /* RXF Page Physical address / Page Length */
896 for (i = 0; i < AT_MAX_RECEIVE_QUEUE; i++) {
897 AT_WRITE_REG(hw, atl1e_rx_page_hi_addr_regs[i],
898 (u32)((adapter->ring_dma &
899 AT_DMA_HI_ADDR_MASK) >> 32));
900 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
901 u32 page_phy_addr;
902 u32 offset_phy_addr;
903
904 page_phy_addr = rx_page_desc[i].rx_page[j].dma;
905 offset_phy_addr =
906 rx_page_desc[i].rx_page[j].write_offset_dma;
907
908 AT_WRITE_REG(hw, atl1e_rx_page_lo_addr_regs[i][j],
909 page_phy_addr & AT_DMA_LO_ADDR_MASK);
910 AT_WRITE_REG(hw, atl1e_rx_page_write_offset_regs[i][j],
911 offset_phy_addr & AT_DMA_LO_ADDR_MASK);
912 AT_WRITE_REGB(hw, atl1e_rx_page_vld_regs[i][j], 1);
913 }
914 }
915 /* Page Length */
916 AT_WRITE_REG(hw, REG_HOST_RXFPAGE_SIZE, rx_ring->page_size);
917 /* Load all of base address above */
918 AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
919
920 return;
921 }
922
923 static inline void atl1e_configure_tx(struct atl1e_adapter *adapter)
924 {
925 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
926 u32 dev_ctrl_data = 0;
927 u32 max_pay_load = 0;
928 u32 jumbo_thresh = 0;
929 u32 extra_size = 0; /* Jumbo frame threshold in QWORD unit */
930
931 /* configure TXQ param */
932 if (hw->nic_type != athr_l2e_revB) {
933 extra_size = ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN;
934 if (hw->max_frame_size <= 1500) {
935 jumbo_thresh = hw->max_frame_size + extra_size;
936 } else if (hw->max_frame_size < 6*1024) {
937 jumbo_thresh =
938 (hw->max_frame_size + extra_size) * 2 / 3;
939 } else {
940 jumbo_thresh = (hw->max_frame_size + extra_size) / 2;
941 }
942 AT_WRITE_REG(hw, REG_TX_EARLY_TH, (jumbo_thresh + 7) >> 3);
943 }
944
945 dev_ctrl_data = AT_READ_REG(hw, REG_DEVICE_CTRL);
946
947 max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_PAYLOAD_SHIFT)) &
948 DEVICE_CTRL_MAX_PAYLOAD_MASK;
949
950 hw->dmaw_block = min(max_pay_load, hw->dmaw_block);
951
952 max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_RREQ_SZ_SHIFT)) &
953 DEVICE_CTRL_MAX_RREQ_SZ_MASK;
954 hw->dmar_block = min(max_pay_load, hw->dmar_block);
955
956 if (hw->nic_type != athr_l2e_revB)
957 AT_WRITE_REGW(hw, REG_TXQ_CTRL + 2,
958 atl1e_pay_load_size[hw->dmar_block]);
959 /* enable TXQ */
960 AT_WRITE_REGW(hw, REG_TXQ_CTRL,
961 (((u16)hw->tpd_burst & TXQ_CTRL_NUM_TPD_BURST_MASK)
962 << TXQ_CTRL_NUM_TPD_BURST_SHIFT)
963 | TXQ_CTRL_ENH_MODE | TXQ_CTRL_EN);
964 return;
965 }
966
967 static inline void atl1e_configure_rx(struct atl1e_adapter *adapter)
968 {
969 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
970 u32 rxf_len = 0;
971 u32 rxf_low = 0;
972 u32 rxf_high = 0;
973 u32 rxf_thresh_data = 0;
974 u32 rxq_ctrl_data = 0;
975
976 if (hw->nic_type != athr_l2e_revB) {
977 AT_WRITE_REGW(hw, REG_RXQ_JMBOSZ_RRDTIM,
978 (u16)((hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK) <<
979 RXQ_JMBOSZ_TH_SHIFT |
980 (1 & RXQ_JMBO_LKAH_MASK) <<
981 RXQ_JMBO_LKAH_SHIFT));
982
983 rxf_len = AT_READ_REG(hw, REG_SRAM_RXF_LEN);
984 rxf_high = rxf_len * 4 / 5;
985 rxf_low = rxf_len / 5;
986 rxf_thresh_data = ((rxf_high & RXQ_RXF_PAUSE_TH_HI_MASK)
987 << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
988 ((rxf_low & RXQ_RXF_PAUSE_TH_LO_MASK)
989 << RXQ_RXF_PAUSE_TH_LO_SHIFT);
990
991 AT_WRITE_REG(hw, REG_RXQ_RXF_PAUSE_THRESH, rxf_thresh_data);
992 }
993
994 /* RRS */
995 AT_WRITE_REG(hw, REG_IDT_TABLE, hw->indirect_tab);
996 AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, hw->base_cpu);
997
998 if (hw->rrs_type & atl1e_rrs_ipv4)
999 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV4;
1000
1001 if (hw->rrs_type & atl1e_rrs_ipv4_tcp)
1002 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV4_TCP;
1003
1004 if (hw->rrs_type & atl1e_rrs_ipv6)
1005 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV6;
1006
1007 if (hw->rrs_type & atl1e_rrs_ipv6_tcp)
1008 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV6_TCP;
1009
1010 if (hw->rrs_type != atl1e_rrs_disable)
1011 rxq_ctrl_data |=
1012 (RXQ_CTRL_HASH_ENABLE | RXQ_CTRL_RSS_MODE_MQUESINT);
1013
1014 rxq_ctrl_data |= RXQ_CTRL_IPV6_XSUM_VERIFY_EN | RXQ_CTRL_PBA_ALIGN_32 |
1015 RXQ_CTRL_CUT_THRU_EN | RXQ_CTRL_EN;
1016
1017 AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
1018 return;
1019 }
1020
1021 static inline void atl1e_configure_dma(struct atl1e_adapter *adapter)
1022 {
1023 struct atl1e_hw *hw = &adapter->hw;
1024 u32 dma_ctrl_data = 0;
1025
1026 dma_ctrl_data = DMA_CTRL_RXCMB_EN;
1027 dma_ctrl_data |= (((u32)hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1028 << DMA_CTRL_DMAR_BURST_LEN_SHIFT;
1029 dma_ctrl_data |= (((u32)hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1030 << DMA_CTRL_DMAW_BURST_LEN_SHIFT;
1031 dma_ctrl_data |= DMA_CTRL_DMAR_REQ_PRI | DMA_CTRL_DMAR_OUT_ORDER;
1032 dma_ctrl_data |= (((u32)hw->dmar_dly_cnt) & DMA_CTRL_DMAR_DLY_CNT_MASK)
1033 << DMA_CTRL_DMAR_DLY_CNT_SHIFT;
1034 dma_ctrl_data |= (((u32)hw->dmaw_dly_cnt) & DMA_CTRL_DMAW_DLY_CNT_MASK)
1035 << DMA_CTRL_DMAW_DLY_CNT_SHIFT;
1036
1037 AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
1038 return;
1039 }
1040
1041 static void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter)
1042 {
1043 u32 value;
1044 struct atl1e_hw *hw = &adapter->hw;
1045 struct net_device *netdev = adapter->netdev;
1046
1047 /* Config MAC CTRL Register */
1048 value = MAC_CTRL_TX_EN |
1049 MAC_CTRL_RX_EN ;
1050
1051 if (FULL_DUPLEX == adapter->link_duplex)
1052 value |= MAC_CTRL_DUPLX;
1053
1054 value |= ((u32)((SPEED_1000 == adapter->link_speed) ?
1055 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
1056 MAC_CTRL_SPEED_SHIFT);
1057 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1058
1059 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1060 value |= (((u32)adapter->hw.preamble_len &
1061 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1062
1063 if (adapter->vlgrp)
1064 value |= MAC_CTRL_RMV_VLAN;
1065
1066 value |= MAC_CTRL_BC_EN;
1067 if (netdev->flags & IFF_PROMISC)
1068 value |= MAC_CTRL_PROMIS_EN;
1069 if (netdev->flags & IFF_ALLMULTI)
1070 value |= MAC_CTRL_MC_ALL_EN;
1071
1072 AT_WRITE_REG(hw, REG_MAC_CTRL, value);
1073 }
1074
1075 /*
1076 * atl1e_configure - Configure Transmit&Receive Unit after Reset
1077 * @adapter: board private structure
1078 *
1079 * Configure the Tx /Rx unit of the MAC after a reset.
1080 */
1081 static int atl1e_configure(struct atl1e_adapter *adapter)
1082 {
1083 struct atl1e_hw *hw = &adapter->hw;
1084 struct pci_dev *pdev = adapter->pdev;
1085
1086 u32 intr_status_data = 0;
1087
1088 /* clear interrupt status */
1089 AT_WRITE_REG(hw, REG_ISR, ~0);
1090
1091 /* 1. set MAC Address */
1092 atl1e_hw_set_mac_addr(hw);
1093
1094 /* 2. Init the Multicast HASH table done by set_muti */
1095
1096 /* 3. Clear any WOL status */
1097 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
1098
1099 /* 4. Descripter Ring BaseMem/Length/Read ptr/Write ptr
1100 * TPD Ring/SMB/RXF0 Page CMBs, they use the same
1101 * High 32bits memory */
1102 atl1e_configure_des_ring(adapter);
1103
1104 /* 5. set Interrupt Moderator Timer */
1105 AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, hw->imt);
1106 AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER2_INIT, hw->imt);
1107 AT_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_LED_MODE |
1108 MASTER_CTRL_ITIMER_EN | MASTER_CTRL_ITIMER2_EN);
1109
1110 /* 6. rx/tx threshold to trig interrupt */
1111 AT_WRITE_REGW(hw, REG_TRIG_RRD_THRESH, hw->rrd_thresh);
1112 AT_WRITE_REGW(hw, REG_TRIG_TPD_THRESH, hw->tpd_thresh);
1113 AT_WRITE_REGW(hw, REG_TRIG_RXTIMER, hw->rx_count_down);
1114 AT_WRITE_REGW(hw, REG_TRIG_TXTIMER, hw->tx_count_down);
1115
1116 /* 7. set Interrupt Clear Timer */
1117 AT_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, hw->ict);
1118
1119 /* 8. set MTU */
1120 AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
1121 VLAN_HLEN + ETH_FCS_LEN);
1122
1123 /* 9. config TXQ early tx threshold */
1124 atl1e_configure_tx(adapter);
1125
1126 /* 10. config RXQ */
1127 atl1e_configure_rx(adapter);
1128
1129 /* 11. config DMA Engine */
1130 atl1e_configure_dma(adapter);
1131
1132 /* 12. smb timer to trig interrupt */
1133 AT_WRITE_REG(hw, REG_SMB_STAT_TIMER, hw->smb_timer);
1134
1135 intr_status_data = AT_READ_REG(hw, REG_ISR);
1136 if (unlikely((intr_status_data & ISR_PHY_LINKDOWN) != 0)) {
1137 dev_err(&pdev->dev, "atl1e_configure failed,"
1138 "PCIE phy link down\n");
1139 return -1;
1140 }
1141
1142 AT_WRITE_REG(hw, REG_ISR, 0x7fffffff);
1143 return 0;
1144 }
1145
1146 /*
1147 * atl1e_get_stats - Get System Network Statistics
1148 * @netdev: network interface device structure
1149 *
1150 * Returns the address of the device statistics structure.
1151 * The statistics are actually updated from the timer callback.
1152 */
1153 static struct net_device_stats *atl1e_get_stats(struct net_device *netdev)
1154 {
1155 struct atl1e_adapter *adapter = netdev_priv(netdev);
1156 struct atl1e_hw_stats *hw_stats = &adapter->hw_stats;
1157 struct net_device_stats *net_stats = &netdev->stats;
1158
1159 net_stats->rx_packets = hw_stats->rx_ok;
1160 net_stats->tx_packets = hw_stats->tx_ok;
1161 net_stats->rx_bytes = hw_stats->rx_byte_cnt;
1162 net_stats->tx_bytes = hw_stats->tx_byte_cnt;
1163 net_stats->multicast = hw_stats->rx_mcast;
1164 net_stats->collisions = hw_stats->tx_1_col +
1165 hw_stats->tx_2_col * 2 +
1166 hw_stats->tx_late_col + hw_stats->tx_abort_col;
1167
1168 net_stats->rx_errors = hw_stats->rx_frag + hw_stats->rx_fcs_err +
1169 hw_stats->rx_len_err + hw_stats->rx_sz_ov +
1170 hw_stats->rx_rrd_ov + hw_stats->rx_align_err;
1171 net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov;
1172 net_stats->rx_length_errors = hw_stats->rx_len_err;
1173 net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
1174 net_stats->rx_frame_errors = hw_stats->rx_align_err;
1175 net_stats->rx_over_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
1176
1177 net_stats->rx_missed_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
1178
1179 net_stats->tx_errors = hw_stats->tx_late_col + hw_stats->tx_abort_col +
1180 hw_stats->tx_underrun + hw_stats->tx_trunc;
1181 net_stats->tx_fifo_errors = hw_stats->tx_underrun;
1182 net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
1183 net_stats->tx_window_errors = hw_stats->tx_late_col;
1184
1185 return net_stats;
1186 }
1187
1188 static void atl1e_update_hw_stats(struct atl1e_adapter *adapter)
1189 {
1190 u16 hw_reg_addr = 0;
1191 unsigned long *stats_item = NULL;
1192
1193 /* update rx status */
1194 hw_reg_addr = REG_MAC_RX_STATUS_BIN;
1195 stats_item = &adapter->hw_stats.rx_ok;
1196 while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
1197 *stats_item += AT_READ_REG(&adapter->hw, hw_reg_addr);
1198 stats_item++;
1199 hw_reg_addr += 4;
1200 }
1201 /* update tx status */
1202 hw_reg_addr = REG_MAC_TX_STATUS_BIN;
1203 stats_item = &adapter->hw_stats.tx_ok;
1204 while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
1205 *stats_item += AT_READ_REG(&adapter->hw, hw_reg_addr);
1206 stats_item++;
1207 hw_reg_addr += 4;
1208 }
1209 }
1210
1211 static inline void atl1e_clear_phy_int(struct atl1e_adapter *adapter)
1212 {
1213 u16 phy_data;
1214
1215 spin_lock(&adapter->mdio_lock);
1216 atl1e_read_phy_reg(&adapter->hw, MII_INT_STATUS, &phy_data);
1217 spin_unlock(&adapter->mdio_lock);
1218 }
1219
1220 static bool atl1e_clean_tx_irq(struct atl1e_adapter *adapter)
1221 {
1222 struct atl1e_tx_ring *tx_ring = (struct atl1e_tx_ring *)
1223 &adapter->tx_ring;
1224 struct atl1e_tx_buffer *tx_buffer = NULL;
1225 u16 hw_next_to_clean = AT_READ_REGW(&adapter->hw, REG_TPD_CONS_IDX);
1226 u16 next_to_clean = atomic_read(&tx_ring->next_to_clean);
1227
1228 while (next_to_clean != hw_next_to_clean) {
1229 tx_buffer = &tx_ring->tx_buffer[next_to_clean];
1230 if (tx_buffer->dma) {
1231 pci_unmap_page(adapter->pdev, tx_buffer->dma,
1232 tx_buffer->length, PCI_DMA_TODEVICE);
1233 tx_buffer->dma = 0;
1234 }
1235
1236 if (tx_buffer->skb) {
1237 dev_kfree_skb_irq(tx_buffer->skb);
1238 tx_buffer->skb = NULL;
1239 }
1240
1241 if (++next_to_clean == tx_ring->count)
1242 next_to_clean = 0;
1243 }
1244
1245 atomic_set(&tx_ring->next_to_clean, next_to_clean);
1246
1247 if (netif_queue_stopped(adapter->netdev) &&
1248 netif_carrier_ok(adapter->netdev)) {
1249 netif_wake_queue(adapter->netdev);
1250 }
1251
1252 return true;
1253 }
1254
1255 /*
1256 * atl1e_intr - Interrupt Handler
1257 * @irq: interrupt number
1258 * @data: pointer to a network interface device structure
1259 * @pt_regs: CPU registers structure
1260 */
1261 static irqreturn_t atl1e_intr(int irq, void *data)
1262 {
1263 struct net_device *netdev = data;
1264 struct atl1e_adapter *adapter = netdev_priv(netdev);
1265 struct pci_dev *pdev = adapter->pdev;
1266 struct atl1e_hw *hw = &adapter->hw;
1267 int max_ints = AT_MAX_INT_WORK;
1268 int handled = IRQ_NONE;
1269 u32 status;
1270
1271 do {
1272 status = AT_READ_REG(hw, REG_ISR);
1273 if ((status & IMR_NORMAL_MASK) == 0 ||
1274 (status & ISR_DIS_INT) != 0) {
1275 if (max_ints != AT_MAX_INT_WORK)
1276 handled = IRQ_HANDLED;
1277 break;
1278 }
1279 /* link event */
1280 if (status & ISR_GPHY)
1281 atl1e_clear_phy_int(adapter);
1282 /* Ack ISR */
1283 AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
1284
1285 handled = IRQ_HANDLED;
1286 /* check if PCIE PHY Link down */
1287 if (status & ISR_PHY_LINKDOWN) {
1288 dev_err(&pdev->dev,
1289 "pcie phy linkdown %x\n", status);
1290 if (netif_running(adapter->netdev)) {
1291 /* reset MAC */
1292 atl1e_irq_reset(adapter);
1293 schedule_work(&adapter->reset_task);
1294 break;
1295 }
1296 }
1297
1298 /* check if DMA read/write error */
1299 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
1300 dev_err(&pdev->dev,
1301 "PCIE DMA RW error (status = 0x%x)\n",
1302 status);
1303 atl1e_irq_reset(adapter);
1304 schedule_work(&adapter->reset_task);
1305 break;
1306 }
1307
1308 if (status & ISR_SMB)
1309 atl1e_update_hw_stats(adapter);
1310
1311 /* link event */
1312 if (status & (ISR_GPHY | ISR_MANUAL)) {
1313 netdev->stats.tx_carrier_errors++;
1314 atl1e_link_chg_event(adapter);
1315 break;
1316 }
1317
1318 /* transmit event */
1319 if (status & ISR_TX_EVENT)
1320 atl1e_clean_tx_irq(adapter);
1321
1322 if (status & ISR_RX_EVENT) {
1323 /*
1324 * disable rx interrupts, without
1325 * the synchronize_irq bit
1326 */
1327 AT_WRITE_REG(hw, REG_IMR,
1328 IMR_NORMAL_MASK & ~ISR_RX_EVENT);
1329 AT_WRITE_FLUSH(hw);
1330 if (likely(napi_schedule_prep(
1331 &adapter->napi)))
1332 __napi_schedule(&adapter->napi);
1333 }
1334 } while (--max_ints > 0);
1335 /* re-enable Interrupt*/
1336 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
1337
1338 return handled;
1339 }
1340
1341 static inline void atl1e_rx_checksum(struct atl1e_adapter *adapter,
1342 struct sk_buff *skb, struct atl1e_recv_ret_status *prrs)
1343 {
1344 u8 *packet = (u8 *)(prrs + 1);
1345 struct iphdr *iph;
1346 u16 head_len = ETH_HLEN;
1347 u16 pkt_flags;
1348 u16 err_flags;
1349
1350 skb->ip_summed = CHECKSUM_NONE;
1351 pkt_flags = prrs->pkt_flag;
1352 err_flags = prrs->err_flag;
1353 if (((pkt_flags & RRS_IS_IPV4) || (pkt_flags & RRS_IS_IPV6)) &&
1354 ((pkt_flags & RRS_IS_TCP) || (pkt_flags & RRS_IS_UDP))) {
1355 if (pkt_flags & RRS_IS_IPV4) {
1356 if (pkt_flags & RRS_IS_802_3)
1357 head_len += 8;
1358 iph = (struct iphdr *) (packet + head_len);
1359 if (iph->frag_off != 0 && !(pkt_flags & RRS_IS_IP_DF))
1360 goto hw_xsum;
1361 }
1362 if (!(err_flags & (RRS_ERR_IP_CSUM | RRS_ERR_L4_CSUM))) {
1363 skb->ip_summed = CHECKSUM_UNNECESSARY;
1364 return;
1365 }
1366 }
1367
1368 hw_xsum :
1369 return;
1370 }
1371
1372 static struct atl1e_rx_page *atl1e_get_rx_page(struct atl1e_adapter *adapter,
1373 u8 que)
1374 {
1375 struct atl1e_rx_page_desc *rx_page_desc =
1376 (struct atl1e_rx_page_desc *) adapter->rx_ring.rx_page_desc;
1377 u8 rx_using = rx_page_desc[que].rx_using;
1378
1379 return (struct atl1e_rx_page *)&(rx_page_desc[que].rx_page[rx_using]);
1380 }
1381
1382 static void atl1e_clean_rx_irq(struct atl1e_adapter *adapter, u8 que,
1383 int *work_done, int work_to_do)
1384 {
1385 struct pci_dev *pdev = adapter->pdev;
1386 struct net_device *netdev = adapter->netdev;
1387 struct atl1e_rx_ring *rx_ring = (struct atl1e_rx_ring *)
1388 &adapter->rx_ring;
1389 struct atl1e_rx_page_desc *rx_page_desc =
1390 (struct atl1e_rx_page_desc *) rx_ring->rx_page_desc;
1391 struct sk_buff *skb = NULL;
1392 struct atl1e_rx_page *rx_page = atl1e_get_rx_page(adapter, que);
1393 u32 packet_size, write_offset;
1394 struct atl1e_recv_ret_status *prrs;
1395
1396 write_offset = *(rx_page->write_offset_addr);
1397 if (likely(rx_page->read_offset < write_offset)) {
1398 do {
1399 if (*work_done >= work_to_do)
1400 break;
1401 (*work_done)++;
1402 /* get new packet's rrs */
1403 prrs = (struct atl1e_recv_ret_status *) (rx_page->addr +
1404 rx_page->read_offset);
1405 /* check sequence number */
1406 if (prrs->seq_num != rx_page_desc[que].rx_nxseq) {
1407 dev_err(&pdev->dev,
1408 "rx sequence number"
1409 " error (rx=%d) (expect=%d)\n",
1410 prrs->seq_num,
1411 rx_page_desc[que].rx_nxseq);
1412 rx_page_desc[que].rx_nxseq++;
1413 /* just for debug use */
1414 AT_WRITE_REG(&adapter->hw, REG_DEBUG_DATA0,
1415 (((u32)prrs->seq_num) << 16) |
1416 rx_page_desc[que].rx_nxseq);
1417 goto fatal_err;
1418 }
1419 rx_page_desc[que].rx_nxseq++;
1420
1421 /* error packet */
1422 if (prrs->pkt_flag & RRS_IS_ERR_FRAME) {
1423 if (prrs->err_flag & (RRS_ERR_BAD_CRC |
1424 RRS_ERR_DRIBBLE | RRS_ERR_CODE |
1425 RRS_ERR_TRUNC)) {
1426 /* hardware error, discard this packet*/
1427 dev_err(&pdev->dev,
1428 "rx packet desc error %x\n",
1429 *((u32 *)prrs + 1));
1430 goto skip_pkt;
1431 }
1432 }
1433
1434 packet_size = ((prrs->word1 >> RRS_PKT_SIZE_SHIFT) &
1435 RRS_PKT_SIZE_MASK) - 4; /* CRC */
1436 skb = netdev_alloc_skb(netdev,
1437 packet_size + NET_IP_ALIGN);
1438 if (skb == NULL) {
1439 dev_warn(&pdev->dev, "%s: Memory squeeze,"
1440 "deferring packet.\n", netdev->name);
1441 goto skip_pkt;
1442 }
1443 skb_reserve(skb, NET_IP_ALIGN);
1444 skb->dev = netdev;
1445 memcpy(skb->data, (u8 *)(prrs + 1), packet_size);
1446 skb_put(skb, packet_size);
1447 skb->protocol = eth_type_trans(skb, netdev);
1448 atl1e_rx_checksum(adapter, skb, prrs);
1449
1450 if (unlikely(adapter->vlgrp &&
1451 (prrs->pkt_flag & RRS_IS_VLAN_TAG))) {
1452 u16 vlan_tag = (prrs->vtag >> 4) |
1453 ((prrs->vtag & 7) << 13) |
1454 ((prrs->vtag & 8) << 9);
1455 dev_dbg(&pdev->dev,
1456 "RXD VLAN TAG<RRD>=0x%04x\n",
1457 prrs->vtag);
1458 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
1459 vlan_tag);
1460 } else {
1461 netif_receive_skb(skb);
1462 }
1463
1464 skip_pkt:
1465 /* skip current packet whether it's ok or not. */
1466 rx_page->read_offset +=
1467 (((u32)((prrs->word1 >> RRS_PKT_SIZE_SHIFT) &
1468 RRS_PKT_SIZE_MASK) +
1469 sizeof(struct atl1e_recv_ret_status) + 31) &
1470 0xFFFFFFE0);
1471
1472 if (rx_page->read_offset >= rx_ring->page_size) {
1473 /* mark this page clean */
1474 u16 reg_addr;
1475 u8 rx_using;
1476
1477 rx_page->read_offset =
1478 *(rx_page->write_offset_addr) = 0;
1479 rx_using = rx_page_desc[que].rx_using;
1480 reg_addr =
1481 atl1e_rx_page_vld_regs[que][rx_using];
1482 AT_WRITE_REGB(&adapter->hw, reg_addr, 1);
1483 rx_page_desc[que].rx_using ^= 1;
1484 rx_page = atl1e_get_rx_page(adapter, que);
1485 }
1486 write_offset = *(rx_page->write_offset_addr);
1487 } while (rx_page->read_offset < write_offset);
1488 }
1489
1490 return;
1491
1492 fatal_err:
1493 if (!test_bit(__AT_DOWN, &adapter->flags))
1494 schedule_work(&adapter->reset_task);
1495 }
1496
1497 /*
1498 * atl1e_clean - NAPI Rx polling callback
1499 * @adapter: board private structure
1500 */
1501 static int atl1e_clean(struct napi_struct *napi, int budget)
1502 {
1503 struct atl1e_adapter *adapter =
1504 container_of(napi, struct atl1e_adapter, napi);
1505 struct pci_dev *pdev = adapter->pdev;
1506 u32 imr_data;
1507 int work_done = 0;
1508
1509 /* Keep link state information with original netdev */
1510 if (!netif_carrier_ok(adapter->netdev))
1511 goto quit_polling;
1512
1513 atl1e_clean_rx_irq(adapter, 0, &work_done, budget);
1514
1515 /* If no Tx and not enough Rx work done, exit the polling mode */
1516 if (work_done < budget) {
1517 quit_polling:
1518 napi_complete(napi);
1519 imr_data = AT_READ_REG(&adapter->hw, REG_IMR);
1520 AT_WRITE_REG(&adapter->hw, REG_IMR, imr_data | ISR_RX_EVENT);
1521 /* test debug */
1522 if (test_bit(__AT_DOWN, &adapter->flags)) {
1523 atomic_dec(&adapter->irq_sem);
1524 dev_err(&pdev->dev,
1525 "atl1e_clean is called when AT_DOWN\n");
1526 }
1527 /* reenable RX intr */
1528 /*atl1e_irq_enable(adapter); */
1529
1530 }
1531 return work_done;
1532 }
1533
1534 #ifdef CONFIG_NET_POLL_CONTROLLER
1535
1536 /*
1537 * Polling 'interrupt' - used by things like netconsole to send skbs
1538 * without having to re-enable interrupts. It's not called while
1539 * the interrupt routine is executing.
1540 */
1541 static void atl1e_netpoll(struct net_device *netdev)
1542 {
1543 struct atl1e_adapter *adapter = netdev_priv(netdev);
1544
1545 disable_irq(adapter->pdev->irq);
1546 atl1e_intr(adapter->pdev->irq, netdev);
1547 enable_irq(adapter->pdev->irq);
1548 }
1549 #endif
1550
1551 static inline u16 atl1e_tpd_avail(struct atl1e_adapter *adapter)
1552 {
1553 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1554 u16 next_to_use = 0;
1555 u16 next_to_clean = 0;
1556
1557 next_to_clean = atomic_read(&tx_ring->next_to_clean);
1558 next_to_use = tx_ring->next_to_use;
1559
1560 return (u16)(next_to_clean > next_to_use) ?
1561 (next_to_clean - next_to_use - 1) :
1562 (tx_ring->count + next_to_clean - next_to_use - 1);
1563 }
1564
1565 /*
1566 * get next usable tpd
1567 * Note: should call atl1e_tdp_avail to make sure
1568 * there is enough tpd to use
1569 */
1570 static struct atl1e_tpd_desc *atl1e_get_tpd(struct atl1e_adapter *adapter)
1571 {
1572 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1573 u16 next_to_use = 0;
1574
1575 next_to_use = tx_ring->next_to_use;
1576 if (++tx_ring->next_to_use == tx_ring->count)
1577 tx_ring->next_to_use = 0;
1578
1579 memset(&tx_ring->desc[next_to_use], 0, sizeof(struct atl1e_tpd_desc));
1580 return (struct atl1e_tpd_desc *)&tx_ring->desc[next_to_use];
1581 }
1582
1583 static struct atl1e_tx_buffer *
1584 atl1e_get_tx_buffer(struct atl1e_adapter *adapter, struct atl1e_tpd_desc *tpd)
1585 {
1586 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1587
1588 return &tx_ring->tx_buffer[tpd - tx_ring->desc];
1589 }
1590
1591 /* Calculate the transmit packet descript needed*/
1592 static u16 atl1e_cal_tdp_req(const struct sk_buff *skb)
1593 {
1594 int i = 0;
1595 u16 tpd_req = 1;
1596 u16 fg_size = 0;
1597 u16 proto_hdr_len = 0;
1598
1599 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1600 fg_size = skb_shinfo(skb)->frags[i].size;
1601 tpd_req += ((fg_size + MAX_TX_BUF_LEN - 1) >> MAX_TX_BUF_SHIFT);
1602 }
1603
1604 if (skb_is_gso(skb)) {
1605 if (skb->protocol == htons(ETH_P_IP) ||
1606 (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6)) {
1607 proto_hdr_len = skb_transport_offset(skb) +
1608 tcp_hdrlen(skb);
1609 if (proto_hdr_len < skb_headlen(skb)) {
1610 tpd_req += ((skb_headlen(skb) - proto_hdr_len +
1611 MAX_TX_BUF_LEN - 1) >>
1612 MAX_TX_BUF_SHIFT);
1613 }
1614 }
1615
1616 }
1617 return tpd_req;
1618 }
1619
1620 static int atl1e_tso_csum(struct atl1e_adapter *adapter,
1621 struct sk_buff *skb, struct atl1e_tpd_desc *tpd)
1622 {
1623 struct pci_dev *pdev = adapter->pdev;
1624 u8 hdr_len;
1625 u32 real_len;
1626 unsigned short offload_type;
1627 int err;
1628
1629 if (skb_is_gso(skb)) {
1630 if (skb_header_cloned(skb)) {
1631 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1632 if (unlikely(err))
1633 return -1;
1634 }
1635 offload_type = skb_shinfo(skb)->gso_type;
1636
1637 if (offload_type & SKB_GSO_TCPV4) {
1638 real_len = (((unsigned char *)ip_hdr(skb) - skb->data)
1639 + ntohs(ip_hdr(skb)->tot_len));
1640
1641 if (real_len < skb->len)
1642 pskb_trim(skb, real_len);
1643
1644 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
1645 if (unlikely(skb->len == hdr_len)) {
1646 /* only xsum need */
1647 dev_warn(&pdev->dev,
1648 "IPV4 tso with zero data??\n");
1649 goto check_sum;
1650 } else {
1651 ip_hdr(skb)->check = 0;
1652 ip_hdr(skb)->tot_len = 0;
1653 tcp_hdr(skb)->check = ~csum_tcpudp_magic(
1654 ip_hdr(skb)->saddr,
1655 ip_hdr(skb)->daddr,
1656 0, IPPROTO_TCP, 0);
1657 tpd->word3 |= (ip_hdr(skb)->ihl &
1658 TDP_V4_IPHL_MASK) <<
1659 TPD_V4_IPHL_SHIFT;
1660 tpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
1661 TPD_TCPHDRLEN_MASK) <<
1662 TPD_TCPHDRLEN_SHIFT;
1663 tpd->word3 |= ((skb_shinfo(skb)->gso_size) &
1664 TPD_MSS_MASK) << TPD_MSS_SHIFT;
1665 tpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
1666 }
1667 return 0;
1668 }
1669
1670 if (offload_type & SKB_GSO_TCPV6) {
1671 real_len = (((unsigned char *)ipv6_hdr(skb) - skb->data)
1672 + ntohs(ipv6_hdr(skb)->payload_len));
1673 if (real_len < skb->len)
1674 pskb_trim(skb, real_len);
1675
1676 /* check payload == 0 byte ? */
1677 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
1678 if (unlikely(skb->len == hdr_len)) {
1679 /* only xsum need */
1680 dev_warn(&pdev->dev,
1681 "IPV6 tso with zero data??\n");
1682 goto check_sum;
1683 } else {
1684 tcp_hdr(skb)->check = ~csum_ipv6_magic(
1685 &ipv6_hdr(skb)->saddr,
1686 &ipv6_hdr(skb)->daddr,
1687 0, IPPROTO_TCP, 0);
1688 tpd->word3 |= 1 << TPD_IP_VERSION_SHIFT;
1689 hdr_len >>= 1;
1690 tpd->word3 |= (hdr_len & TPD_V6_IPHLLO_MASK) <<
1691 TPD_V6_IPHLLO_SHIFT;
1692 tpd->word3 |= ((hdr_len >> 3) &
1693 TPD_V6_IPHLHI_MASK) <<
1694 TPD_V6_IPHLHI_SHIFT;
1695 tpd->word3 |= (tcp_hdrlen(skb) >> 2 &
1696 TPD_TCPHDRLEN_MASK) <<
1697 TPD_TCPHDRLEN_SHIFT;
1698 tpd->word3 |= ((skb_shinfo(skb)->gso_size) &
1699 TPD_MSS_MASK) << TPD_MSS_SHIFT;
1700 tpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
1701 }
1702 }
1703 return 0;
1704 }
1705
1706 check_sum:
1707 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1708 u8 css, cso;
1709
1710 cso = skb_transport_offset(skb);
1711 if (unlikely(cso & 0x1)) {
1712 dev_err(&adapter->pdev->dev,
1713 "pay load offset should not ant event number\n");
1714 return -1;
1715 } else {
1716 css = cso + skb->csum_offset;
1717 tpd->word3 |= (cso & TPD_PLOADOFFSET_MASK) <<
1718 TPD_PLOADOFFSET_SHIFT;
1719 tpd->word3 |= (css & TPD_CCSUMOFFSET_MASK) <<
1720 TPD_CCSUMOFFSET_SHIFT;
1721 tpd->word3 |= 1 << TPD_CC_SEGMENT_EN_SHIFT;
1722 }
1723 }
1724
1725 return 0;
1726 }
1727
1728 static void atl1e_tx_map(struct atl1e_adapter *adapter,
1729 struct sk_buff *skb, struct atl1e_tpd_desc *tpd)
1730 {
1731 struct atl1e_tpd_desc *use_tpd = NULL;
1732 struct atl1e_tx_buffer *tx_buffer = NULL;
1733 u16 buf_len = skb->len - skb->data_len;
1734 u16 map_len = 0;
1735 u16 mapped_len = 0;
1736 u16 hdr_len = 0;
1737 u16 nr_frags;
1738 u16 f;
1739 int segment;
1740
1741 nr_frags = skb_shinfo(skb)->nr_frags;
1742 segment = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK;
1743 if (segment) {
1744 /* TSO */
1745 map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1746 use_tpd = tpd;
1747
1748 tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
1749 tx_buffer->length = map_len;
1750 tx_buffer->dma = pci_map_single(adapter->pdev,
1751 skb->data, hdr_len, PCI_DMA_TODEVICE);
1752 mapped_len += map_len;
1753 use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
1754 use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
1755 ((cpu_to_le32(tx_buffer->length) &
1756 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
1757 }
1758
1759 while (mapped_len < buf_len) {
1760 /* mapped_len == 0, means we should use the first tpd,
1761 which is given by caller */
1762 if (mapped_len == 0) {
1763 use_tpd = tpd;
1764 } else {
1765 use_tpd = atl1e_get_tpd(adapter);
1766 memcpy(use_tpd, tpd, sizeof(struct atl1e_tpd_desc));
1767 }
1768 tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
1769 tx_buffer->skb = NULL;
1770
1771 tx_buffer->length = map_len =
1772 ((buf_len - mapped_len) >= MAX_TX_BUF_LEN) ?
1773 MAX_TX_BUF_LEN : (buf_len - mapped_len);
1774 tx_buffer->dma =
1775 pci_map_single(adapter->pdev, skb->data + mapped_len,
1776 map_len, PCI_DMA_TODEVICE);
1777 mapped_len += map_len;
1778 use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
1779 use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
1780 ((cpu_to_le32(tx_buffer->length) &
1781 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
1782 }
1783
1784 for (f = 0; f < nr_frags; f++) {
1785 struct skb_frag_struct *frag;
1786 u16 i;
1787 u16 seg_num;
1788
1789 frag = &skb_shinfo(skb)->frags[f];
1790 buf_len = frag->size;
1791
1792 seg_num = (buf_len + MAX_TX_BUF_LEN - 1) / MAX_TX_BUF_LEN;
1793 for (i = 0; i < seg_num; i++) {
1794 use_tpd = atl1e_get_tpd(adapter);
1795 memcpy(use_tpd, tpd, sizeof(struct atl1e_tpd_desc));
1796
1797 tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
1798 BUG_ON(tx_buffer->skb);
1799
1800 tx_buffer->skb = NULL;
1801 tx_buffer->length =
1802 (buf_len > MAX_TX_BUF_LEN) ?
1803 MAX_TX_BUF_LEN : buf_len;
1804 buf_len -= tx_buffer->length;
1805
1806 tx_buffer->dma =
1807 pci_map_page(adapter->pdev, frag->page,
1808 frag->page_offset +
1809 (i * MAX_TX_BUF_LEN),
1810 tx_buffer->length,
1811 PCI_DMA_TODEVICE);
1812 use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
1813 use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
1814 ((cpu_to_le32(tx_buffer->length) &
1815 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
1816 }
1817 }
1818
1819 if ((tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK)
1820 /* note this one is a tcp header */
1821 tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT;
1822 /* The last tpd */
1823
1824 use_tpd->word3 |= 1 << TPD_EOP_SHIFT;
1825 /* The last buffer info contain the skb address,
1826 so it will be free after unmap */
1827 tx_buffer->skb = skb;
1828 }
1829
1830 static void atl1e_tx_queue(struct atl1e_adapter *adapter, u16 count,
1831 struct atl1e_tpd_desc *tpd)
1832 {
1833 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1834 /* Force memory writes to complete before letting h/w
1835 * know there are new descriptors to fetch. (Only
1836 * applicable for weak-ordered memory model archs,
1837 * such as IA-64). */
1838 wmb();
1839 AT_WRITE_REG(&adapter->hw, REG_MB_TPD_PROD_IDX, tx_ring->next_to_use);
1840 }
1841
1842 static int atl1e_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1843 {
1844 struct atl1e_adapter *adapter = netdev_priv(netdev);
1845 unsigned long flags;
1846 u16 tpd_req = 1;
1847 struct atl1e_tpd_desc *tpd;
1848
1849 if (test_bit(__AT_DOWN, &adapter->flags)) {
1850 dev_kfree_skb_any(skb);
1851 return NETDEV_TX_OK;
1852 }
1853
1854 if (unlikely(skb->len <= 0)) {
1855 dev_kfree_skb_any(skb);
1856 return NETDEV_TX_OK;
1857 }
1858 tpd_req = atl1e_cal_tdp_req(skb);
1859 if (!spin_trylock_irqsave(&adapter->tx_lock, flags))
1860 return NETDEV_TX_LOCKED;
1861
1862 if (atl1e_tpd_avail(adapter) < tpd_req) {
1863 /* no enough descriptor, just stop queue */
1864 netif_stop_queue(netdev);
1865 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1866 return NETDEV_TX_BUSY;
1867 }
1868
1869 tpd = atl1e_get_tpd(adapter);
1870
1871 if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
1872 u16 vlan_tag = vlan_tx_tag_get(skb);
1873 u16 atl1e_vlan_tag;
1874
1875 tpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT;
1876 AT_VLAN_TAG_TO_TPD_TAG(vlan_tag, atl1e_vlan_tag);
1877 tpd->word2 |= (atl1e_vlan_tag & TPD_VLANTAG_MASK) <<
1878 TPD_VLAN_SHIFT;
1879 }
1880
1881 if (skb->protocol == htons(ETH_P_8021Q))
1882 tpd->word3 |= 1 << TPD_VL_TAGGED_SHIFT;
1883
1884 if (skb_network_offset(skb) != ETH_HLEN)
1885 tpd->word3 |= 1 << TPD_ETHTYPE_SHIFT; /* 802.3 frame */
1886
1887 /* do TSO and check sum */
1888 if (atl1e_tso_csum(adapter, skb, tpd) != 0) {
1889 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1890 dev_kfree_skb_any(skb);
1891 return NETDEV_TX_OK;
1892 }
1893
1894 atl1e_tx_map(adapter, skb, tpd);
1895 atl1e_tx_queue(adapter, tpd_req, tpd);
1896
1897 netdev->trans_start = jiffies; /* NETIF_F_LLTX driver :( */
1898 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1899 return NETDEV_TX_OK;
1900 }
1901
1902 static void atl1e_free_irq(struct atl1e_adapter *adapter)
1903 {
1904 struct net_device *netdev = adapter->netdev;
1905
1906 free_irq(adapter->pdev->irq, netdev);
1907
1908 if (adapter->have_msi)
1909 pci_disable_msi(adapter->pdev);
1910 }
1911
1912 static int atl1e_request_irq(struct atl1e_adapter *adapter)
1913 {
1914 struct pci_dev *pdev = adapter->pdev;
1915 struct net_device *netdev = adapter->netdev;
1916 int flags = 0;
1917 int err = 0;
1918
1919 adapter->have_msi = true;
1920 err = pci_enable_msi(adapter->pdev);
1921 if (err) {
1922 dev_dbg(&pdev->dev,
1923 "Unable to allocate MSI interrupt Error: %d\n", err);
1924 adapter->have_msi = false;
1925 } else
1926 netdev->irq = pdev->irq;
1927
1928
1929 if (!adapter->have_msi)
1930 flags |= IRQF_SHARED;
1931 err = request_irq(adapter->pdev->irq, &atl1e_intr, flags,
1932 netdev->name, netdev);
1933 if (err) {
1934 dev_dbg(&pdev->dev,
1935 "Unable to allocate interrupt Error: %d\n", err);
1936 if (adapter->have_msi)
1937 pci_disable_msi(adapter->pdev);
1938 return err;
1939 }
1940 dev_dbg(&pdev->dev, "atl1e_request_irq OK\n");
1941 return err;
1942 }
1943
1944 int atl1e_up(struct atl1e_adapter *adapter)
1945 {
1946 struct net_device *netdev = adapter->netdev;
1947 int err = 0;
1948 u32 val;
1949
1950 /* hardware has been reset, we need to reload some things */
1951 err = atl1e_init_hw(&adapter->hw);
1952 if (err) {
1953 err = -EIO;
1954 return err;
1955 }
1956 atl1e_init_ring_ptrs(adapter);
1957 atl1e_set_multi(netdev);
1958 atl1e_restore_vlan(adapter);
1959
1960 if (atl1e_configure(adapter)) {
1961 err = -EIO;
1962 goto err_up;
1963 }
1964
1965 clear_bit(__AT_DOWN, &adapter->flags);
1966 napi_enable(&adapter->napi);
1967 atl1e_irq_enable(adapter);
1968 val = AT_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1969 AT_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
1970 val | MASTER_CTRL_MANUAL_INT);
1971
1972 err_up:
1973 return err;
1974 }
1975
1976 void atl1e_down(struct atl1e_adapter *adapter)
1977 {
1978 struct net_device *netdev = adapter->netdev;
1979
1980 /* signal that we're down so the interrupt handler does not
1981 * reschedule our watchdog timer */
1982 set_bit(__AT_DOWN, &adapter->flags);
1983
1984 #ifdef NETIF_F_LLTX
1985 netif_stop_queue(netdev);
1986 #else
1987 netif_tx_disable(netdev);
1988 #endif
1989
1990 /* reset MAC to disable all RX/TX */
1991 atl1e_reset_hw(&adapter->hw);
1992 msleep(1);
1993
1994 napi_disable(&adapter->napi);
1995 atl1e_del_timer(adapter);
1996 atl1e_irq_disable(adapter);
1997
1998 netif_carrier_off(netdev);
1999 adapter->link_speed = SPEED_0;
2000 adapter->link_duplex = -1;
2001 atl1e_clean_tx_ring(adapter);
2002 atl1e_clean_rx_ring(adapter);
2003 }
2004
2005 /*
2006 * atl1e_open - Called when a network interface is made active
2007 * @netdev: network interface device structure
2008 *
2009 * Returns 0 on success, negative value on failure
2010 *
2011 * The open entry point is called when a network interface is made
2012 * active by the system (IFF_UP). At this point all resources needed
2013 * for transmit and receive operations are allocated, the interrupt
2014 * handler is registered with the OS, the watchdog timer is started,
2015 * and the stack is notified that the interface is ready.
2016 */
2017 static int atl1e_open(struct net_device *netdev)
2018 {
2019 struct atl1e_adapter *adapter = netdev_priv(netdev);
2020 int err;
2021
2022 /* disallow open during test */
2023 if (test_bit(__AT_TESTING, &adapter->flags))
2024 return -EBUSY;
2025
2026 /* allocate rx/tx dma buffer & descriptors */
2027 atl1e_init_ring_resources(adapter);
2028 err = atl1e_setup_ring_resources(adapter);
2029 if (unlikely(err))
2030 return err;
2031
2032 err = atl1e_request_irq(adapter);
2033 if (unlikely(err))
2034 goto err_req_irq;
2035
2036 err = atl1e_up(adapter);
2037 if (unlikely(err))
2038 goto err_up;
2039
2040 return 0;
2041
2042 err_up:
2043 atl1e_free_irq(adapter);
2044 err_req_irq:
2045 atl1e_free_ring_resources(adapter);
2046 atl1e_reset_hw(&adapter->hw);
2047
2048 return err;
2049 }
2050
2051 /*
2052 * atl1e_close - Disables a network interface
2053 * @netdev: network interface device structure
2054 *
2055 * Returns 0, this is not allowed to fail
2056 *
2057 * The close entry point is called when an interface is de-activated
2058 * by the OS. The hardware is still under the drivers control, but
2059 * needs to be disabled. A global MAC reset is issued to stop the
2060 * hardware, and all transmit and receive resources are freed.
2061 */
2062 static int atl1e_close(struct net_device *netdev)
2063 {
2064 struct atl1e_adapter *adapter = netdev_priv(netdev);
2065
2066 WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
2067 atl1e_down(adapter);
2068 atl1e_free_irq(adapter);
2069 atl1e_free_ring_resources(adapter);
2070
2071 return 0;
2072 }
2073
2074 static int atl1e_suspend(struct pci_dev *pdev, pm_message_t state)
2075 {
2076 struct net_device *netdev = pci_get_drvdata(pdev);
2077 struct atl1e_adapter *adapter = netdev_priv(netdev);
2078 struct atl1e_hw *hw = &adapter->hw;
2079 u32 ctrl = 0;
2080 u32 mac_ctrl_data = 0;
2081 u32 wol_ctrl_data = 0;
2082 u16 mii_advertise_data = 0;
2083 u16 mii_bmsr_data = 0;
2084 u16 mii_intr_status_data = 0;
2085 u32 wufc = adapter->wol;
2086 u32 i;
2087 #ifdef CONFIG_PM
2088 int retval = 0;
2089 #endif
2090
2091 if (netif_running(netdev)) {
2092 WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
2093 atl1e_down(adapter);
2094 }
2095 netif_device_detach(netdev);
2096
2097 #ifdef CONFIG_PM
2098 retval = pci_save_state(pdev);
2099 if (retval)
2100 return retval;
2101 #endif
2102
2103 if (wufc) {
2104 /* get link status */
2105 atl1e_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data);
2106 atl1e_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data);
2107
2108 mii_advertise_data = MII_AR_10T_HD_CAPS;
2109
2110 if ((atl1e_write_phy_reg(hw, MII_AT001_CR, 0) != 0) ||
2111 (atl1e_write_phy_reg(hw,
2112 MII_ADVERTISE, mii_advertise_data) != 0) ||
2113 (atl1e_phy_commit(hw)) != 0) {
2114 dev_dbg(&pdev->dev, "set phy register failed\n");
2115 goto wol_dis;
2116 }
2117
2118 hw->phy_configured = false; /* re-init PHY when resume */
2119
2120 /* turn on magic packet wol */
2121 if (wufc & AT_WUFC_MAG)
2122 wol_ctrl_data |= WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
2123
2124 if (wufc & AT_WUFC_LNKC) {
2125 /* if orignal link status is link, just wait for retrive link */
2126 if (mii_bmsr_data & BMSR_LSTATUS) {
2127 for (i = 0; i < AT_SUSPEND_LINK_TIMEOUT; i++) {
2128 msleep(100);
2129 atl1e_read_phy_reg(hw, MII_BMSR,
2130 (u16 *)&mii_bmsr_data);
2131 if (mii_bmsr_data & BMSR_LSTATUS)
2132 break;
2133 }
2134
2135 if ((mii_bmsr_data & BMSR_LSTATUS) == 0)
2136 dev_dbg(&pdev->dev,
2137 "%s: Link may change"
2138 "when suspend\n",
2139 atl1e_driver_name);
2140 }
2141 wol_ctrl_data |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN;
2142 /* only link up can wake up */
2143 if (atl1e_write_phy_reg(hw, MII_INT_CTRL, 0x400) != 0) {
2144 dev_dbg(&pdev->dev, "%s: read write phy "
2145 "register failed.\n",
2146 atl1e_driver_name);
2147 goto wol_dis;
2148 }
2149 }
2150 /* clear phy interrupt */
2151 atl1e_read_phy_reg(hw, MII_INT_STATUS, &mii_intr_status_data);
2152 /* Config MAC Ctrl register */
2153 mac_ctrl_data = MAC_CTRL_RX_EN;
2154 /* set to 10/100M halt duplex */
2155 mac_ctrl_data |= MAC_CTRL_SPEED_10_100 << MAC_CTRL_SPEED_SHIFT;
2156 mac_ctrl_data |= (((u32)adapter->hw.preamble_len &
2157 MAC_CTRL_PRMLEN_MASK) <<
2158 MAC_CTRL_PRMLEN_SHIFT);
2159
2160 if (adapter->vlgrp)
2161 mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
2162
2163 /* magic packet maybe Broadcast&multicast&Unicast frame */
2164 if (wufc & AT_WUFC_MAG)
2165 mac_ctrl_data |= MAC_CTRL_BC_EN;
2166
2167 dev_dbg(&pdev->dev,
2168 "%s: suspend MAC=0x%x\n",
2169 atl1e_driver_name, mac_ctrl_data);
2170
2171 AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
2172 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
2173 /* pcie patch */
2174 ctrl = AT_READ_REG(hw, REG_PCIE_PHYMISC);
2175 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2176 AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
2177 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
2178 goto suspend_exit;
2179 }
2180 wol_dis:
2181
2182 /* WOL disabled */
2183 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
2184
2185 /* pcie patch */
2186 ctrl = AT_READ_REG(hw, REG_PCIE_PHYMISC);
2187 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2188 AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
2189
2190 atl1e_force_ps(hw);
2191 hw->phy_configured = false; /* re-init PHY when resume */
2192
2193 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
2194
2195 suspend_exit:
2196
2197 if (netif_running(netdev))
2198 atl1e_free_irq(adapter);
2199
2200 pci_disable_device(pdev);
2201
2202 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2203
2204 return 0;
2205 }
2206
2207 #ifdef CONFIG_PM
2208 static int atl1e_resume(struct pci_dev *pdev)
2209 {
2210 struct net_device *netdev = pci_get_drvdata(pdev);
2211 struct atl1e_adapter *adapter = netdev_priv(netdev);
2212 u32 err;
2213
2214 pci_set_power_state(pdev, PCI_D0);
2215 pci_restore_state(pdev);
2216
2217 err = pci_enable_device(pdev);
2218 if (err) {
2219 dev_err(&pdev->dev, "ATL1e: Cannot enable PCI"
2220 " device from suspend\n");
2221 return err;
2222 }
2223
2224 pci_set_master(pdev);
2225
2226 AT_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
2227
2228 pci_enable_wake(pdev, PCI_D3hot, 0);
2229 pci_enable_wake(pdev, PCI_D3cold, 0);
2230
2231 AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
2232
2233 if (netif_running(netdev)) {
2234 err = atl1e_request_irq(adapter);
2235 if (err)
2236 return err;
2237 }
2238
2239 atl1e_reset_hw(&adapter->hw);
2240
2241 if (netif_running(netdev))
2242 atl1e_up(adapter);
2243
2244 netif_device_attach(netdev);
2245
2246 return 0;
2247 }
2248 #endif
2249
2250 static void atl1e_shutdown(struct pci_dev *pdev)
2251 {
2252 atl1e_suspend(pdev, PMSG_SUSPEND);
2253 }
2254
2255 static const struct net_device_ops atl1e_netdev_ops = {
2256 .ndo_open = atl1e_open,
2257 .ndo_stop = atl1e_close,
2258 .ndo_start_xmit = atl1e_xmit_frame,
2259 .ndo_get_stats = atl1e_get_stats,
2260 .ndo_set_multicast_list = atl1e_set_multi,
2261 .ndo_validate_addr = eth_validate_addr,
2262 .ndo_set_mac_address = atl1e_set_mac_addr,
2263 .ndo_change_mtu = atl1e_change_mtu,
2264 .ndo_do_ioctl = atl1e_ioctl,
2265 .ndo_tx_timeout = atl1e_tx_timeout,
2266 .ndo_vlan_rx_register = atl1e_vlan_rx_register,
2267 #ifdef CONFIG_NET_POLL_CONTROLLER
2268 .ndo_poll_controller = atl1e_netpoll,
2269 #endif
2270
2271 };
2272
2273 static int atl1e_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
2274 {
2275 SET_NETDEV_DEV(netdev, &pdev->dev);
2276 pci_set_drvdata(pdev, netdev);
2277
2278 netdev->irq = pdev->irq;
2279 netdev->netdev_ops = &atl1e_netdev_ops;
2280
2281 netdev->watchdog_timeo = AT_TX_WATCHDOG;
2282 atl1e_set_ethtool_ops(netdev);
2283
2284 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM |
2285 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2286 netdev->features |= NETIF_F_LLTX;
2287 netdev->features |= NETIF_F_TSO;
2288 netdev->features |= NETIF_F_TSO6;
2289
2290 return 0;
2291 }
2292
2293 /*
2294 * atl1e_probe - Device Initialization Routine
2295 * @pdev: PCI device information struct
2296 * @ent: entry in atl1e_pci_tbl
2297 *
2298 * Returns 0 on success, negative on failure
2299 *
2300 * atl1e_probe initializes an adapter identified by a pci_dev structure.
2301 * The OS initialization, configuring of the adapter private structure,
2302 * and a hardware reset occur.
2303 */
2304 static int __devinit atl1e_probe(struct pci_dev *pdev,
2305 const struct pci_device_id *ent)
2306 {
2307 struct net_device *netdev;
2308 struct atl1e_adapter *adapter = NULL;
2309 static int cards_found;
2310
2311 int err = 0;
2312
2313 err = pci_enable_device(pdev);
2314 if (err) {
2315 dev_err(&pdev->dev, "cannot enable PCI device\n");
2316 return err;
2317 }
2318
2319 /*
2320 * The atl1e chip can DMA to 64-bit addresses, but it uses a single
2321 * shared register for the high 32 bits, so only a single, aligned,
2322 * 4 GB physical address range can be used at a time.
2323 *
2324 * Supporting 64-bit DMA on this hardware is more trouble than it's
2325 * worth. It is far easier to limit to 32-bit DMA than update
2326 * various kernel subsystems to support the mechanics required by a
2327 * fixed-high-32-bit system.
2328 */
2329 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
2330 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
2331 dev_err(&pdev->dev, "No usable DMA configuration,aborting\n");
2332 goto err_dma;
2333 }
2334
2335 err = pci_request_regions(pdev, atl1e_driver_name);
2336 if (err) {
2337 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
2338 goto err_pci_reg;
2339 }
2340
2341 pci_set_master(pdev);
2342
2343 netdev = alloc_etherdev(sizeof(struct atl1e_adapter));
2344 if (netdev == NULL) {
2345 err = -ENOMEM;
2346 dev_err(&pdev->dev, "etherdev alloc failed\n");
2347 goto err_alloc_etherdev;
2348 }
2349
2350 err = atl1e_init_netdev(netdev, pdev);
2351 if (err) {
2352 dev_err(&pdev->dev, "init netdevice failed\n");
2353 goto err_init_netdev;
2354 }
2355 adapter = netdev_priv(netdev);
2356 adapter->bd_number = cards_found;
2357 adapter->netdev = netdev;
2358 adapter->pdev = pdev;
2359 adapter->hw.adapter = adapter;
2360 adapter->hw.hw_addr = pci_iomap(pdev, BAR_0, 0);
2361 if (!adapter->hw.hw_addr) {
2362 err = -EIO;
2363 dev_err(&pdev->dev, "cannot map device registers\n");
2364 goto err_ioremap;
2365 }
2366 netdev->base_addr = (unsigned long)adapter->hw.hw_addr;
2367
2368 /* init mii data */
2369 adapter->mii.dev = netdev;
2370 adapter->mii.mdio_read = atl1e_mdio_read;
2371 adapter->mii.mdio_write = atl1e_mdio_write;
2372 adapter->mii.phy_id_mask = 0x1f;
2373 adapter->mii.reg_num_mask = MDIO_REG_ADDR_MASK;
2374
2375 netif_napi_add(netdev, &adapter->napi, atl1e_clean, 64);
2376
2377 init_timer(&adapter->phy_config_timer);
2378 adapter->phy_config_timer.function = &atl1e_phy_config;
2379 adapter->phy_config_timer.data = (unsigned long) adapter;
2380
2381 /* get user settings */
2382 atl1e_check_options(adapter);
2383 /*
2384 * Mark all PCI regions associated with PCI device
2385 * pdev as being reserved by owner atl1e_driver_name
2386 * Enables bus-mastering on the device and calls
2387 * pcibios_set_master to do the needed arch specific settings
2388 */
2389 atl1e_setup_pcicmd(pdev);
2390 /* setup the private structure */
2391 err = atl1e_sw_init(adapter);
2392 if (err) {
2393 dev_err(&pdev->dev, "net device private data init failed\n");
2394 goto err_sw_init;
2395 }
2396
2397 /* Init GPHY as early as possible due to power saving issue */
2398 atl1e_phy_init(&adapter->hw);
2399 /* reset the controller to
2400 * put the device in a known good starting state */
2401 err = atl1e_reset_hw(&adapter->hw);
2402 if (err) {
2403 err = -EIO;
2404 goto err_reset;
2405 }
2406
2407 if (atl1e_read_mac_addr(&adapter->hw) != 0) {
2408 err = -EIO;
2409 dev_err(&pdev->dev, "get mac address failed\n");
2410 goto err_eeprom;
2411 }
2412
2413 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
2414 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
2415 dev_dbg(&pdev->dev, "mac address : %02x-%02x-%02x-%02x-%02x-%02x\n",
2416 adapter->hw.mac_addr[0], adapter->hw.mac_addr[1],
2417 adapter->hw.mac_addr[2], adapter->hw.mac_addr[3],
2418 adapter->hw.mac_addr[4], adapter->hw.mac_addr[5]);
2419
2420 INIT_WORK(&adapter->reset_task, atl1e_reset_task);
2421 INIT_WORK(&adapter->link_chg_task, atl1e_link_chg_task);
2422 err = register_netdev(netdev);
2423 if (err) {
2424 dev_err(&pdev->dev, "register netdevice failed\n");
2425 goto err_register;
2426 }
2427
2428 /* assume we have no link for now */
2429 netif_stop_queue(netdev);
2430 netif_carrier_off(netdev);
2431
2432 cards_found++;
2433
2434 return 0;
2435
2436 err_reset:
2437 err_register:
2438 err_sw_init:
2439 err_eeprom:
2440 iounmap(adapter->hw.hw_addr);
2441 err_init_netdev:
2442 err_ioremap:
2443 free_netdev(netdev);
2444 err_alloc_etherdev:
2445 pci_release_regions(pdev);
2446 err_pci_reg:
2447 err_dma:
2448 pci_disable_device(pdev);
2449 return err;
2450 }
2451
2452 /*
2453 * atl1e_remove - Device Removal Routine
2454 * @pdev: PCI device information struct
2455 *
2456 * atl1e_remove is called by the PCI subsystem to alert the driver
2457 * that it should release a PCI device. The could be caused by a
2458 * Hot-Plug event, or because the driver is going to be removed from
2459 * memory.
2460 */
2461 static void __devexit atl1e_remove(struct pci_dev *pdev)
2462 {
2463 struct net_device *netdev = pci_get_drvdata(pdev);
2464 struct atl1e_adapter *adapter = netdev_priv(netdev);
2465
2466 /*
2467 * flush_scheduled work may reschedule our watchdog task, so
2468 * explicitly disable watchdog tasks from being rescheduled
2469 */
2470 set_bit(__AT_DOWN, &adapter->flags);
2471
2472 atl1e_del_timer(adapter);
2473 atl1e_cancel_work(adapter);
2474
2475 unregister_netdev(netdev);
2476 atl1e_free_ring_resources(adapter);
2477 atl1e_force_ps(&adapter->hw);
2478 iounmap(adapter->hw.hw_addr);
2479 pci_release_regions(pdev);
2480 free_netdev(netdev);
2481 pci_disable_device(pdev);
2482 }
2483
2484 /*
2485 * atl1e_io_error_detected - called when PCI error is detected
2486 * @pdev: Pointer to PCI device
2487 * @state: The current pci connection state
2488 *
2489 * This function is called after a PCI bus error affecting
2490 * this device has been detected.
2491 */
2492 static pci_ers_result_t
2493 atl1e_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
2494 {
2495 struct net_device *netdev = pci_get_drvdata(pdev);
2496 struct atl1e_adapter *adapter = netdev_priv(netdev);
2497
2498 netif_device_detach(netdev);
2499
2500 if (netif_running(netdev))
2501 atl1e_down(adapter);
2502
2503 pci_disable_device(pdev);
2504
2505 /* Request a slot slot reset. */
2506 return PCI_ERS_RESULT_NEED_RESET;
2507 }
2508
2509 /*
2510 * atl1e_io_slot_reset - called after the pci bus has been reset.
2511 * @pdev: Pointer to PCI device
2512 *
2513 * Restart the card from scratch, as if from a cold-boot. Implementation
2514 * resembles the first-half of the e1000_resume routine.
2515 */
2516 static pci_ers_result_t atl1e_io_slot_reset(struct pci_dev *pdev)
2517 {
2518 struct net_device *netdev = pci_get_drvdata(pdev);
2519 struct atl1e_adapter *adapter = netdev_priv(netdev);
2520
2521 if (pci_enable_device(pdev)) {
2522 dev_err(&pdev->dev,
2523 "ATL1e: Cannot re-enable PCI device after reset.\n");
2524 return PCI_ERS_RESULT_DISCONNECT;
2525 }
2526 pci_set_master(pdev);
2527
2528 pci_enable_wake(pdev, PCI_D3hot, 0);
2529 pci_enable_wake(pdev, PCI_D3cold, 0);
2530
2531 atl1e_reset_hw(&adapter->hw);
2532
2533 return PCI_ERS_RESULT_RECOVERED;
2534 }
2535
2536 /*
2537 * atl1e_io_resume - called when traffic can start flowing again.
2538 * @pdev: Pointer to PCI device
2539 *
2540 * This callback is called when the error recovery driver tells us that
2541 * its OK to resume normal operation. Implementation resembles the
2542 * second-half of the atl1e_resume routine.
2543 */
2544 static void atl1e_io_resume(struct pci_dev *pdev)
2545 {
2546 struct net_device *netdev = pci_get_drvdata(pdev);
2547 struct atl1e_adapter *adapter = netdev_priv(netdev);
2548
2549 if (netif_running(netdev)) {
2550 if (atl1e_up(adapter)) {
2551 dev_err(&pdev->dev,
2552 "ATL1e: can't bring device back up after reset\n");
2553 return;
2554 }
2555 }
2556
2557 netif_device_attach(netdev);
2558 }
2559
2560 static struct pci_error_handlers atl1e_err_handler = {
2561 .error_detected = atl1e_io_error_detected,
2562 .slot_reset = atl1e_io_slot_reset,
2563 .resume = atl1e_io_resume,
2564 };
2565
2566 static struct pci_driver atl1e_driver = {
2567 .name = atl1e_driver_name,
2568 .id_table = atl1e_pci_tbl,
2569 .probe = atl1e_probe,
2570 .remove = __devexit_p(atl1e_remove),
2571 /* Power Managment Hooks */
2572 #ifdef CONFIG_PM
2573 .suspend = atl1e_suspend,
2574 .resume = atl1e_resume,
2575 #endif
2576 .shutdown = atl1e_shutdown,
2577 .err_handler = &atl1e_err_handler
2578 };
2579
2580 /*
2581 * atl1e_init_module - Driver Registration Routine
2582 *
2583 * atl1e_init_module is the first routine called when the driver is
2584 * loaded. All it does is register with the PCI subsystem.
2585 */
2586 static int __init atl1e_init_module(void)
2587 {
2588 return pci_register_driver(&atl1e_driver);
2589 }
2590
2591 /*
2592 * atl1e_exit_module - Driver Exit Cleanup Routine
2593 *
2594 * atl1e_exit_module is called just before the driver is removed
2595 * from memory.
2596 */
2597 static void __exit atl1e_exit_module(void)
2598 {
2599 pci_unregister_driver(&atl1e_driver);
2600 }
2601
2602 module_init(atl1e_init_module);
2603 module_exit(atl1e_exit_module);
linux-next