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ath5k: fix values for bus error bits in ISR2
[linux-2.6/next.git] / drivers / net / ixgbe / ixgbe.h
blobdc3cc4348d1dc940e2085154103f8764a904408d
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #ifndef _IXGBE_H_
29 #define _IXGBE_H_
30
31 #include <linux/types.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/aer.h>
35
36 #include "ixgbe_type.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_dcb.h"
39 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
40 #define IXGBE_FCOE
41 #include "ixgbe_fcoe.h"
42 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
43 #ifdef CONFIG_IXGBE_DCA
44 #include <linux/dca.h>
45 #endif
46
47 #define PFX "ixgbe: "
48 #define DPRINTK(nlevel, klevel, fmt, args...) \
49 ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
50 printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
51 __func__ , ## args)))
52
53 /* TX/RX descriptor defines */
54 #define IXGBE_DEFAULT_TXD 1024
55 #define IXGBE_MAX_TXD 4096
56 #define IXGBE_MIN_TXD 64
57
58 #define IXGBE_DEFAULT_RXD 1024
59 #define IXGBE_MAX_RXD 4096
60 #define IXGBE_MIN_RXD 64
61
62 /* flow control */
63 #define IXGBE_DEFAULT_FCRTL 0x10000
64 #define IXGBE_MIN_FCRTL 0x40
65 #define IXGBE_MAX_FCRTL 0x7FF80
66 #define IXGBE_DEFAULT_FCRTH 0x20000
67 #define IXGBE_MIN_FCRTH 0x600
68 #define IXGBE_MAX_FCRTH 0x7FFF0
69 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
70 #define IXGBE_MIN_FCPAUSE 0
71 #define IXGBE_MAX_FCPAUSE 0xFFFF
72
73 /* Supported Rx Buffer Sizes */
74 #define IXGBE_RXBUFFER_64 64 /* Used for packet split */
75 #define IXGBE_RXBUFFER_128 128 /* Used for packet split */
76 #define IXGBE_RXBUFFER_256 256 /* Used for packet split */
77 #define IXGBE_RXBUFFER_2048 2048
78 #define IXGBE_RXBUFFER_4096 4096
79 #define IXGBE_RXBUFFER_8192 8192
80 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
81
82 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
83
84 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
85
86 /* How many Rx Buffers do we bundle into one write to the hardware ? */
87 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
88
89 #define IXGBE_TX_FLAGS_CSUM (u32)(1)
90 #define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
91 #define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
92 #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
93 #define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
94 #define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
95 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
96 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
97 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
98
99 /* wrapper around a pointer to a socket buffer,
100 * so a DMA handle can be stored along with the buffer */
101 struct ixgbe_tx_buffer {
102 struct sk_buff *skb;
103 dma_addr_t dma;
104 unsigned long time_stamp;
105 u16 length;
106 u16 next_to_watch;
107 };
108
109 struct ixgbe_rx_buffer {
110 struct sk_buff *skb;
111 dma_addr_t dma;
112 struct page *page;
113 dma_addr_t page_dma;
114 unsigned int page_offset;
115 };
116
117 struct ixgbe_queue_stats {
118 u64 packets;
119 u64 bytes;
120 };
121
122 struct ixgbe_ring {
123 void *desc; /* descriptor ring memory */
124 union {
125 struct ixgbe_tx_buffer *tx_buffer_info;
126 struct ixgbe_rx_buffer *rx_buffer_info;
127 };
128 u8 atr_sample_rate;
129 u8 atr_count;
130 u16 count; /* amount of descriptors */
131 u16 rx_buf_len;
132 u16 next_to_use;
133 u16 next_to_clean;
134
135 u8 queue_index; /* needed for multiqueue queue management */
136
137 u16 head;
138 u16 tail;
139
140 unsigned int total_bytes;
141 unsigned int total_packets;
142
143 #ifdef CONFIG_IXGBE_DCA
144 /* cpu for tx queue */
145 int cpu;
146 #endif
147
148 u16 work_limit; /* max work per interrupt */
149 u16 reg_idx; /* holds the special value that gets
150 * the hardware register offset
151 * associated with this ring, which is
152 * different for DCB and RSS modes
153 */
154
155 struct ixgbe_queue_stats stats;
156 unsigned long reinit_state;
157 u64 rsc_count; /* stat for coalesced packets */
158
159 unsigned int size; /* length in bytes */
160 dma_addr_t dma; /* phys. address of descriptor ring */
161 };
162
163 enum ixgbe_ring_f_enum {
164 RING_F_NONE = 0,
165 RING_F_DCB,
166 RING_F_VMDQ,
167 RING_F_RSS,
168 RING_F_FDIR,
169 #ifdef IXGBE_FCOE
170 RING_F_FCOE,
171 #endif /* IXGBE_FCOE */
172
173 RING_F_ARRAY_SIZE /* must be last in enum set */
174 };
175
176 #define IXGBE_MAX_DCB_INDICES 8
177 #define IXGBE_MAX_RSS_INDICES 16
178 #define IXGBE_MAX_VMDQ_INDICES 16
179 #define IXGBE_MAX_FDIR_INDICES 64
180 #ifdef IXGBE_FCOE
181 #define IXGBE_MAX_FCOE_INDICES 8
182 #endif /* IXGBE_FCOE */
183 struct ixgbe_ring_feature {
184 int indices;
185 int mask;
186 };
187
188 #define MAX_RX_QUEUES 128
189 #define MAX_TX_QUEUES 128
190
191 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
192 ? 8 : 1)
193 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
194
195 /* MAX_MSIX_Q_VECTORS of these are allocated,
196 * but we only use one per queue-specific vector.
197 */
198 struct ixgbe_q_vector {
199 struct ixgbe_adapter *adapter;
200 unsigned int v_idx; /* index of q_vector within array, also used for
201 * finding the bit in EICR and friends that
202 * represents the vector for this ring */
203 struct napi_struct napi;
204 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
205 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
206 u8 rxr_count; /* Rx ring count assigned to this vector */
207 u8 txr_count; /* Tx ring count assigned to this vector */
208 u8 tx_itr;
209 u8 rx_itr;
210 u32 eitr;
211 };
212
213 /* Helper macros to switch between ints/sec and what the register uses.
214 * And yes, it's the same math going both ways. The lowest value
215 * supported by all of the ixgbe hardware is 8.
216 */
217 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
218 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
219 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
220
221 #define IXGBE_DESC_UNUSED(R) \
222 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
223 (R)->next_to_clean - (R)->next_to_use - 1)
224
225 #define IXGBE_RX_DESC_ADV(R, i) \
226 (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
227 #define IXGBE_TX_DESC_ADV(R, i) \
228 (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
229 #define IXGBE_TX_CTXTDESC_ADV(R, i) \
230 (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
231
232 #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
233 #ifdef IXGBE_FCOE
234 /* Use 3K as the baby jumbo frame size for FCoE */
235 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
236 #endif /* IXGBE_FCOE */
237
238 #define OTHER_VECTOR 1
239 #define NON_Q_VECTORS (OTHER_VECTOR)
240
241 #define MAX_MSIX_VECTORS_82599 64
242 #define MAX_MSIX_Q_VECTORS_82599 64
243 #define MAX_MSIX_VECTORS_82598 18
244 #define MAX_MSIX_Q_VECTORS_82598 16
245
246 #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
247 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
248
249 #define MIN_MSIX_Q_VECTORS 2
250 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
251
252 /* board specific private data structure */
253 struct ixgbe_adapter {
254 struct timer_list watchdog_timer;
255 struct vlan_group *vlgrp;
256 u16 bd_number;
257 struct work_struct reset_task;
258 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
259 char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
260 struct ixgbe_dcb_config dcb_cfg;
261 struct ixgbe_dcb_config temp_dcb_cfg;
262 u8 dcb_set_bitmap;
263 enum ixgbe_fc_mode last_lfc_mode;
264
265 /* Interrupt Throttle Rate */
266 u32 itr_setting;
267 u16 eitr_low;
268 u16 eitr_high;
269
270 /* TX */
271 struct ixgbe_ring *tx_ring; /* One per active queue */
272 int num_tx_queues;
273 u64 restart_queue;
274 u64 hw_csum_tx_good;
275 u64 lsc_int;
276 u64 hw_tso_ctxt;
277 u64 hw_tso6_ctxt;
278 u32 tx_timeout_count;
279 bool detect_tx_hung;
280
281 /* RX */
282 struct ixgbe_ring *rx_ring; /* One per active queue */
283 int num_rx_queues;
284 u64 hw_csum_rx_error;
285 u64 hw_rx_no_dma_resources;
286 u64 hw_csum_rx_good;
287 u64 non_eop_descs;
288 int num_msix_vectors;
289 int max_msix_q_vectors; /* true count of q_vectors for device */
290 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
291 struct msix_entry *msix_entries;
292
293 u64 rx_hdr_split;
294 u32 alloc_rx_page_failed;
295 u32 alloc_rx_buff_failed;
296
297 /* Some features need tri-state capability,
298 * thus the additional *_CAPABLE flags.
299 */
300 u32 flags;
301 #define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
302 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
303 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
304 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
305 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
306 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
307 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
308 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
309 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
310 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
311 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
312 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
313 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
314 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
315 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
316 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
317 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
318 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
319 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
320 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
321 #define IXGBE_FLAG_IN_WATCHDOG_TASK (u32)(1 << 23)
322 #define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 24)
323 #define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 25)
324 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 26)
325 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 27)
326 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 28)
327 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 29)
328
329 u32 flags2;
330 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
331 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
332 /* default to trying for four seconds */
333 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
334
335 /* OS defined structs */
336 struct net_device *netdev;
337 struct pci_dev *pdev;
338 struct net_device_stats net_stats;
339
340 u32 test_icr;
341 struct ixgbe_ring test_tx_ring;
342 struct ixgbe_ring test_rx_ring;
343
344 /* structs defined in ixgbe_hw.h */
345 struct ixgbe_hw hw;
346 u16 msg_enable;
347 struct ixgbe_hw_stats stats;
348
349 /* Interrupt Throttle Rate */
350 u32 eitr_param;
351
352 unsigned long state;
353 u64 tx_busy;
354 unsigned int tx_ring_count;
355 unsigned int rx_ring_count;
356
357 u32 link_speed;
358 bool link_up;
359 unsigned long link_check_timeout;
360
361 struct work_struct watchdog_task;
362 struct work_struct sfp_task;
363 struct timer_list sfp_timer;
364 struct work_struct multispeed_fiber_task;
365 struct work_struct sfp_config_module_task;
366 u32 fdir_pballoc;
367 u32 atr_sample_rate;
368 spinlock_t fdir_perfect_lock;
369 struct work_struct fdir_reinit_task;
370 #ifdef IXGBE_FCOE
371 struct ixgbe_fcoe fcoe;
372 #endif /* IXGBE_FCOE */
373 u64 rsc_count;
374 u32 wol;
375 u16 eeprom_version;
376 };
377
378 enum ixbge_state_t {
379 __IXGBE_TESTING,
380 __IXGBE_RESETTING,
381 __IXGBE_DOWN,
382 __IXGBE_FDIR_INIT_DONE,
383 __IXGBE_SFP_MODULE_NOT_FOUND
384 };
385
386 enum ixgbe_boards {
387 board_82598,
388 board_82599,
389 };
390
391 extern struct ixgbe_info ixgbe_82598_info;
392 extern struct ixgbe_info ixgbe_82599_info;
393 #ifdef CONFIG_IXGBE_DCB
394 extern struct dcbnl_rtnl_ops dcbnl_ops;
395 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
396 struct ixgbe_dcb_config *dst_dcb_cfg,
397 int tc_max);
398 #endif
399
400 extern char ixgbe_driver_name[];
401 extern const char ixgbe_driver_version[];
402
403 extern int ixgbe_up(struct ixgbe_adapter *adapter);
404 extern void ixgbe_down(struct ixgbe_adapter *adapter);
405 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
406 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
407 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
408 extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
409 extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
410 extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
411 extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
412 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
413 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
414 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
415 extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
416 extern int ethtool_ioctl(struct ifreq *ifr);
417 extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
418 extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
419 extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
420 extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
421 struct ixgbe_atr_input *input,
422 u8 queue);
423 extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
424 struct ixgbe_atr_input *input,
425 u16 soft_id,
426 u8 queue);
427 extern u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *input, u32 key);
428 extern s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input,
429 u16 vlan_id);
430 extern s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input,
431 u32 src_addr);
432 extern s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input,
433 u32 dst_addr);
434 extern s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
435 u32 src_addr_1, u32 src_addr_2,
436 u32 src_addr_3, u32 src_addr_4);
437 extern s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
438 u32 dst_addr_1, u32 dst_addr_2,
439 u32 dst_addr_3, u32 dst_addr_4);
440 extern s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input,
441 u16 src_port);
442 extern s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input,
443 u16 dst_port);
444 extern s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input,
445 u16 flex_byte);
446 extern s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input,
447 u8 vm_pool);
448 extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input,
449 u8 l4type);
450 extern s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input,
451 u16 *vlan_id);
452 extern s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
453 u32 *src_addr);
454 extern s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
455 u32 *dst_addr);
456 extern s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
457 u32 *src_addr_1, u32 *src_addr_2,
458 u32 *src_addr_3, u32 *src_addr_4);
459 extern s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
460 u32 *dst_addr_1, u32 *dst_addr_2,
461 u32 *dst_addr_3, u32 *dst_addr_4);
462 extern s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
463 u16 *src_port);
464 extern s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
465 u16 *dst_port);
466 extern s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
467 u16 *flex_byte);
468 extern s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input,
469 u8 *vm_pool);
470 extern s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
471 u8 *l4type);
472 #ifdef IXGBE_FCOE
473 extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
474 extern int ixgbe_fso(struct ixgbe_adapter *adapter,
475 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
476 u32 tx_flags, u8 *hdr_len);
477 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
478 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
479 union ixgbe_adv_rx_desc *rx_desc,
480 struct sk_buff *skb);
481 extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
482 struct scatterlist *sgl, unsigned int sgc);
483 extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
484 #endif /* IXGBE_FCOE */
485
486 #endif /* _IXGBE_H_ */
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