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ath5k: fix values for bus error bits in ISR2
[linux-2.6/next.git] / drivers / s390 / cio / qdio_setup.c
blob18d54fc21ce90b43b9e43418a4b3a47e9e6e15ae
1 /*
2 * driver/s390/cio/qdio_setup.c
3 *
4 * qdio queue initialization
5 *
6 * Copyright (C) IBM Corp. 2008
7 * Author(s): Jan Glauber <jang@linux.vnet.ibm.com>
8 */
9 #include <linux/kernel.h>
10 #include <linux/slab.h>
11 #include <asm/qdio.h>
12
13 #include "cio.h"
14 #include "css.h"
15 #include "device.h"
16 #include "ioasm.h"
17 #include "chsc.h"
18 #include "qdio.h"
19 #include "qdio_debug.h"
20
21 static struct kmem_cache *qdio_q_cache;
22
23 /*
24 * qebsm is only available under 64bit but the adapter sets the feature
25 * flag anyway, so we manually override it.
26 */
27 static inline int qebsm_possible(void)
28 {
29 #ifdef CONFIG_64BIT
30 return css_general_characteristics.qebsm;
31 #endif
32 return 0;
33 }
34
35 /*
36 * qib_param_field: pointer to 128 bytes or NULL, if no param field
37 * nr_input_qs: pointer to nr_queues*128 words of data or NULL
38 */
39 static void set_impl_params(struct qdio_irq *irq_ptr,
40 unsigned int qib_param_field_format,
41 unsigned char *qib_param_field,
42 unsigned long *input_slib_elements,
43 unsigned long *output_slib_elements)
44 {
45 struct qdio_q *q;
46 int i, j;
47
48 if (!irq_ptr)
49 return;
50
51 WARN_ON((unsigned long)&irq_ptr->qib & 0xff);
52 irq_ptr->qib.pfmt = qib_param_field_format;
53 if (qib_param_field)
54 memcpy(irq_ptr->qib.parm, qib_param_field,
55 QDIO_MAX_BUFFERS_PER_Q);
56
57 if (!input_slib_elements)
58 goto output;
59
60 for_each_input_queue(irq_ptr, q, i) {
61 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; j++)
62 q->slib->slibe[j].parms =
63 input_slib_elements[i * QDIO_MAX_BUFFERS_PER_Q + j];
64 }
65 output:
66 if (!output_slib_elements)
67 return;
68
69 for_each_output_queue(irq_ptr, q, i) {
70 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; j++)
71 q->slib->slibe[j].parms =
72 output_slib_elements[i * QDIO_MAX_BUFFERS_PER_Q + j];
73 }
74 }
75
76 static int __qdio_allocate_qs(struct qdio_q **irq_ptr_qs, int nr_queues)
77 {
78 struct qdio_q *q;
79 int i;
80
81 for (i = 0; i < nr_queues; i++) {
82 q = kmem_cache_alloc(qdio_q_cache, GFP_KERNEL);
83 if (!q)
84 return -ENOMEM;
85 WARN_ON((unsigned long)q & 0xff);
86
87 q->slib = (struct slib *) __get_free_page(GFP_KERNEL);
88 if (!q->slib) {
89 kmem_cache_free(qdio_q_cache, q);
90 return -ENOMEM;
91 }
92 WARN_ON((unsigned long)q->slib & 0x7ff);
93 irq_ptr_qs[i] = q;
94 }
95 return 0;
96 }
97
98 int qdio_allocate_qs(struct qdio_irq *irq_ptr, int nr_input_qs, int nr_output_qs)
99 {
100 int rc;
101
102 rc = __qdio_allocate_qs(irq_ptr->input_qs, nr_input_qs);
103 if (rc)
104 return rc;
105 rc = __qdio_allocate_qs(irq_ptr->output_qs, nr_output_qs);
106 return rc;
107 }
108
109 static void setup_queues_misc(struct qdio_q *q, struct qdio_irq *irq_ptr,
110 qdio_handler_t *handler, int i)
111 {
112 /* must be cleared by every qdio_establish */
113 memset(q, 0, ((char *)&q->slib) - ((char *)q));
114 memset(q->slib, 0, PAGE_SIZE);
115
116 q->irq_ptr = irq_ptr;
117 q->mask = 1 << (31 - i);
118 q->nr = i;
119 q->handler = handler;
120 }
121
122 static void setup_storage_lists(struct qdio_q *q, struct qdio_irq *irq_ptr,
123 void **sbals_array, int i)
124 {
125 struct qdio_q *prev;
126 int j;
127
128 DBF_HEX(&q, sizeof(void *));
129 q->sl = (struct sl *)((char *)q->slib + PAGE_SIZE / 2);
130
131 /* fill in sbal */
132 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; j++) {
133 q->sbal[j] = *sbals_array++;
134 WARN_ON((unsigned long)q->sbal[j] & 0xff);
135 }
136
137 /* fill in slib */
138 if (i > 0) {
139 prev = (q->is_input_q) ? irq_ptr->input_qs[i - 1]
140 : irq_ptr->output_qs[i - 1];
141 prev->slib->nsliba = (unsigned long)q->slib;
142 }
143
144 q->slib->sla = (unsigned long)q->sl;
145 q->slib->slsba = (unsigned long)&q->slsb.val[0];
146
147 /* fill in sl */
148 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; j++)
149 q->sl->element[j].sbal = (unsigned long)q->sbal[j];
150
151 DBF_EVENT("sl-slsb-sbal");
152 DBF_HEX(q->sl, sizeof(void *));
153 DBF_HEX(&q->slsb, sizeof(void *));
154 DBF_HEX(q->sbal, sizeof(void *));
155 }
156
157 static void setup_queues(struct qdio_irq *irq_ptr,
158 struct qdio_initialize *qdio_init)
159 {
160 struct qdio_q *q;
161 void **input_sbal_array = qdio_init->input_sbal_addr_array;
162 void **output_sbal_array = qdio_init->output_sbal_addr_array;
163 int i;
164
165 for_each_input_queue(irq_ptr, q, i) {
166 DBF_EVENT("in-q:%1d", i);
167 setup_queues_misc(q, irq_ptr, qdio_init->input_handler, i);
168
169 q->is_input_q = 1;
170 setup_storage_lists(q, irq_ptr, input_sbal_array, i);
171 input_sbal_array += QDIO_MAX_BUFFERS_PER_Q;
172
173 if (is_thinint_irq(irq_ptr))
174 tasklet_init(&q->tasklet, tiqdio_inbound_processing,
175 (unsigned long) q);
176 else
177 tasklet_init(&q->tasklet, qdio_inbound_processing,
178 (unsigned long) q);
179 }
180
181 for_each_output_queue(irq_ptr, q, i) {
182 DBF_EVENT("outq:%1d", i);
183 setup_queues_misc(q, irq_ptr, qdio_init->output_handler, i);
184
185 q->is_input_q = 0;
186 setup_storage_lists(q, irq_ptr, output_sbal_array, i);
187 output_sbal_array += QDIO_MAX_BUFFERS_PER_Q;
188
189 tasklet_init(&q->tasklet, qdio_outbound_processing,
190 (unsigned long) q);
191 setup_timer(&q->u.out.timer, (void(*)(unsigned long))
192 &qdio_outbound_timer, (unsigned long)q);
193 }
194 }
195
196 static void process_ac_flags(struct qdio_irq *irq_ptr, unsigned char qdioac)
197 {
198 if (qdioac & AC1_SIGA_INPUT_NEEDED)
199 irq_ptr->siga_flag.input = 1;
200 if (qdioac & AC1_SIGA_OUTPUT_NEEDED)
201 irq_ptr->siga_flag.output = 1;
202 if (qdioac & AC1_SIGA_SYNC_NEEDED)
203 irq_ptr->siga_flag.sync = 1;
204 if (qdioac & AC1_AUTOMATIC_SYNC_ON_THININT)
205 irq_ptr->siga_flag.no_sync_ti = 1;
206 if (qdioac & AC1_AUTOMATIC_SYNC_ON_OUT_PCI)
207 irq_ptr->siga_flag.no_sync_out_pci = 1;
208
209 if (irq_ptr->siga_flag.no_sync_out_pci &&
210 irq_ptr->siga_flag.no_sync_ti)
211 irq_ptr->siga_flag.no_sync_out_ti = 1;
212 }
213
214 static void check_and_setup_qebsm(struct qdio_irq *irq_ptr,
215 unsigned char qdioac, unsigned long token)
216 {
217 if (!(irq_ptr->qib.rflags & QIB_RFLAGS_ENABLE_QEBSM))
218 goto no_qebsm;
219 if (!(qdioac & AC1_SC_QEBSM_AVAILABLE) ||
220 (!(qdioac & AC1_SC_QEBSM_ENABLED)))
221 goto no_qebsm;
222
223 irq_ptr->sch_token = token;
224
225 DBF_EVENT("V=V:1");
226 DBF_EVENT("%8lx", irq_ptr->sch_token);
227 return;
228
229 no_qebsm:
230 irq_ptr->sch_token = 0;
231 irq_ptr->qib.rflags &= ~QIB_RFLAGS_ENABLE_QEBSM;
232 DBF_EVENT("noV=V");
233 }
234
235 /*
236 * If there is a qdio_irq we use the chsc_page and store the information
237 * in the qdio_irq, otherwise we copy it to the specified structure.
238 */
239 int qdio_setup_get_ssqd(struct qdio_irq *irq_ptr,
240 struct subchannel_id *schid,
241 struct qdio_ssqd_desc *data)
242 {
243 struct chsc_ssqd_area *ssqd;
244 int rc;
245
246 DBF_EVENT("getssqd:%4x", schid->sch_no);
247 if (irq_ptr != NULL)
248 ssqd = (struct chsc_ssqd_area *)irq_ptr->chsc_page;
249 else
250 ssqd = (struct chsc_ssqd_area *)__get_free_page(GFP_KERNEL);
251 memset(ssqd, 0, PAGE_SIZE);
252
253 ssqd->request = (struct chsc_header) {
254 .length = 0x0010,
255 .code = 0x0024,
256 };
257 ssqd->first_sch = schid->sch_no;
258 ssqd->last_sch = schid->sch_no;
259 ssqd->ssid = schid->ssid;
260
261 if (chsc(ssqd))
262 return -EIO;
263 rc = chsc_error_from_response(ssqd->response.code);
264 if (rc)
265 return rc;
266
267 if (!(ssqd->qdio_ssqd.flags & CHSC_FLAG_QDIO_CAPABILITY) ||
268 !(ssqd->qdio_ssqd.flags & CHSC_FLAG_VALIDITY) ||
269 (ssqd->qdio_ssqd.sch != schid->sch_no))
270 return -EINVAL;
271
272 if (irq_ptr != NULL)
273 memcpy(&irq_ptr->ssqd_desc, &ssqd->qdio_ssqd,
274 sizeof(struct qdio_ssqd_desc));
275 else {
276 memcpy(data, &ssqd->qdio_ssqd,
277 sizeof(struct qdio_ssqd_desc));
278 free_page((unsigned long)ssqd);
279 }
280 return 0;
281 }
282
283 void qdio_setup_ssqd_info(struct qdio_irq *irq_ptr)
284 {
285 unsigned char qdioac;
286 int rc;
287
288 rc = qdio_setup_get_ssqd(irq_ptr, &irq_ptr->schid, NULL);
289 if (rc) {
290 DBF_ERROR("%4x ssqd ERR", irq_ptr->schid.sch_no);
291 DBF_ERROR("rc:%x", rc);
292 /* all flags set, worst case */
293 qdioac = AC1_SIGA_INPUT_NEEDED | AC1_SIGA_OUTPUT_NEEDED |
294 AC1_SIGA_SYNC_NEEDED;
295 } else
296 qdioac = irq_ptr->ssqd_desc.qdioac1;
297
298 check_and_setup_qebsm(irq_ptr, qdioac, irq_ptr->ssqd_desc.sch_token);
299 process_ac_flags(irq_ptr, qdioac);
300 DBF_EVENT("qdioac:%4x", qdioac);
301 }
302
303 void qdio_release_memory(struct qdio_irq *irq_ptr)
304 {
305 struct qdio_q *q;
306 int i;
307
308 /*
309 * Must check queue array manually since irq_ptr->nr_input_queues /
310 * irq_ptr->nr_input_queues may not yet be set.
311 */
312 for (i = 0; i < QDIO_MAX_QUEUES_PER_IRQ; i++) {
313 q = irq_ptr->input_qs[i];
314 if (q) {
315 free_page((unsigned long) q->slib);
316 kmem_cache_free(qdio_q_cache, q);
317 }
318 }
319 for (i = 0; i < QDIO_MAX_QUEUES_PER_IRQ; i++) {
320 q = irq_ptr->output_qs[i];
321 if (q) {
322 free_page((unsigned long) q->slib);
323 kmem_cache_free(qdio_q_cache, q);
324 }
325 }
326 free_page((unsigned long) irq_ptr->qdr);
327 free_page(irq_ptr->chsc_page);
328 free_page((unsigned long) irq_ptr);
329 }
330
331 static void __qdio_allocate_fill_qdr(struct qdio_irq *irq_ptr,
332 struct qdio_q **irq_ptr_qs,
333 int i, int nr)
334 {
335 irq_ptr->qdr->qdf0[i + nr].sliba =
336 (unsigned long)irq_ptr_qs[i]->slib;
337
338 irq_ptr->qdr->qdf0[i + nr].sla =
339 (unsigned long)irq_ptr_qs[i]->sl;
340
341 irq_ptr->qdr->qdf0[i + nr].slsba =
342 (unsigned long)&irq_ptr_qs[i]->slsb.val[0];
343
344 irq_ptr->qdr->qdf0[i + nr].akey = PAGE_DEFAULT_KEY;
345 irq_ptr->qdr->qdf0[i + nr].bkey = PAGE_DEFAULT_KEY;
346 irq_ptr->qdr->qdf0[i + nr].ckey = PAGE_DEFAULT_KEY;
347 irq_ptr->qdr->qdf0[i + nr].dkey = PAGE_DEFAULT_KEY;
348 }
349
350 static void setup_qdr(struct qdio_irq *irq_ptr,
351 struct qdio_initialize *qdio_init)
352 {
353 int i;
354
355 irq_ptr->qdr->qfmt = qdio_init->q_format;
356 irq_ptr->qdr->iqdcnt = qdio_init->no_input_qs;
357 irq_ptr->qdr->oqdcnt = qdio_init->no_output_qs;
358 irq_ptr->qdr->iqdsz = sizeof(struct qdesfmt0) / 4; /* size in words */
359 irq_ptr->qdr->oqdsz = sizeof(struct qdesfmt0) / 4;
360 irq_ptr->qdr->qiba = (unsigned long)&irq_ptr->qib;
361 irq_ptr->qdr->qkey = PAGE_DEFAULT_KEY;
362
363 for (i = 0; i < qdio_init->no_input_qs; i++)
364 __qdio_allocate_fill_qdr(irq_ptr, irq_ptr->input_qs, i, 0);
365
366 for (i = 0; i < qdio_init->no_output_qs; i++)
367 __qdio_allocate_fill_qdr(irq_ptr, irq_ptr->output_qs, i,
368 qdio_init->no_input_qs);
369 }
370
371 static void setup_qib(struct qdio_irq *irq_ptr,
372 struct qdio_initialize *init_data)
373 {
374 if (qebsm_possible())
375 irq_ptr->qib.rflags |= QIB_RFLAGS_ENABLE_QEBSM;
376
377 irq_ptr->qib.qfmt = init_data->q_format;
378 if (init_data->no_input_qs)
379 irq_ptr->qib.isliba =
380 (unsigned long)(irq_ptr->input_qs[0]->slib);
381 if (init_data->no_output_qs)
382 irq_ptr->qib.osliba =
383 (unsigned long)(irq_ptr->output_qs[0]->slib);
384 memcpy(irq_ptr->qib.ebcnam, init_data->adapter_name, 8);
385 }
386
387 int qdio_setup_irq(struct qdio_initialize *init_data)
388 {
389 struct ciw *ciw;
390 struct qdio_irq *irq_ptr = init_data->cdev->private->qdio_data;
391 int rc;
392
393 memset(irq_ptr, 0, ((char *)&irq_ptr->qdr) - ((char *)irq_ptr));
394 /* wipes qib.ac, required by ar7063 */
395 memset(irq_ptr->qdr, 0, sizeof(struct qdr));
396
397 irq_ptr->int_parm = init_data->int_parm;
398 irq_ptr->nr_input_qs = init_data->no_input_qs;
399 irq_ptr->nr_output_qs = init_data->no_output_qs;
400
401 irq_ptr->schid = ccw_device_get_subchannel_id(init_data->cdev);
402 irq_ptr->cdev = init_data->cdev;
403 setup_queues(irq_ptr, init_data);
404
405 setup_qib(irq_ptr, init_data);
406 qdio_setup_thinint(irq_ptr);
407 set_impl_params(irq_ptr, init_data->qib_param_field_format,
408 init_data->qib_param_field,
409 init_data->input_slib_elements,
410 init_data->output_slib_elements);
411
412 /* fill input and output descriptors */
413 setup_qdr(irq_ptr, init_data);
414
415 /* qdr, qib, sls, slsbs, slibs, sbales are filled now */
416
417 /* get qdio commands */
418 ciw = ccw_device_get_ciw(init_data->cdev, CIW_TYPE_EQUEUE);
419 if (!ciw) {
420 DBF_ERROR("%4x NO EQ", irq_ptr->schid.sch_no);
421 rc = -EINVAL;
422 goto out_err;
423 }
424 irq_ptr->equeue = *ciw;
425
426 ciw = ccw_device_get_ciw(init_data->cdev, CIW_TYPE_AQUEUE);
427 if (!ciw) {
428 DBF_ERROR("%4x NO AQ", irq_ptr->schid.sch_no);
429 rc = -EINVAL;
430 goto out_err;
431 }
432 irq_ptr->aqueue = *ciw;
433
434 /* set new interrupt handler */
435 irq_ptr->orig_handler = init_data->cdev->handler;
436 init_data->cdev->handler = qdio_int_handler;
437 return 0;
438 out_err:
439 qdio_release_memory(irq_ptr);
440 return rc;
441 }
442
443 void qdio_print_subchannel_info(struct qdio_irq *irq_ptr,
444 struct ccw_device *cdev)
445 {
446 char s[80];
447
448 snprintf(s, 80, "qdio: %s %s on SC %x using "
449 "AI:%d QEBSM:%d PCI:%d TDD:%d SIGA:%s%s%s%s%s%s\n",
450 dev_name(&cdev->dev),
451 (irq_ptr->qib.qfmt == QDIO_QETH_QFMT) ? "OSA" :
452 ((irq_ptr->qib.qfmt == QDIO_ZFCP_QFMT) ? "ZFCP" : "HS"),
453 irq_ptr->schid.sch_no,
454 is_thinint_irq(irq_ptr),
455 (irq_ptr->sch_token) ? 1 : 0,
456 (irq_ptr->qib.ac & QIB_AC_OUTBOUND_PCI_SUPPORTED) ? 1 : 0,
457 css_general_characteristics.aif_tdd,
458 (irq_ptr->siga_flag.input) ? "R" : " ",
459 (irq_ptr->siga_flag.output) ? "W" : " ",
460 (irq_ptr->siga_flag.sync) ? "S" : " ",
461 (!irq_ptr->siga_flag.no_sync_ti) ? "A" : " ",
462 (!irq_ptr->siga_flag.no_sync_out_ti) ? "O" : " ",
463 (!irq_ptr->siga_flag.no_sync_out_pci) ? "P" : " ");
464 printk(KERN_INFO "%s", s);
465 }
466
467 int __init qdio_setup_init(void)
468 {
469 qdio_q_cache = kmem_cache_create("qdio_q", sizeof(struct qdio_q),
470 256, 0, NULL);
471 if (!qdio_q_cache)
472 return -ENOMEM;
473
474 /* Check for OSA/FCP thin interrupts (bit 67). */
475 DBF_EVENT("thinint:%1d",
476 (css_general_characteristics.aif_osa) ? 1 : 0);
477
478 /* Check for QEBSM support in general (bit 58). */
479 DBF_EVENT("cssQEBSM:%1d", (qebsm_possible()) ? 1 : 0);
480 return 0;
481 }
482
483 void qdio_setup_exit(void)
484 {
485 kmem_cache_destroy(qdio_q_cache);
486 }
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