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ath5k: fix values for bus error bits in ISR2
[linux-2.6/next.git] / drivers / spi / spi_s3c24xx.c
blobe0d44af4745ad946e0c8aab75dce100610938acd
1 /* linux/drivers/spi/spi_s3c24xx.c
2 *
3 * Copyright (c) 2006 Ben Dooks
4 * Copyright (c) 2006 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12
13 #include <linux/init.h>
14 #include <linux/spinlock.h>
15 #include <linux/workqueue.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/platform_device.h>
22 #include <linux/gpio.h>
23
24 #include <linux/spi/spi.h>
25 #include <linux/spi/spi_bitbang.h>
26
27 #include <asm/io.h>
28 #include <asm/dma.h>
29 #include <mach/hardware.h>
30
31 #include <plat/regs-spi.h>
32 #include <mach/spi.h>
33
34 struct s3c24xx_spi {
35 /* bitbang has to be first */
36 struct spi_bitbang bitbang;
37 struct completion done;
38
39 void __iomem *regs;
40 int irq;
41 int len;
42 int count;
43
44 void (*set_cs)(struct s3c2410_spi_info *spi,
45 int cs, int pol);
46
47 /* data buffers */
48 const unsigned char *tx;
49 unsigned char *rx;
50
51 struct clk *clk;
52 struct resource *ioarea;
53 struct spi_master *master;
54 struct spi_device *curdev;
55 struct device *dev;
56 struct s3c2410_spi_info *pdata;
57 };
58
59 #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
60 #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
61
62 static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
63 {
64 return spi_master_get_devdata(sdev->master);
65 }
66
67 static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
68 {
69 gpio_set_value(spi->pin_cs, pol);
70 }
71
72 static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
73 {
74 struct s3c24xx_spi *hw = to_hw(spi);
75 unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
76 unsigned int spcon;
77
78 switch (value) {
79 case BITBANG_CS_INACTIVE:
80 hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
81 break;
82
83 case BITBANG_CS_ACTIVE:
84 spcon = readb(hw->regs + S3C2410_SPCON);
85
86 if (spi->mode & SPI_CPHA)
87 spcon |= S3C2410_SPCON_CPHA_FMTB;
88 else
89 spcon &= ~S3C2410_SPCON_CPHA_FMTB;
90
91 if (spi->mode & SPI_CPOL)
92 spcon |= S3C2410_SPCON_CPOL_HIGH;
93 else
94 spcon &= ~S3C2410_SPCON_CPOL_HIGH;
95
96 spcon |= S3C2410_SPCON_ENSCK;
97
98 /* write new configration */
99
100 writeb(spcon, hw->regs + S3C2410_SPCON);
101 hw->set_cs(hw->pdata, spi->chip_select, cspol);
102
103 break;
104 }
105 }
106
107 static int s3c24xx_spi_setupxfer(struct spi_device *spi,
108 struct spi_transfer *t)
109 {
110 struct s3c24xx_spi *hw = to_hw(spi);
111 unsigned int bpw;
112 unsigned int hz;
113 unsigned int div;
114
115 bpw = t ? t->bits_per_word : spi->bits_per_word;
116 hz = t ? t->speed_hz : spi->max_speed_hz;
117
118 if (bpw != 8) {
119 dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
120 return -EINVAL;
121 }
122
123 div = clk_get_rate(hw->clk) / hz;
124
125 /* is clk = pclk / (2 * (pre+1)), or is it
126 * clk = (pclk * 2) / ( pre + 1) */
127
128 div /= 2;
129
130 if (div > 0)
131 div -= 1;
132
133 if (div > 255)
134 div = 255;
135
136 dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", div, hz);
137 writeb(div, hw->regs + S3C2410_SPPRE);
138
139 spin_lock(&hw->bitbang.lock);
140 if (!hw->bitbang.busy) {
141 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
142 /* need to ndelay for 0.5 clocktick ? */
143 }
144 spin_unlock(&hw->bitbang.lock);
145
146 return 0;
147 }
148
149 static int s3c24xx_spi_setup(struct spi_device *spi)
150 {
151 int ret;
152
153 ret = s3c24xx_spi_setupxfer(spi, NULL);
154 if (ret < 0) {
155 dev_err(&spi->dev, "setupxfer returned %d\n", ret);
156 return ret;
157 }
158
159 return 0;
160 }
161
162 static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
163 {
164 return hw->tx ? hw->tx[count] : 0;
165 }
166
167 static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
168 {
169 struct s3c24xx_spi *hw = to_hw(spi);
170
171 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
172 t->tx_buf, t->rx_buf, t->len);
173
174 hw->tx = t->tx_buf;
175 hw->rx = t->rx_buf;
176 hw->len = t->len;
177 hw->count = 0;
178
179 init_completion(&hw->done);
180
181 /* send the first byte */
182 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
183
184 wait_for_completion(&hw->done);
185
186 return hw->count;
187 }
188
189 static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
190 {
191 struct s3c24xx_spi *hw = dev;
192 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
193 unsigned int count = hw->count;
194
195 if (spsta & S3C2410_SPSTA_DCOL) {
196 dev_dbg(hw->dev, "data-collision\n");
197 complete(&hw->done);
198 goto irq_done;
199 }
200
201 if (!(spsta & S3C2410_SPSTA_READY)) {
202 dev_dbg(hw->dev, "spi not ready for tx?\n");
203 complete(&hw->done);
204 goto irq_done;
205 }
206
207 hw->count++;
208
209 if (hw->rx)
210 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
211
212 count++;
213
214 if (count < hw->len)
215 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
216 else
217 complete(&hw->done);
218
219 irq_done:
220 return IRQ_HANDLED;
221 }
222
223 static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
224 {
225 /* for the moment, permanently enable the clock */
226
227 clk_enable(hw->clk);
228
229 /* program defaults into the registers */
230
231 writeb(0xff, hw->regs + S3C2410_SPPRE);
232 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
233 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
234
235 if (hw->pdata) {
236 if (hw->set_cs == s3c24xx_spi_gpiocs)
237 gpio_direction_output(hw->pdata->pin_cs, 1);
238
239 if (hw->pdata->gpio_setup)
240 hw->pdata->gpio_setup(hw->pdata, 1);
241 }
242 }
243
244 static int __init s3c24xx_spi_probe(struct platform_device *pdev)
245 {
246 struct s3c2410_spi_info *pdata;
247 struct s3c24xx_spi *hw;
248 struct spi_master *master;
249 struct resource *res;
250 int err = 0;
251
252 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
253 if (master == NULL) {
254 dev_err(&pdev->dev, "No memory for spi_master\n");
255 err = -ENOMEM;
256 goto err_nomem;
257 }
258
259 hw = spi_master_get_devdata(master);
260 memset(hw, 0, sizeof(struct s3c24xx_spi));
261
262 hw->master = spi_master_get(master);
263 hw->pdata = pdata = pdev->dev.platform_data;
264 hw->dev = &pdev->dev;
265
266 if (pdata == NULL) {
267 dev_err(&pdev->dev, "No platform data supplied\n");
268 err = -ENOENT;
269 goto err_no_pdata;
270 }
271
272 platform_set_drvdata(pdev, hw);
273 init_completion(&hw->done);
274
275 /* setup the master state. */
276
277 /* the spi->mode bits understood by this driver: */
278 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
279
280 master->num_chipselect = hw->pdata->num_cs;
281 master->bus_num = pdata->bus_num;
282
283 /* setup the state for the bitbang driver */
284
285 hw->bitbang.master = hw->master;
286 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
287 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
288 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
289 hw->bitbang.master->setup = s3c24xx_spi_setup;
290
291 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
292
293 /* find and map our resources */
294
295 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
296 if (res == NULL) {
297 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
298 err = -ENOENT;
299 goto err_no_iores;
300 }
301
302 hw->ioarea = request_mem_region(res->start, (res->end - res->start)+1,
303 pdev->name);
304
305 if (hw->ioarea == NULL) {
306 dev_err(&pdev->dev, "Cannot reserve region\n");
307 err = -ENXIO;
308 goto err_no_iores;
309 }
310
311 hw->regs = ioremap(res->start, (res->end - res->start)+1);
312 if (hw->regs == NULL) {
313 dev_err(&pdev->dev, "Cannot map IO\n");
314 err = -ENXIO;
315 goto err_no_iomap;
316 }
317
318 hw->irq = platform_get_irq(pdev, 0);
319 if (hw->irq < 0) {
320 dev_err(&pdev->dev, "No IRQ specified\n");
321 err = -ENOENT;
322 goto err_no_irq;
323 }
324
325 err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
326 if (err) {
327 dev_err(&pdev->dev, "Cannot claim IRQ\n");
328 goto err_no_irq;
329 }
330
331 hw->clk = clk_get(&pdev->dev, "spi");
332 if (IS_ERR(hw->clk)) {
333 dev_err(&pdev->dev, "No clock for device\n");
334 err = PTR_ERR(hw->clk);
335 goto err_no_clk;
336 }
337
338 /* setup any gpio we can */
339
340 if (!pdata->set_cs) {
341 if (pdata->pin_cs < 0) {
342 dev_err(&pdev->dev, "No chipselect pin\n");
343 goto err_register;
344 }
345
346 err = gpio_request(pdata->pin_cs, dev_name(&pdev->dev));
347 if (err) {
348 dev_err(&pdev->dev, "Failed to get gpio for cs\n");
349 goto err_register;
350 }
351
352 hw->set_cs = s3c24xx_spi_gpiocs;
353 gpio_direction_output(pdata->pin_cs, 1);
354 } else
355 hw->set_cs = pdata->set_cs;
356
357 s3c24xx_spi_initialsetup(hw);
358
359 /* register our spi controller */
360
361 err = spi_bitbang_start(&hw->bitbang);
362 if (err) {
363 dev_err(&pdev->dev, "Failed to register SPI master\n");
364 goto err_register;
365 }
366
367 return 0;
368
369 err_register:
370 if (hw->set_cs == s3c24xx_spi_gpiocs)
371 gpio_free(pdata->pin_cs);
372
373 clk_disable(hw->clk);
374 clk_put(hw->clk);
375
376 err_no_clk:
377 free_irq(hw->irq, hw);
378
379 err_no_irq:
380 iounmap(hw->regs);
381
382 err_no_iomap:
383 release_resource(hw->ioarea);
384 kfree(hw->ioarea);
385
386 err_no_iores:
387 err_no_pdata:
388 spi_master_put(hw->master);;
389
390 err_nomem:
391 return err;
392 }
393
394 static int __exit s3c24xx_spi_remove(struct platform_device *dev)
395 {
396 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
397
398 platform_set_drvdata(dev, NULL);
399
400 spi_unregister_master(hw->master);
401
402 clk_disable(hw->clk);
403 clk_put(hw->clk);
404
405 free_irq(hw->irq, hw);
406 iounmap(hw->regs);
407
408 if (hw->set_cs == s3c24xx_spi_gpiocs)
409 gpio_free(hw->pdata->pin_cs);
410
411 release_resource(hw->ioarea);
412 kfree(hw->ioarea);
413
414 spi_master_put(hw->master);
415 return 0;
416 }
417
418
419 #ifdef CONFIG_PM
420
421 static int s3c24xx_spi_suspend(struct platform_device *pdev, pm_message_t msg)
422 {
423 struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
424
425 if (hw->pdata && hw->pdata->gpio_setup)
426 hw->pdata->gpio_setup(hw->pdata, 0);
427
428 clk_disable(hw->clk);
429 return 0;
430 }
431
432 static int s3c24xx_spi_resume(struct platform_device *pdev)
433 {
434 struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
435
436 s3c24xx_spi_initialsetup(hw);
437 return 0;
438 }
439
440 #else
441 #define s3c24xx_spi_suspend NULL
442 #define s3c24xx_spi_resume NULL
443 #endif
444
445 MODULE_ALIAS("platform:s3c2410-spi");
446 static struct platform_driver s3c24xx_spi_driver = {
447 .remove = __exit_p(s3c24xx_spi_remove),
448 .suspend = s3c24xx_spi_suspend,
449 .resume = s3c24xx_spi_resume,
450 .driver = {
451 .name = "s3c2410-spi",
452 .owner = THIS_MODULE,
453 },
454 };
455
456 static int __init s3c24xx_spi_init(void)
457 {
458 return platform_driver_probe(&s3c24xx_spi_driver, s3c24xx_spi_probe);
459 }
460
461 static void __exit s3c24xx_spi_exit(void)
462 {
463 platform_driver_unregister(&s3c24xx_spi_driver);
464 }
465
466 module_init(s3c24xx_spi_init);
467 module_exit(s3c24xx_spi_exit);
468
469 MODULE_DESCRIPTION("S3C24XX SPI Driver");
470 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
471 MODULE_LICENSE("GPL");
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