| blob | aa65a72333dd5b2c9fa7512d4d7f66edd1e01676 |
1 /*
2 * linux/arch/arm/kernel/head.S
3 *
4 * Copyright (C) 1994-2002 Russell King
5 * Copyright (c) 2003 ARM Limited
6 * All Rights Reserved
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Kernel startup code for all 32-bit CPUs
13 */
14 #include <linux/linkage.h>
15 #include <linux/init.h>
17 #include <asm/assembler.h>
18 #include <asm/domain.h>
19 #include <asm/ptrace.h>
20 #include <asm/asm-offsets.h>
21 #include <asm/memory.h>
22 #include <asm/thread_info.h>
23 #include <asm/system.h>
24 #include <asm/pgtable.h>
26 #ifdef CONFIG_DEBUG_LL
27 #include <mach/debug-macro.S>
28 #endif
30 /*
31 * swapper_pg_dir is the virtual address of the initial page table.
32 * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must
33 * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect
34 * the least significant 16 bits to be 0x8000, but we could probably
35 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
36 */
37 #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
38 #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
39 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
40 #endif
42 #ifdef CONFIG_ARM_LPAE
43 /* LPAE requires an additional page for the PGD */
44 #define PG_DIR_SIZE 0x5000
45 #define PMD_ORDER 3
46 #else
47 #define PG_DIR_SIZE 0x4000
48 #define PMD_ORDER 2
49 #endif
51 .globl swapper_pg_dir
52 .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
54 .macro pgtbl, rd, phys
55 add \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE
56 .endm
58 #ifdef CONFIG_XIP_KERNEL
59 #define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
60 #define KERNEL_END _edata_loc
61 #else
62 #define KERNEL_START KERNEL_RAM_VADDR
63 #define KERNEL_END _end
64 #endif
66 /*
67 * Kernel startup entry point.
68 * ---------------------------
69 *
70 * This is normally called from the decompressor code. The requirements
71 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
72 * r1 = machine nr, r2 = atags or dtb pointer.
73 *
74 * This code is mostly position independent, so if you link the kernel at
75 * 0xc0008000, you call this at __pa(0xc0008000).
76 *
77 * See linux/arch/arm/tools/mach-types for the complete list of machine
78 * numbers for r1.
79 *
80 * We're trying to keep crap to a minimum; DO NOT add any machine specific
81 * crap here - that's what the boot loader (or in extreme, well justified
82 * circumstances, zImage) is for.
83 */
84 .arm
86 __HEAD
87 ENTRY(stext)
89 THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM.
90 THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
91 THUMB( .thumb ) @ switch to Thumb now.
92 THUMB(1: )
94 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
95 @ and irqs disabled
96 mrc p15, 0, r9, c0, c0 @ get processor id
97 bl __lookup_processor_type @ r5=procinfo r9=cpuid
98 movs r10, r5 @ invalid processor (r5=0)?
99 THUMB( it eq ) @ force fixup-able long branch encoding
100 beq __error_p @ yes, error 'p'
102 #ifndef CONFIG_XIP_KERNEL
103 adr r3, 2f
104 ldmia r3, {r4, r8}
105 sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET)
106 add r8, r8, r4 @ PHYS_OFFSET
107 #else
108 ldr r8, =PLAT_PHYS_OFFSET
109 #endif
111 /*
112 * r1 = machine no, r2 = atags or dtb,
113 * r8 = phys_offset, r9 = cpuid, r10 = procinfo
114 */
115 bl __vet_atags
116 #ifdef CONFIG_SMP_ON_UP
117 bl __fixup_smp
118 #endif
119 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
120 bl __fixup_pv_table
121 #endif
122 bl __create_page_tables
124 /*
125 * The following calls CPU specific code in a position independent
126 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of
127 * xxx_proc_info structure selected by __lookup_processor_type
128 * above. On return, the CPU will be ready for the MMU to be
129 * turned on, and r0 will hold the CPU control register value.
130 */
131 ldr r13, =__mmap_switched @ address to jump to after
132 @ mmu has been enabled
133 adr lr, BSYM(1f) @ return (PIC) address
134 mov r8, r4 @ set TTBR1 to swapper_pg_dir
135 ARM( add pc, r10, #PROCINFO_INITFUNC )
136 THUMB( add r12, r10, #PROCINFO_INITFUNC )
137 THUMB( mov pc, r12 )
138 1: b __enable_mmu
139 ENDPROC(stext)
140 .ltorg
141 #ifndef CONFIG_XIP_KERNEL
142 2: .long .
143 .long PAGE_OFFSET
144 #endif
146 /*
147 * Setup the initial page tables. We only setup the barest
148 * amount which are required to get the kernel running, which
149 * generally means mapping in the kernel code.
150 *
151 * r8 = phys_offset, r9 = cpuid, r10 = procinfo
152 *
153 * Returns:
154 * r0, r3, r5-r7 corrupted
155 * r4 = physical page table address
156 */
157 __create_page_tables:
158 pgtbl r4, r8 @ page table address
160 /*
161 * Clear the swapper page table
162 */
163 mov r0, r4
164 mov r3, #0
165 add r6, r0, #PG_DIR_SIZE
166 1: str r3, [r0], #4
167 str r3, [r0], #4
168 str r3, [r0], #4
169 str r3, [r0], #4
170 teq r0, r6
171 bne 1b
173 #ifdef CONFIG_ARM_LPAE
174 /*
175 * Build the PGD table (first level) to point to the PMD table. A PGD
176 * entry is 64-bit wide.
177 */
178 mov r0, r4
179 add r3, r4, #0x1000 @ first PMD table address
180 orr r3, r3, #3 @ PGD block type
181 mov r6, #4 @ PTRS_PER_PGD
182 mov r7, #1 << (55 - 32) @ L_PGD_SWAPPER
183 1: str r3, [r0], #4 @ set bottom PGD entry bits
184 str r7, [r0], #4 @ set top PGD entry bits
185 add r3, r3, #0x1000 @ next PMD table
186 subs r6, r6, #1
187 bne 1b
189 add r4, r4, #0x1000 @ point to the PMD tables
190 #endif
192 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
194 /*
195 * Create identity mapping to cater for __enable_mmu.
196 * This identity mapping will be removed by paging_init().
197 */
198 adr r0, __enable_mmu_loc
199 ldmia r0, {r3, r5, r6}
200 sub r0, r0, r3 @ virt->phys offset
201 add r5, r5, r0 @ phys __enable_mmu
202 add r6, r6, r0 @ phys __enable_mmu_end
203 mov r5, r5, lsr #SECTION_SHIFT
204 mov r6, r6, lsr #SECTION_SHIFT
206 1: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base
207 str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping
208 cmp r5, r6
209 addlo r5, r5, #1 @ next section
210 blo 1b
212 /*
213 * Now setup the pagetables for our kernel direct
214 * mapped region.
215 */
216 mov r3, pc
217 mov r3, r3, lsr #SECTION_SHIFT
218 orr r3, r7, r3, lsl #SECTION_SHIFT
219 add r0, r4, #(KERNEL_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
220 str r3, [r0, #((KERNEL_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
221 ldr r6, =(KERNEL_END - 1)
222 add r0, r0, #1 << PMD_ORDER
223 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
224 1: cmp r0, r6
225 add r3, r3, #1 << SECTION_SHIFT
226 strls r3, [r0], #1 << PMD_ORDER
227 bls 1b
229 #ifdef CONFIG_XIP_KERNEL
230 /*
231 * Map some ram to cover our .data and .bss areas.
232 */
233 add r3, r8, #TEXT_OFFSET
234 orr r3, r3, r7
235 add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
236 str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> (SECTION_SHIFT - PMD_ORDER)]!
237 ldr r6, =(_end - 1)
238 add r0, r0, #4
239 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
240 1: cmp r0, r6
241 add r3, r3, #1 << 20
242 strls r3, [r0], #4
243 bls 1b
244 #endif
246 /*
247 * Then map boot params address in r2 or the first 1MB (2MB with LPAE)
248 * of ram if boot params address is not specified.
249 */
250 mov r0, r2, lsr #SECTION_SHIFT
251 movs r0, r0, lsl #SECTION_SHIFT
252 moveq r0, r8
253 sub r3, r0, r8
254 add r3, r3, #PAGE_OFFSET
255 add r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
256 orr r6, r7, r0
257 str r6, [r3]
259 #ifdef CONFIG_DEBUG_LL
260 #ifndef CONFIG_DEBUG_ICEDCC
261 /*
262 * Map in IO space for serial debugging.
263 * This allows debug messages to be output
264 * via a serial console before paging_init.
265 */
266 addruart r7, r3
268 mov r3, r3, lsr #SECTION_SHIFT
269 mov r3, r3, lsl #PMD_ORDER
271 add r0, r4, r3
272 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long)
273 cmp r3, #0x0800 @ limit to 512MB
274 movhi r3, #0x0800
275 add r6, r0, r3
276 mov r3, r7, lsr #SECTION_SHIFT
277 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
278 orr r3, r7, r3, lsl #SECTION_SHIFT
279 #ifdef CONFIG_ARM_LPAE
280 mov r7, #1 << (54 - 32) @ XN
281 #endif
282 1: str r3, [r0], #4
283 #ifdef CONFIG_ARM_LPAE
284 str r7, [r0], #4
285 #endif
286 add r3, r3, #1 << SECTION_SHIFT
287 cmp r0, r6
288 blo 1b
290 #else /* CONFIG_DEBUG_ICEDCC */
291 /* we don't need any serial debugging mappings for ICEDCC */
292 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
293 #endif /* !CONFIG_DEBUG_ICEDCC */
295 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
296 /*
297 * If we're using the NetWinder or CATS, we also need to map
298 * in the 16550-type serial port for the debug messages
299 */
300 add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER)
301 orr r3, r7, #0x7c000000
302 str r3, [r0]
303 #endif
304 #ifdef CONFIG_ARCH_RPC
305 /*
306 * Map in screen at 0x02000000 & SCREEN2_BASE
307 * Similar reasons here - for debug. This is
308 * only for Acorn RiscPC architectures.
309 */
310 add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER)
311 orr r3, r7, #0x02000000
312 str r3, [r0]
313 add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER)
314 str r3, [r0]
315 #endif
316 #endif
317 #ifdef CONFIG_ARM_LPAE
318 sub r4, r4, #0x1000 @ point to the PGD table
319 #endif
320 mov pc, lr
321 ENDPROC(__create_page_tables)
322 .ltorg
323 .align
324 __enable_mmu_loc:
325 .long .
326 .long __enable_mmu
327 .long __enable_mmu_end
329 #if defined(CONFIG_SMP)
330 __CPUINIT
331 ENTRY(secondary_startup)
332 /*
333 * Common entry point for secondary CPUs.
334 *
335 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
336 * the processor type - there is no need to check the machine type
337 * as it has already been validated by the primary processor.
338 */
339 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
340 mrc p15, 0, r9, c0, c0 @ get processor id
341 bl __lookup_processor_type
342 movs r10, r5 @ invalid processor?
343 moveq r0, #'p' @ yes, error 'p'
344 THUMB( it eq ) @ force fixup-able long branch encoding
345 beq __error_p
347 /*
348 * Use the page tables supplied from __cpu_up.
349 */
350 adr r4, __secondary_data
351 ldmia r4, {r5, r7, r12} @ address to jump to after
352 sub lr, r4, r5 @ mmu has been enabled
353 ldr r4, [r7, lr] @ get secondary_data.pgdir
354 add r7, r7, #4
355 ldr r8, [r7, lr] @ get secondary_data.swapper_pg_dir
356 adr lr, BSYM(__enable_mmu) @ return address
357 mov r13, r12 @ __secondary_switched address
358 ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor
359 @ (return control reg)
360 THUMB( add r12, r10, #PROCINFO_INITFUNC )
361 THUMB( mov pc, r12 )
362 ENDPROC(secondary_startup)
364 /*
365 * r6 = &secondary_data
366 */
367 ENTRY(__secondary_switched)
368 ldr sp, [r7, #4] @ get secondary_data.stack
369 mov fp, #0
370 b secondary_start_kernel
371 ENDPROC(__secondary_switched)
373 .align
375 .type __secondary_data, %object
376 __secondary_data:
377 .long .
378 .long secondary_data
379 .long __secondary_switched
380 #endif /* defined(CONFIG_SMP) */
384 /*
385 * Setup common bits before finally enabling the MMU. Essentially
386 * this is just loading the page table pointer and domain access
387 * registers.
388 *
389 * r0 = cp#15 control register
390 * r1 = machine ID
391 * r2 = atags or dtb pointer
392 * r4 = page table pointer
393 * r9 = processor ID
394 * r13 = *virtual* address to jump to upon completion
395 */
396 __enable_mmu:
397 #ifdef CONFIG_ALIGNMENT_TRAP
398 orr r0, r0, #CR_A
399 #else
400 bic r0, r0, #CR_A
401 #endif
402 #ifdef CONFIG_CPU_DCACHE_DISABLE
403 bic r0, r0, #CR_C
404 #endif
405 #ifdef CONFIG_CPU_BPREDICT_DISABLE
406 bic r0, r0, #CR_Z
407 #endif
408 #ifdef CONFIG_CPU_ICACHE_DISABLE
409 bic r0, r0, #CR_I
410 #endif
411 #ifdef CONFIG_ARM_LPAE
412 mov r5, #0
413 mcrr p15, 0, r4, r5, c2 @ load TTBR0
414 #else
415 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
416 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
417 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
418 domain_val(DOMAIN_IO, DOMAIN_CLIENT))
419 mcr p15, 0, r5, c3, c0, 0 @ load domain access register
420 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
421 #endif
422 b __turn_mmu_on
423 ENDPROC(__enable_mmu)
425 /*
426 * Enable the MMU. This completely changes the structure of the visible
427 * memory space. You will not be able to trace execution through this.
428 * If you have an enquiry about this, *please* check the linux-arm-kernel
429 * mailing list archives BEFORE sending another post to the list.
430 *
431 * r0 = cp#15 control register
432 * r1 = machine ID
433 * r2 = atags or dtb pointer
434 * r9 = processor ID
435 * r13 = *virtual* address to jump to upon completion
436 *
437 * other registers depend on the function called upon completion
438 */
439 .align 5
440 __turn_mmu_on:
441 mov r0, r0
442 instr_sync
443 mcr p15, 0, r0, c1, c0, 0 @ write control reg
444 mrc p15, 0, r3, c0, c0, 0 @ read id reg
445 instr_sync
446 mov r3, r3
447 mov r3, r13
448 mov pc, r3
449 __enable_mmu_end:
450 ENDPROC(__turn_mmu_on)
453 #ifdef CONFIG_SMP_ON_UP
454 __INIT
455 __fixup_smp:
456 and r3, r9, #0x000f0000 @ architecture version
457 teq r3, #0x000f0000 @ CPU ID supported?
458 bne __fixup_smp_on_up @ no, assume UP
460 bic r3, r9, #0x00ff0000
461 bic r3, r3, #0x0000000f @ mask 0xff00fff0
462 mov r4, #0x41000000
463 orr r4, r4, #0x0000b000
464 orr r4, r4, #0x00000020 @ val 0x4100b020
465 teq r3, r4 @ ARM 11MPCore?
466 moveq pc, lr @ yes, assume SMP
468 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
469 and r0, r0, #0xc0000000 @ multiprocessing extensions and
470 teq r0, #0x80000000 @ not part of a uniprocessor system?
471 moveq pc, lr @ yes, assume SMP
473 __fixup_smp_on_up:
474 adr r0, 1f
475 ldmia r0, {r3 - r5}
476 sub r3, r0, r3
477 add r4, r4, r3
478 add r5, r5, r3
479 b __do_fixup_smp_on_up
480 ENDPROC(__fixup_smp)
482 .align
483 1: .word .
484 .word __smpalt_begin
485 .word __smpalt_end
487 .pushsection .data
488 .globl smp_on_up
489 smp_on_up:
490 ALT_SMP(.long 1)
491 ALT_UP(.long 0)
492 .popsection
493 #endif
495 .text
496 __do_fixup_smp_on_up:
497 cmp r4, r5
498 movhs pc, lr
499 ldmia r4!, {r0, r6}
500 ARM( str r6, [r0, r3] )
501 THUMB( add r0, r0, r3 )
502 #ifdef __ARMEB__
503 THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian.
504 #endif
505 THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords
506 THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3.
507 THUMB( strh r6, [r0] )
508 b __do_fixup_smp_on_up
509 ENDPROC(__do_fixup_smp_on_up)
511 ENTRY(fixup_smp)
512 stmfd sp!, {r4 - r6, lr}
513 mov r4, r0
514 add r5, r0, r1
515 mov r3, #0
516 bl __do_fixup_smp_on_up
517 ldmfd sp!, {r4 - r6, pc}
518 ENDPROC(fixup_smp)
520 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
522 /* __fixup_pv_table - patch the stub instructions with the delta between
523 * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
524 * can be expressed by an immediate shifter operand. The stub instruction
525 * has a form of '(add|sub) rd, rn, #imm'.
526 */
527 __HEAD
528 __fixup_pv_table:
529 adr r0, 1f
530 ldmia r0, {r3-r5, r7}
531 sub r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET
532 add r4, r4, r3 @ adjust table start address
533 add r5, r5, r3 @ adjust table end address
534 add r7, r7, r3 @ adjust __pv_phys_offset address
535 str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset
536 mov r6, r3, lsr #24 @ constant for add/sub instructions
537 teq r3, r6, lsl #24 @ must be 16MiB aligned
538 THUMB( it ne @ cross section branch )
539 bne __error
540 str r6, [r7, #4] @ save to __pv_offset
541 b __fixup_a_pv_table
542 ENDPROC(__fixup_pv_table)
544 .align
545 1: .long .
546 .long __pv_table_begin
547 .long __pv_table_end
548 2: .long __pv_phys_offset
550 .text
551 __fixup_a_pv_table:
552 #ifdef CONFIG_THUMB2_KERNEL
553 lsls r6, #24
554 beq 2f
555 clz r7, r6
556 lsr r6, #24
557 lsl r6, r7
558 bic r6, #0x0080
559 lsrs r7, #1
560 orrcs r6, #0x0080
561 orr r6, r6, r7, lsl #12
562 orr r6, #0x4000
563 b 2f
564 1: add r7, r3
565 ldrh ip, [r7, #2]
566 and ip, 0x8f00
567 orr ip, r6 @ mask in offset bits 31-24
568 strh ip, [r7, #2]
569 2: cmp r4, r5
570 ldrcc r7, [r4], #4 @ use branch for delay slot
571 bcc 1b
572 bx lr
573 #else
574 b 2f
575 1: ldr ip, [r7, r3]
576 bic ip, ip, #0x000000ff
577 orr ip, ip, r6 @ mask in offset bits 31-24
578 str ip, [r7, r3]
579 2: cmp r4, r5
580 ldrcc r7, [r4], #4 @ use branch for delay slot
581 bcc 1b
582 mov pc, lr
583 #endif
584 ENDPROC(__fixup_a_pv_table)
586 ENTRY(fixup_pv_table)
587 stmfd sp!, {r4 - r7, lr}
588 ldr r2, 2f @ get address of __pv_phys_offset
589 mov r3, #0 @ no offset
590 mov r4, r0 @ r0 = table start
591 add r5, r0, r1 @ r1 = table size
592 ldr r6, [r2, #4] @ get __pv_offset
593 bl __fixup_a_pv_table
594 ldmfd sp!, {r4 - r7, pc}
595 ENDPROC(fixup_pv_table)
597 .align
598 2: .long __pv_phys_offset
600 .data
601 .globl __pv_phys_offset
602 .type __pv_phys_offset, %object
603 __pv_phys_offset:
604 .long 0
605 .size __pv_phys_offset, . - __pv_phys_offset
606 __pv_offset:
607 .long 0
608 #endif
610 #include "head-common.S"