arch/arm/mach-at91/at91sam926x_time.c

   1 /*
   2  * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
   3  *
   4  * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
   5  * Revision      2005 M. Nicolas Diremdjian, ATMEL Rousset, France
   6  * Converted to ClockSource/ClockEvents by David Brownell.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/interrupt.h>
  13 #include <linux/irq.h>
  14 #include <linux/kernel.h>
  15 #include <linux/clk.h>
  16 #include <linux/clockchips.h>
  17
  18 #include <asm/mach/time.h>
  19
  20 #include <mach/at91_pit.h>
  21
  22
  23 #define PIT_CPIV(x)     ((x) & AT91_PIT_CPIV)
  24 #define PIT_PICNT(x)    (((x) & AT91_PIT_PICNT) >> 20)
  25
  26 static u32 pit_cycle;           /* write-once */
  27 static u32 pit_cnt;             /* access only w/system irq blocked */
  28
  29
  30 /*
  31  * Clocksource:  just a monotonic counter of MCK/16 cycles.
  32  * We don't care whether or not PIT irqs are enabled.
  33  */
  34 static cycle_t read_pit_clk(struct clocksource *cs)
  35 {
  36         unsigned long flags;
  37         u32 elapsed;
  38         u32 t;
  39
  40         raw_local_irq_save(flags);
  41         elapsed = pit_cnt;
  42         t = at91_sys_read(AT91_PIT_PIIR);
  43         raw_local_irq_restore(flags);
  44
  45         elapsed += PIT_PICNT(t) * pit_cycle;
  46         elapsed += PIT_CPIV(t);
  47         return elapsed;
  48 }
  49
  50 static struct clocksource pit_clk = {
  51         .name           = "pit",
  52         .rating         = 175,
  53         .read           = read_pit_clk,
  54         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  55 };
  56
  57
  58 /*
  59  * Clockevent device:  interrupts every 1/HZ (== pit_cycles * MCK/16)
  60  */
  61 static void
  62 pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
  63 {
  64         switch (mode) {
  65         case CLOCK_EVT_MODE_PERIODIC:
  66                 /* update clocksource counter */
  67                 pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
  68                 at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
  69                                 | AT91_PIT_PITIEN);
  70                 break;
  71         case CLOCK_EVT_MODE_ONESHOT:
  72                 BUG();
  73                 /* FALLTHROUGH */
  74         case CLOCK_EVT_MODE_SHUTDOWN:
  75         case CLOCK_EVT_MODE_UNUSED:
  76                 /* disable irq, leaving the clocksource active */
  77                 at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
  78                 break;
  79         case CLOCK_EVT_MODE_RESUME:
  80                 break;
  81         }
  82 }
  83
  84 static struct clock_event_device pit_clkevt = {
  85         .name           = "pit",
  86         .features       = CLOCK_EVT_FEAT_PERIODIC,
  87         .shift          = 32,
  88         .rating         = 100,
  89         .set_mode       = pit_clkevt_mode,
  90 };
  91
  92
  93 /*
  94  * IRQ handler for the timer.
  95  */
  96 static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
  97 {
  98         /*
  99          * irqs should be disabled here, but as the irq is shared they are only
 100          * guaranteed to be off if the timer irq is registered first.
 101          */
 102         WARN_ON_ONCE(!irqs_disabled());
 103
 104         /* The PIT interrupt may be disabled, and is shared */
 105         if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
 106                         && (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
 107                 unsigned nr_ticks;
 108
 109                 /* Get number of ticks performed before irq, and ack it */
 110                 nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
 111                 do {
 112                         pit_cnt += pit_cycle;
 113                         pit_clkevt.event_handler(&pit_clkevt);
 114                         nr_ticks--;
 115                 } while (nr_ticks);
 116
 117                 return IRQ_HANDLED;
 118         }
 119
 120         return IRQ_NONE;
 121 }
 122
 123 static struct irqaction at91sam926x_pit_irq = {
 124         .name           = "at91_tick",
 125         .flags          = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 126         .handler        = at91sam926x_pit_interrupt
 127 };
 128
 129 static void at91sam926x_pit_reset(void)
 130 {
 131         /* Disable timer and irqs */
 132         at91_sys_write(AT91_PIT_MR, 0);
 133
 134         /* Clear any pending interrupts, wait for PIT to stop counting */
 135         while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0)
 136                 cpu_relax();
 137
 138         /* Start PIT but don't enable IRQ */
 139         at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
 140 }
 141
 142 /*
 143  * Set up both clocksource and clockevent support.
 144  */
 145 static void __init at91sam926x_pit_init(void)
 146 {
 147         unsigned long   pit_rate;
 148         unsigned        bits;
 149
 150         /*
 151          * Use our actual MCK to figure out how many MCK/16 ticks per
 152          * 1/HZ period (instead of a compile-time constant LATCH).
 153          */
 154         pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
 155         pit_cycle = (pit_rate + HZ/2) / HZ;
 156         WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
 157
 158         /* Initialize and enable the timer */
 159         at91sam926x_pit_reset();
 160
 161         /*
 162          * Register clocksource.  The high order bits of PIV are unused,
 163          * so this isn't a 32-bit counter unless we get clockevent irqs.
 164          */
 165         bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
 166         pit_clk.mask = CLOCKSOURCE_MASK(bits);
 167         clocksource_register_hz(&pit_clk, pit_rate);
 168
 169         /* Set up irq handler */
 170         setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
 171
 172         /* Set up and register clockevents */
 173         pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
 174         pit_clkevt.cpumask = cpumask_of(0);
 175         clockevents_register_device(&pit_clkevt);
 176 }
 177
 178 static void at91sam926x_pit_suspend(void)
 179 {
 180         /* Disable timer */
 181         at91_sys_write(AT91_PIT_MR, 0);
 182 }
 183
 184 struct sys_timer at91sam926x_timer = {
 185         .init           = at91sam926x_pit_init,
 186         .suspend        = at91sam926x_pit_suspend,
 187         .resume         = at91sam926x_pit_reset,
 188 };