Merge remote-tracking branch 's5p/for-next'
[linux-2.6/next.git] / arch / arm / mach-at91 / at91sam9g45.c
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1 /*
2 * Chip-specific setup code for the AT91SAM9G45 family
4 * Copyright (C) 2009 Atmel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/pm.h>
16 #include <asm/irq.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
19 #include <mach/at91sam9g45.h>
20 #include <mach/at91_pmc.h>
21 #include <mach/at91_rstc.h>
22 #include <mach/at91_shdwc.h>
23 #include <mach/cpu.h>
25 #include "soc.h"
26 #include "generic.h"
27 #include "clock.h"
29 /* --------------------------------------------------------------------
30 * Clocks
31 * -------------------------------------------------------------------- */
34 * The peripheral clocks.
36 static struct clk pioA_clk = {
37 .name = "pioA_clk",
38 .pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
39 .type = CLK_TYPE_PERIPHERAL,
41 static struct clk pioB_clk = {
42 .name = "pioB_clk",
43 .pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
44 .type = CLK_TYPE_PERIPHERAL,
46 static struct clk pioC_clk = {
47 .name = "pioC_clk",
48 .pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
49 .type = CLK_TYPE_PERIPHERAL,
51 static struct clk pioDE_clk = {
52 .name = "pioDE_clk",
53 .pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
54 .type = CLK_TYPE_PERIPHERAL,
56 static struct clk usart0_clk = {
57 .name = "usart0_clk",
58 .pmc_mask = 1 << AT91SAM9G45_ID_US0,
59 .type = CLK_TYPE_PERIPHERAL,
61 static struct clk usart1_clk = {
62 .name = "usart1_clk",
63 .pmc_mask = 1 << AT91SAM9G45_ID_US1,
64 .type = CLK_TYPE_PERIPHERAL,
66 static struct clk usart2_clk = {
67 .name = "usart2_clk",
68 .pmc_mask = 1 << AT91SAM9G45_ID_US2,
69 .type = CLK_TYPE_PERIPHERAL,
71 static struct clk usart3_clk = {
72 .name = "usart3_clk",
73 .pmc_mask = 1 << AT91SAM9G45_ID_US3,
74 .type = CLK_TYPE_PERIPHERAL,
76 static struct clk mmc0_clk = {
77 .name = "mci0_clk",
78 .pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
79 .type = CLK_TYPE_PERIPHERAL,
81 static struct clk twi0_clk = {
82 .name = "twi0_clk",
83 .pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
84 .type = CLK_TYPE_PERIPHERAL,
86 static struct clk twi1_clk = {
87 .name = "twi1_clk",
88 .pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
89 .type = CLK_TYPE_PERIPHERAL,
91 static struct clk spi0_clk = {
92 .name = "spi0_clk",
93 .pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
94 .type = CLK_TYPE_PERIPHERAL,
96 static struct clk spi1_clk = {
97 .name = "spi1_clk",
98 .pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
99 .type = CLK_TYPE_PERIPHERAL,
101 static struct clk ssc0_clk = {
102 .name = "ssc0_clk",
103 .pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
104 .type = CLK_TYPE_PERIPHERAL,
106 static struct clk ssc1_clk = {
107 .name = "ssc1_clk",
108 .pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
109 .type = CLK_TYPE_PERIPHERAL,
111 static struct clk tcb0_clk = {
112 .name = "tcb0_clk",
113 .pmc_mask = 1 << AT91SAM9G45_ID_TCB,
114 .type = CLK_TYPE_PERIPHERAL,
116 static struct clk pwm_clk = {
117 .name = "pwm_clk",
118 .pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
119 .type = CLK_TYPE_PERIPHERAL,
121 static struct clk tsc_clk = {
122 .name = "tsc_clk",
123 .pmc_mask = 1 << AT91SAM9G45_ID_TSC,
124 .type = CLK_TYPE_PERIPHERAL,
126 static struct clk dma_clk = {
127 .name = "dma_clk",
128 .pmc_mask = 1 << AT91SAM9G45_ID_DMA,
129 .type = CLK_TYPE_PERIPHERAL,
131 static struct clk uhphs_clk = {
132 .name = "uhphs_clk",
133 .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
134 .type = CLK_TYPE_PERIPHERAL,
136 static struct clk lcdc_clk = {
137 .name = "lcdc_clk",
138 .pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
139 .type = CLK_TYPE_PERIPHERAL,
141 static struct clk ac97_clk = {
142 .name = "ac97_clk",
143 .pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
144 .type = CLK_TYPE_PERIPHERAL,
146 static struct clk macb_clk = {
147 .name = "macb_clk",
148 .pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
149 .type = CLK_TYPE_PERIPHERAL,
151 static struct clk isi_clk = {
152 .name = "isi_clk",
153 .pmc_mask = 1 << AT91SAM9G45_ID_ISI,
154 .type = CLK_TYPE_PERIPHERAL,
156 static struct clk udphs_clk = {
157 .name = "udphs_clk",
158 .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
159 .type = CLK_TYPE_PERIPHERAL,
161 static struct clk mmc1_clk = {
162 .name = "mci1_clk",
163 .pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
164 .type = CLK_TYPE_PERIPHERAL,
167 /* Video decoder clock - Only for sam9m10/sam9m11 */
168 static struct clk vdec_clk = {
169 .name = "vdec_clk",
170 .pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
171 .type = CLK_TYPE_PERIPHERAL,
174 static struct clk *periph_clocks[] __initdata = {
175 &pioA_clk,
176 &pioB_clk,
177 &pioC_clk,
178 &pioDE_clk,
179 &usart0_clk,
180 &usart1_clk,
181 &usart2_clk,
182 &usart3_clk,
183 &mmc0_clk,
184 &twi0_clk,
185 &twi1_clk,
186 &spi0_clk,
187 &spi1_clk,
188 &ssc0_clk,
189 &ssc1_clk,
190 &tcb0_clk,
191 &pwm_clk,
192 &tsc_clk,
193 &dma_clk,
194 &uhphs_clk,
195 &lcdc_clk,
196 &ac97_clk,
197 &macb_clk,
198 &isi_clk,
199 &udphs_clk,
200 &mmc1_clk,
201 // irq0
204 static struct clk_lookup periph_clocks_lookups[] = {
205 /* One additional fake clock for ohci */
206 CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
207 CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
208 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
209 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
210 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
211 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
212 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
213 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
214 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
215 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
216 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
217 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
220 static struct clk_lookup usart_clocks_lookups[] = {
221 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
222 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
223 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
224 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
225 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
229 * The two programmable clocks.
230 * You must configure pin multiplexing to bring these signals out.
232 static struct clk pck0 = {
233 .name = "pck0",
234 .pmc_mask = AT91_PMC_PCK0,
235 .type = CLK_TYPE_PROGRAMMABLE,
236 .id = 0,
238 static struct clk pck1 = {
239 .name = "pck1",
240 .pmc_mask = AT91_PMC_PCK1,
241 .type = CLK_TYPE_PROGRAMMABLE,
242 .id = 1,
245 static void __init at91sam9g45_register_clocks(void)
247 int i;
249 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
250 clk_register(periph_clocks[i]);
252 clkdev_add_table(periph_clocks_lookups,
253 ARRAY_SIZE(periph_clocks_lookups));
254 clkdev_add_table(usart_clocks_lookups,
255 ARRAY_SIZE(usart_clocks_lookups));
257 if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
258 clk_register(&vdec_clk);
260 clk_register(&pck0);
261 clk_register(&pck1);
264 static struct clk_lookup console_clock_lookup;
266 void __init at91sam9g45_set_console_clock(int id)
268 if (id >= ARRAY_SIZE(usart_clocks_lookups))
269 return;
271 console_clock_lookup.con_id = "usart";
272 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
273 clkdev_add(&console_clock_lookup);
276 /* --------------------------------------------------------------------
277 * GPIO
278 * -------------------------------------------------------------------- */
280 static struct at91_gpio_bank at91sam9g45_gpio[] = {
282 .id = AT91SAM9G45_ID_PIOA,
283 .offset = AT91_PIOA,
284 .clock = &pioA_clk,
285 }, {
286 .id = AT91SAM9G45_ID_PIOB,
287 .offset = AT91_PIOB,
288 .clock = &pioB_clk,
289 }, {
290 .id = AT91SAM9G45_ID_PIOC,
291 .offset = AT91_PIOC,
292 .clock = &pioC_clk,
293 }, {
294 .id = AT91SAM9G45_ID_PIODE,
295 .offset = AT91_PIOD,
296 .clock = &pioDE_clk,
297 }, {
298 .id = AT91SAM9G45_ID_PIODE,
299 .offset = AT91_PIOE,
300 .clock = &pioDE_clk,
304 static void at91sam9g45_reset(void)
306 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
309 static void at91sam9g45_poweroff(void)
311 at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
315 /* --------------------------------------------------------------------
316 * AT91SAM9G45 processor initialization
317 * -------------------------------------------------------------------- */
319 static void __init at91sam9g45_map_io(void)
321 at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
324 static void __init at91sam9g45_initialize(void)
326 at91_arch_reset = at91sam9g45_reset;
327 pm_power_off = at91sam9g45_poweroff;
328 at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
330 /* Register GPIO subsystem */
331 at91_gpio_init(at91sam9g45_gpio, 5);
334 /* --------------------------------------------------------------------
335 * Interrupt initialization
336 * -------------------------------------------------------------------- */
339 * The default interrupt priority levels (0 = lowest, 7 = highest).
341 static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
342 7, /* Advanced Interrupt Controller (FIQ) */
343 7, /* System Peripherals */
344 1, /* Parallel IO Controller A */
345 1, /* Parallel IO Controller B */
346 1, /* Parallel IO Controller C */
347 1, /* Parallel IO Controller D and E */
349 5, /* USART 0 */
350 5, /* USART 1 */
351 5, /* USART 2 */
352 5, /* USART 3 */
353 0, /* Multimedia Card Interface 0 */
354 6, /* Two-Wire Interface 0 */
355 6, /* Two-Wire Interface 1 */
356 5, /* Serial Peripheral Interface 0 */
357 5, /* Serial Peripheral Interface 1 */
358 4, /* Serial Synchronous Controller 0 */
359 4, /* Serial Synchronous Controller 1 */
360 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
361 0, /* Pulse Width Modulation Controller */
362 0, /* Touch Screen Controller */
363 0, /* DMA Controller */
364 2, /* USB Host High Speed port */
365 3, /* LDC Controller */
366 5, /* AC97 Controller */
367 3, /* Ethernet */
368 0, /* Image Sensor Interface */
369 2, /* USB Device High speed port */
371 0, /* Multimedia Card Interface 1 */
373 0, /* Advanced Interrupt Controller (IRQ0) */
376 struct at91_init_soc __initdata at91sam9g45_soc = {
377 .map_io = at91sam9g45_map_io,
378 .default_irq_priority = at91sam9g45_default_irq_priority,
379 .register_clocks = at91sam9g45_register_clocks,
380 .init = at91sam9g45_initialize,