2 * TI DAVINCI dma definitions
4 * Copyright (C) 2006-2009 Texas Instruments.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
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24 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 * This EDMA3 programming framework exposes two basic kinds of resource:
31 * Channel Triggers transfers, usually from a hardware event but
32 * also manually or by "chaining" from DMA completions.
33 * Each channel is coupled to a Parameter RAM (PaRAM) slot.
35 * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
36 * "set"), source and destination addresses, a link to a
37 * next PaRAM slot (if any), options for the transfer, and
38 * instructions for updating those addresses. There are
39 * more than twice as many slots as event channels.
41 * Each PaRAM set describes a sequence of transfers, either for one large
42 * buffer or for several discontiguous smaller buffers. An EDMA transfer
43 * is driven only from a channel, which performs the transfers specified
44 * in its PaRAM slot until there are no more transfers. When that last
45 * transfer completes, the "link" field may be used to reload the channel's
46 * PaRAM slot with a new transfer descriptor.
48 * The EDMA Channel Controller (CC) maps requests from channels into physical
49 * Transfer Controller (TC) requests when the channel triggers (by hardware
50 * or software events, or by chaining). The two physical DMA channels provided
51 * by the TCs are thus shared by many logical channels.
53 * DaVinci hardware also has a "QDMA" mechanism which is not currently
54 * supported through this interface. (DSP firmware uses it though.)
60 /* PaRAM slots are laid out like this */
66 unsigned int src_dst_bidx
;
67 unsigned int link_bcntrld
;
68 unsigned int src_dst_cidx
;
72 #define CCINT0_INTERRUPT 16
73 #define CCERRINT_INTERRUPT 17
74 #define TCERRINT0_INTERRUPT 18
75 #define TCERRINT1_INTERRUPT 19
77 /* fields in edmacc_param.opt */
80 #define SYNCDIM BIT(2)
82 #define EDMA_FWID (0x07 << 8)
83 #define TCCMODE BIT(11)
84 #define EDMA_TCC(t) ((t) << 12)
85 #define TCINTEN BIT(20)
86 #define ITCINTEN BIT(21)
87 #define TCCHEN BIT(22)
88 #define ITCCHEN BIT(23)
90 #define TRWORD (0x7<<2)
91 #define PAENTRY (0x1ff<<5)
93 /* Drivers should avoid using these symbolic names for dm644x
94 * channels, and use platform_device IORESOURCE_DMA resources
95 * instead. (Other DaVinci chips have different peripherals
96 * and thus have different DMA channel mappings.)
98 #define DAVINCI_DMA_MCBSP_TX 2
99 #define DAVINCI_DMA_MCBSP_RX 3
100 #define DAVINCI_DMA_VPSS_HIST 4
101 #define DAVINCI_DMA_VPSS_H3A 5
102 #define DAVINCI_DMA_VPSS_PRVU 6
103 #define DAVINCI_DMA_VPSS_RSZ 7
104 #define DAVINCI_DMA_IMCOP_IMXINT 8
105 #define DAVINCI_DMA_IMCOP_VLCDINT 9
106 #define DAVINCI_DMA_IMCO_PASQINT 10
107 #define DAVINCI_DMA_IMCOP_DSQINT 11
108 #define DAVINCI_DMA_SPI_SPIX 16
109 #define DAVINCI_DMA_SPI_SPIR 17
110 #define DAVINCI_DMA_UART0_URXEVT0 18
111 #define DAVINCI_DMA_UART0_UTXEVT0 19
112 #define DAVINCI_DMA_UART1_URXEVT1 20
113 #define DAVINCI_DMA_UART1_UTXEVT1 21
114 #define DAVINCI_DMA_UART2_URXEVT2 22
115 #define DAVINCI_DMA_UART2_UTXEVT2 23
116 #define DAVINCI_DMA_MEMSTK_MSEVT 24
117 #define DAVINCI_DMA_MMCRXEVT 26
118 #define DAVINCI_DMA_MMCTXEVT 27
119 #define DAVINCI_DMA_I2C_ICREVT 28
120 #define DAVINCI_DMA_I2C_ICXEVT 29
121 #define DAVINCI_DMA_GPIO_GPINT0 32
122 #define DAVINCI_DMA_GPIO_GPINT1 33
123 #define DAVINCI_DMA_GPIO_GPINT2 34
124 #define DAVINCI_DMA_GPIO_GPINT3 35
125 #define DAVINCI_DMA_GPIO_GPINT4 36
126 #define DAVINCI_DMA_GPIO_GPINT5 37
127 #define DAVINCI_DMA_GPIO_GPINT6 38
128 #define DAVINCI_DMA_GPIO_GPINT7 39
129 #define DAVINCI_DMA_GPIO_GPBNKINT0 40
130 #define DAVINCI_DMA_GPIO_GPBNKINT1 41
131 #define DAVINCI_DMA_GPIO_GPBNKINT2 42
132 #define DAVINCI_DMA_GPIO_GPBNKINT3 43
133 #define DAVINCI_DMA_GPIO_GPBNKINT4 44
134 #define DAVINCI_DMA_TIMER0_TINT0 48
135 #define DAVINCI_DMA_TIMER1_TINT1 49
136 #define DAVINCI_DMA_TIMER2_TINT2 50
137 #define DAVINCI_DMA_TIMER3_TINT3 51
138 #define DAVINCI_DMA_PWM0 52
139 #define DAVINCI_DMA_PWM1 53
140 #define DAVINCI_DMA_PWM2 54
142 /* DA830 specific EDMA3 information */
143 #define EDMA_DA830_NUM_DMACH 32
144 #define EDMA_DA830_NUM_TCC 32
145 #define EDMA_DA830_NUM_PARAMENTRY 128
146 #define EDMA_DA830_NUM_EVQUE 2
147 #define EDMA_DA830_NUM_TC 2
148 #define EDMA_DA830_CHMAP_EXIST 0
149 #define EDMA_DA830_NUM_REGIONS 4
150 #define DA830_DMACH2EVENT_MAP0 0x000FC03Fu
151 #define DA830_DMACH2EVENT_MAP1 0x00000000u
152 #define DA830_EDMA_ARM_OWN 0x30FFCCFFu
154 /*ch_status paramater of callback function possible values*/
155 #define DMA_COMPLETE 1
156 #define DMA_CC_ERROR 2
157 #define DMA_TC1_ERROR 3
158 #define DMA_TC2_ERROR 4
182 enum sync_dimension
{
187 #define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
188 #define EDMA_CTLR(i) ((i) >> 16)
189 #define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
191 #define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
192 #define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
193 #define EDMA_CONT_PARAMS_ANY 1001
194 #define EDMA_CONT_PARAMS_FIXED_EXACT 1002
195 #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
197 #define EDMA_MAX_CC 2
199 /* alloc/free DMA channels and their dedicated parameter RAM slots */
200 int edma_alloc_channel(int channel
,
201 void (*callback
)(unsigned channel
, u16 ch_status
, void *data
),
202 void *data
, enum dma_event_q
);
203 void edma_free_channel(unsigned channel
);
205 /* alloc/free parameter RAM slots */
206 int edma_alloc_slot(unsigned ctlr
, int slot
);
207 void edma_free_slot(unsigned slot
);
209 /* alloc/free a set of contiguous parameter RAM slots */
210 int edma_alloc_cont_slots(unsigned ctlr
, unsigned int id
, int slot
, int count
);
211 int edma_free_cont_slots(unsigned slot
, int count
);
213 /* calls that operate on part of a parameter RAM slot */
214 void edma_set_src(unsigned slot
, dma_addr_t src_port
,
215 enum address_mode mode
, enum fifo_width
);
216 void edma_set_dest(unsigned slot
, dma_addr_t dest_port
,
217 enum address_mode mode
, enum fifo_width
);
218 void edma_get_position(unsigned slot
, dma_addr_t
*src
, dma_addr_t
*dst
);
219 void edma_set_src_index(unsigned slot
, s16 src_bidx
, s16 src_cidx
);
220 void edma_set_dest_index(unsigned slot
, s16 dest_bidx
, s16 dest_cidx
);
221 void edma_set_transfer_params(unsigned slot
, u16 acnt
, u16 bcnt
, u16 ccnt
,
222 u16 bcnt_rld
, enum sync_dimension sync_mode
);
223 void edma_link(unsigned from
, unsigned to
);
224 void edma_unlink(unsigned from
);
226 /* calls that operate on an entire parameter RAM slot */
227 void edma_write_slot(unsigned slot
, const struct edmacc_param
*params
);
228 void edma_read_slot(unsigned slot
, struct edmacc_param
*params
);
230 /* channel control operations */
231 int edma_start(unsigned channel
);
232 void edma_stop(unsigned channel
);
233 void edma_clean_channel(unsigned channel
);
234 void edma_clear_event(unsigned channel
);
235 void edma_pause(unsigned channel
);
236 void edma_resume(unsigned channel
);
238 struct edma_rsv_info
{
240 const s16 (*rsv_chans
)[2];
241 const s16 (*rsv_slots
)[2];
244 /* platform_data for EDMA driver */
245 struct edma_soc_info
{
247 /* how many dma resources of each type */
253 enum dma_event_q default_queue
;
255 /* Resource reservation for other cores */
256 struct edma_rsv_info
*rsv
;
258 const s8 (*queue_tc_mapping
)[2];
259 const s8 (*queue_priority_mapping
)[2];