2 * Table of the DAVINCI register configurations for the PINMUX combinations
4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
6 * Based on linux/include/asm-arm/arch-omap/mux.h:
7 * Copyright (C) 2003 - 2005 Nokia Corporation
9 * Written by Tony Lindgren
11 * 2007 (c) MontaVista Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
16 * Copyright (C) 2008 Texas Instruments.
19 #ifndef __INC_MACH_MUX_H
20 #define __INC_MACH_MUX_H
24 const char *mux_reg_name
;
25 const unsigned char mux_reg
;
26 const unsigned char mask_offset
;
27 const unsigned char mask
;
28 const unsigned char mode
;
32 enum davinci_dm644x_index
{
33 /* ATA and HDDIR functions */
78 /* EMAC and MDIO function */
81 /* GPIO3V[0:16] pins */
98 enum davinci_dm646x_index
{
110 DM646X_STSOMUX_DISABLE
,
111 DM646X_STSIMUX_DISABLE
,
112 DM646X_PTSOMUX_DISABLE
,
113 DM646X_PTSIMUX_DISABLE
,
118 DM646X_PTSOMUX_PARALLEL
,
119 DM646X_PTSIMUX_PARALLEL
,
120 DM646X_PTSOMUX_SERIAL
,
121 DM646X_PTSIMUX_SERIAL
,
124 enum davinci_dm355_index
{
155 DM355_INT_EDMA_TC0_ERR
,
156 DM355_INT_EDMA_TC1_ERR
,
158 /* EDMA event muxing */
165 DM355_VOUT_FIELD_G70
,
170 /* Video In Pin Mux */
180 enum davinci_dm365_index
{
309 DM365_VOUT_FIELD_G81
,
321 DM365_INT_EDMA_TC0_ERR
,
322 DM365_INT_EDMA_TC1_ERR
,
323 DM365_INT_EDMA_TC2_ERR
,
324 DM365_INT_EDMA_TC3_ERR
,
326 DM365_INT_EMAC_RXTHRESH
,
327 DM365_INT_EMAC_RXPULSE
,
328 DM365_INT_EMAC_TXPULSE
,
329 DM365_INT_EMAC_MISCPULSE
,
330 DM365_INT_IMX0_ENABLE
,
331 DM365_INT_IMX0_DISABLE
,
332 DM365_INT_HDVICP_ENABLE
,
333 DM365_INT_HDVICP_DISABLE
,
334 DM365_INT_IMX1_ENABLE
,
335 DM365_INT_IMX1_DISABLE
,
336 DM365_INT_NSF_ENABLE
,
337 DM365_INT_NSF_DISABLE
,
339 /* EDMA event muxing */
495 DA830_RMII_MHZ_50_CLK
,
702 DA830_NLCD_AC_ENB_CS
,
751 enum davinci_da850_index
{
803 DA850_RMII_MHZ_50_CLK
,
850 DA850_NLCD_AC_ENB_CS
,
852 /* MMC/SD0 function */
860 /* EMIF2.5/EMIFA function */
923 enum davinci_tnetv107x_index
{
947 TNETV107X_BOOT_STRP_0
,
949 TNETV107X_BOOT_STRP_1
,
962 TNETV107X_SDIO1_DATA3_0
,
965 TNETV107X_SDIO1_DATA2_0
,
968 TNETV107X_SDIO1_DATA1_0
,
971 TNETV107X_SDIO1_DATA0_0
,
974 TNETV107X_SDIO1_CMD_0
,
977 TNETV107X_SDIO1_CLK_0
,
980 TNETV107X_SYS_PLL_CLK
,
984 TNETV107X_TDM_PLL_CLK
,
986 TNETV107X_ETH_PHY_CLK
,
1008 TNETV107X_SDIO1_DATA3_1
,
1010 TNETV107X_SDIO1_DATA2_1
,
1012 TNETV107X_SDIO1_DATA1_1
,
1014 TNETV107X_SDIO1_DATA0_1
,
1016 TNETV107X_SDIO1_CMD_1
,
1018 TNETV107X_SDIO1_CLK_1
,
1020 TNETV107X_BOOT_STRP_2
,
1026 TNETV107X_BOOT_STRP_3
,
1027 TNETV107X_ASR_WE_DQM0
,
1029 TNETV107X_LCD_PD17_0
,
1030 TNETV107X_ASR_WE_DQM1
,
1031 TNETV107X_ASR_BA0_0
,
1032 TNETV107X_VLYNQ_CLK
,
1034 TNETV107X_LCD_PD19_0
,
1035 TNETV107X_VLYNQ_RXD0
,
1037 TNETV107X_LCD_PD20_0
,
1038 TNETV107X_VLYNQ_RXD1
,
1040 TNETV107X_LCD_PD21_0
,
1041 TNETV107X_VLYNQ_TXD0
,
1043 TNETV107X_LCD_PD22_0
,
1044 TNETV107X_VLYNQ_TXD1
,
1046 TNETV107X_LCD_PD23_0
,
1047 TNETV107X_SDIO0_CLK
,
1049 TNETV107X_SDIO0_CMD
,
1051 TNETV107X_SDIO0_DATA0
,
1053 TNETV107X_SDIO0_DATA1
,
1055 TNETV107X_SDIO0_DATA2
,
1057 TNETV107X_SDIO0_DATA3
,
1071 TNETV107X_KEYPAD_R0
,
1072 TNETV107X_KEYPAD_R1
,
1073 TNETV107X_KEYPAD_R2
,
1074 TNETV107X_KEYPAD_R3
,
1075 TNETV107X_KEYPAD_R4
,
1076 TNETV107X_KEYPAD_R5
,
1077 TNETV107X_KEYPAD_R6
,
1079 TNETV107X_KEYPAD_R7
,
1081 TNETV107X_KEYPAD_C0
,
1082 TNETV107X_KEYPAD_C1
,
1083 TNETV107X_KEYPAD_C2
,
1084 TNETV107X_KEYPAD_C3
,
1085 TNETV107X_KEYPAD_C4
,
1086 TNETV107X_KEYPAD_C5
,
1087 TNETV107X_KEYPAD_C6
,
1089 TNETV107X_TEST_CLK_IN
,
1090 TNETV107X_KEYPAD_C7
,
1094 TNETV107X_LCD_PD20_1
,
1097 TNETV107X_LCD_PD21_1
,
1100 TNETV107X_LCD_PD22_1
,
1102 TNETV107X_SCC_RESETN
,
1103 TNETV107X_LCD_PD23_1
,
1106 TNETV107X_UART2_CTS
,
1112 TNETV107X_UART2_RTS
,
1116 TNETV107X_UART0_CTS
,
1118 TNETV107X_UART0_RTS
,
1122 TNETV107X_LCD_AC_NCS
,
1123 TNETV107X_LCD_HSYNC_RNW
,
1124 TNETV107X_LCD_VSYNC_A0
,
1126 TNETV107X_LCD_PD16_0
,
1127 TNETV107X_LCD_PCLK_E
,
1141 TNETV107X_ASR_BA0_1
,
1158 TNETV107X_LCD_PD20_2
,
1159 TNETV107X_TDM_CLK_IN_2
,
1161 TNETV107X_LCD_PD21_2
,
1162 TNETV107X_24M_CLK_OUT_1
,
1164 TNETV107X_LCD_PD22_2
,
1166 TNETV107X_LCD_PD23_2
,
1168 TNETV107X_LCD_PD16_1
,
1169 TNETV107X_USB0_RXERR
,
1171 TNETV107X_LCD_PD17_1
,
1172 TNETV107X_TDM_CLK_IN_1
,
1175 TNETV107X_24M_CLK_OUT_2
,
1177 TNETV107X_LCD_PD19_1
,
1178 TNETV107X_USB1_RXERR
,
1179 TNETV107X_ETH_PLL_CLK
,
1182 TNETV107X_AIC_MUTE_STAT_N
,
1184 TNETV107X_AIC_HNS_EN_N
,
1186 TNETV107X_AIC_HDS_EN_STAT_N
,
1188 TNETV107X_AIC_HNF_EN_STAT_N
,
1192 #define PINMUX(x) (4 * (x))
1194 #ifdef CONFIG_DAVINCI_MUX
1195 /* setup pin muxing */
1196 extern int davinci_cfg_reg(unsigned long reg_cfg
);
1197 extern int davinci_cfg_reg_list(const short pins
[]);
1199 /* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
1200 static inline int davinci_cfg_reg(unsigned long reg_cfg
) { return 0; }
1201 static inline int davinci_cfg_reg_list(const short pins
[])
1207 #endif /* __INC_MACH_MUX_H */