arch/arm/mach-imx/mach-pcm043.c

   1 /*
   2  *  Copyright (C) 2009 Sascha Hauer, Pengutronix
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/types.h>
  16 #include <linux/init.h>
  17
  18 #include <linux/platform_device.h>
  19 #include <linux/mtd/physmap.h>
  20 #include <linux/mtd/plat-ram.h>
  21 #include <linux/memory.h>
  22 #include <linux/gpio.h>
  23 #include <linux/smc911x.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/delay.h>
  26 #include <linux/i2c.h>
  27 #include <linux/i2c/at24.h>
  28 #include <linux/usb/otg.h>
  29 #include <linux/usb/ulpi.h>
  30
  31 #include <asm/mach-types.h>
  32 #include <asm/mach/arch.h>
  33 #include <asm/mach/time.h>
  34 #include <asm/mach/map.h>
  35
  36 #include <mach/hardware.h>
  37 #include <mach/common.h>
  38 #include <mach/iomux-mx35.h>
  39 #include <mach/ulpi.h>
  40 #include <mach/audmux.h>
  41
  42 #include "devices-imx35.h"
  43
  44 static const struct fb_videomode fb_modedb[] = {
  45         {
  46                 /* 240x320 @ 60 Hz */
  47                 .name           = "Sharp-LQ035Q7",
  48                 .refresh        = 60,
  49                 .xres           = 240,
  50                 .yres           = 320,
  51                 .pixclock       = 185925,
  52                 .left_margin    = 9,
  53                 .right_margin   = 16,
  54                 .upper_margin   = 7,
  55                 .lower_margin   = 9,
  56                 .hsync_len      = 1,
  57                 .vsync_len      = 1,
  58                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
  59                 .vmode          = FB_VMODE_NONINTERLACED,
  60                 .flag           = 0,
  61         }, {
  62                 /* 240x320 @ 60 Hz */
  63                 .name           = "TX090",
  64                 .refresh        = 60,
  65                 .xres           = 240,
  66                 .yres           = 320,
  67                 .pixclock       = 38255,
  68                 .left_margin    = 144,
  69                 .right_margin   = 0,
  70                 .upper_margin   = 7,
  71                 .lower_margin   = 40,
  72                 .hsync_len      = 96,
  73                 .vsync_len      = 1,
  74                 .sync           = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
  75                 .vmode          = FB_VMODE_NONINTERLACED,
  76                 .flag           = 0,
  77         },
  78 };
  79
  80 static const struct ipu_platform_data mx3_ipu_data __initconst = {
  81         .irq_base = MXC_IPU_IRQ_START,
  82 };
  83
  84 static struct mx3fb_platform_data mx3fb_pdata __initdata = {
  85         .name           = "Sharp-LQ035Q7",
  86         .mode           = fb_modedb,
  87         .num_modes      = ARRAY_SIZE(fb_modedb),
  88 };
  89
  90 static struct physmap_flash_data pcm043_flash_data = {
  91         .width  = 2,
  92 };
  93
  94 static struct resource pcm043_flash_resource = {
  95         .start  = 0xa0000000,
  96         .end    = 0xa1ffffff,
  97         .flags  = IORESOURCE_MEM,
  98 };
  99
 100 static struct platform_device pcm043_flash = {
 101         .name   = "physmap-flash",
 102         .id     = 0,
 103         .dev    = {
 104                 .platform_data  = &pcm043_flash_data,
 105         },
 106         .resource = &pcm043_flash_resource,
 107         .num_resources = 1,
 108 };
 109
 110 static const struct imxuart_platform_data uart_pdata __initconst = {
 111         .flags = IMXUART_HAVE_RTSCTS,
 112 };
 113
 114 static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
 115         .bitrate = 50000,
 116 };
 117
 118 static struct at24_platform_data board_eeprom = {
 119         .byte_len = 4096,
 120         .page_size = 32,
 121         .flags = AT24_FLAG_ADDR16,
 122 };
 123
 124 static struct i2c_board_info pcm043_i2c_devices[] = {
 125         {
 126                 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
 127                 .platform_data = &board_eeprom,
 128         }, {
 129                 I2C_BOARD_INFO("pcf8563", 0x51),
 130         },
 131 };
 132
 133 static struct platform_device *devices[] __initdata = {
 134         &pcm043_flash,
 135 };
 136
 137 static iomux_v3_cfg_t pcm043_pads[] = {
 138         /* UART1 */
 139         MX35_PAD_CTS1__UART1_CTS,
 140         MX35_PAD_RTS1__UART1_RTS,
 141         MX35_PAD_TXD1__UART1_TXD_MUX,
 142         MX35_PAD_RXD1__UART1_RXD_MUX,
 143         /* UART2 */
 144         MX35_PAD_CTS2__UART2_CTS,
 145         MX35_PAD_RTS2__UART2_RTS,
 146         MX35_PAD_TXD2__UART2_TXD_MUX,
 147         MX35_PAD_RXD2__UART2_RXD_MUX,
 148         /* FEC */
 149         MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
 150         MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
 151         MX35_PAD_FEC_RX_DV__FEC_RX_DV,
 152         MX35_PAD_FEC_COL__FEC_COL,
 153         MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
 154         MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
 155         MX35_PAD_FEC_TX_EN__FEC_TX_EN,
 156         MX35_PAD_FEC_MDC__FEC_MDC,
 157         MX35_PAD_FEC_MDIO__FEC_MDIO,
 158         MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
 159         MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
 160         MX35_PAD_FEC_CRS__FEC_CRS,
 161         MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
 162         MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
 163         MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
 164         MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
 165         MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
 166         MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
 167         /* I2C1 */
 168         MX35_PAD_I2C1_CLK__I2C1_SCL,
 169         MX35_PAD_I2C1_DAT__I2C1_SDA,
 170         /* Display */
 171         MX35_PAD_LD0__IPU_DISPB_DAT_0,
 172         MX35_PAD_LD1__IPU_DISPB_DAT_1,
 173         MX35_PAD_LD2__IPU_DISPB_DAT_2,
 174         MX35_PAD_LD3__IPU_DISPB_DAT_3,
 175         MX35_PAD_LD4__IPU_DISPB_DAT_4,
 176         MX35_PAD_LD5__IPU_DISPB_DAT_5,
 177         MX35_PAD_LD6__IPU_DISPB_DAT_6,
 178         MX35_PAD_LD7__IPU_DISPB_DAT_7,
 179         MX35_PAD_LD8__IPU_DISPB_DAT_8,
 180         MX35_PAD_LD9__IPU_DISPB_DAT_9,
 181         MX35_PAD_LD10__IPU_DISPB_DAT_10,
 182         MX35_PAD_LD11__IPU_DISPB_DAT_11,
 183         MX35_PAD_LD12__IPU_DISPB_DAT_12,
 184         MX35_PAD_LD13__IPU_DISPB_DAT_13,
 185         MX35_PAD_LD14__IPU_DISPB_DAT_14,
 186         MX35_PAD_LD15__IPU_DISPB_DAT_15,
 187         MX35_PAD_LD16__IPU_DISPB_DAT_16,
 188         MX35_PAD_LD17__IPU_DISPB_DAT_17,
 189         MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
 190         MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
 191         MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
 192         MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
 193         MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
 194         MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
 195         MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
 196         /* gpio */
 197         MX35_PAD_ATA_CS0__GPIO2_6,
 198         /* USB host */
 199         MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
 200         MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
 201         /* SSI */
 202         MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
 203         MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
 204         MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
 205         MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
 206         /* CAN2 */
 207         MX35_PAD_TX5_RX0__CAN2_TXCAN,
 208         MX35_PAD_TX4_RX1__CAN2_RXCAN,
 209         /* esdhc */
 210         MX35_PAD_SD1_CMD__ESDHC1_CMD,
 211         MX35_PAD_SD1_CLK__ESDHC1_CLK,
 212         MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
 213         MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
 214         MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
 215         MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
 216         MX35_PAD_ATA_DATA10__GPIO2_23, /* WriteProtect */
 217         MX35_PAD_ATA_DATA11__GPIO2_24, /* CardDetect */
 218 };
 219
 220 #define AC97_GPIO_TXFS  IMX_GPIO_NR(2, 31)
 221 #define AC97_GPIO_TXD   IMX_GPIO_NR(2, 28)
 222 #define AC97_GPIO_RESET IMX_GPIO_NR(2, 0)
 223 #define SD1_GPIO_WP     IMX_GPIO_NR(2, 23)
 224 #define SD1_GPIO_CD     IMX_GPIO_NR(2, 24)
 225
 226 static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
 227 {
 228         iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
 229         iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
 230         int ret;
 231
 232         ret = gpio_request(AC97_GPIO_TXFS, "SSI");
 233         if (ret) {
 234                 printk("failed to get GPIO_TXFS: %d\n", ret);
 235                 return;
 236         }
 237
 238         mxc_iomux_v3_setup_pad(txfs_gpio);
 239
 240         /* warm reset */
 241         gpio_direction_output(AC97_GPIO_TXFS, 1);
 242         udelay(2);
 243         gpio_set_value(AC97_GPIO_TXFS, 0);
 244
 245         gpio_free(AC97_GPIO_TXFS);
 246         mxc_iomux_v3_setup_pad(txfs);
 247 }
 248
 249 static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
 250 {
 251         iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
 252         iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
 253         iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28;
 254         iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
 255         iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
 256         int ret;
 257
 258         ret = gpio_request(AC97_GPIO_TXFS, "SSI");
 259         if (ret)
 260                 goto err1;
 261
 262         ret = gpio_request(AC97_GPIO_TXD, "SSI");
 263         if (ret)
 264                 goto err2;
 265
 266         ret = gpio_request(AC97_GPIO_RESET, "SSI");
 267         if (ret)
 268                 goto err3;
 269
 270         mxc_iomux_v3_setup_pad(txfs_gpio);
 271         mxc_iomux_v3_setup_pad(txd_gpio);
 272         mxc_iomux_v3_setup_pad(reset_gpio);
 273
 274         gpio_direction_output(AC97_GPIO_TXFS, 0);
 275         gpio_direction_output(AC97_GPIO_TXD, 0);
 276
 277         /* cold reset */
 278         gpio_direction_output(AC97_GPIO_RESET, 0);
 279         udelay(10);
 280         gpio_direction_output(AC97_GPIO_RESET, 1);
 281
 282         mxc_iomux_v3_setup_pad(txd);
 283         mxc_iomux_v3_setup_pad(txfs);
 284
 285         gpio_free(AC97_GPIO_RESET);
 286 err3:
 287         gpio_free(AC97_GPIO_TXD);
 288 err2:
 289         gpio_free(AC97_GPIO_TXFS);
 290 err1:
 291         if (ret)
 292                 printk("%s failed with %d\n", __func__, ret);
 293         mdelay(1);
 294 }
 295
 296 static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = {
 297         .ac97_reset = pcm043_ac97_cold_reset,
 298         .ac97_warm_reset = pcm043_ac97_warm_reset,
 299         .flags = IMX_SSI_USE_AC97,
 300 };
 301
 302 static const struct mxc_nand_platform_data
 303 pcm037_nand_board_info __initconst = {
 304         .width = 1,
 305         .hw_ecc = 1,
 306 };
 307
 308 static int pcm043_otg_init(struct platform_device *pdev)
 309 {
 310         return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
 311 }
 312
 313 static struct mxc_usbh_platform_data otg_pdata __initdata = {
 314         .init   = pcm043_otg_init,
 315         .portsc = MXC_EHCI_MODE_UTMI,
 316 };
 317
 318 static int pcm043_usbh1_init(struct platform_device *pdev)
 319 {
 320         return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
 321                         MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
 322 }
 323
 324 static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
 325         .init   = pcm043_usbh1_init,
 326         .portsc = MXC_EHCI_MODE_SERIAL,
 327 };
 328
 329 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
 330         .operating_mode = FSL_USB2_DR_DEVICE,
 331         .phy_mode       = FSL_USB2_PHY_UTMI,
 332 };
 333
 334 static int otg_mode_host;
 335
 336 static int __init pcm043_otg_mode(char *options)
 337 {
 338         if (!strcmp(options, "host"))
 339                 otg_mode_host = 1;
 340         else if (!strcmp(options, "device"))
 341                 otg_mode_host = 0;
 342         else
 343                 pr_info("otg_mode neither \"host\" nor \"device\". "
 344                         "Defaulting to device\n");
 345         return 0;
 346 }
 347 __setup("otg_mode=", pcm043_otg_mode);
 348
 349 static struct esdhc_platform_data sd1_pdata = {
 350         .wp_gpio = SD1_GPIO_WP,
 351         .cd_gpio = SD1_GPIO_CD,
 352         .wp_type = ESDHC_WP_GPIO,
 353         .cd_type = ESDHC_CD_GPIO,
 354 };
 355
 356 /*
 357  * Board specific initialization.
 358  */
 359 static void __init pcm043_init(void)
 360 {
 361         imx35_soc_init();
 362
 363         mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
 364
 365         mxc_audmux_v2_configure_port(3,
 366                         MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
 367                         MXC_AUDMUX_V2_PTCR_TFSEL(0) |
 368                         MXC_AUDMUX_V2_PTCR_TFSDIR,
 369                         MXC_AUDMUX_V2_PDCR_RXDSEL(0));
 370
 371         mxc_audmux_v2_configure_port(0,
 372                         MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
 373                         MXC_AUDMUX_V2_PTCR_TCSEL(3) |
 374                         MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
 375                         MXC_AUDMUX_V2_PDCR_RXDSEL(3));
 376
 377         imx35_add_fec(NULL);
 378         platform_add_devices(devices, ARRAY_SIZE(devices));
 379         imx35_add_imx2_wdt(NULL);
 380
 381         imx35_add_imx_uart0(&uart_pdata);
 382         imx35_add_mxc_nand(&pcm037_nand_board_info);
 383         imx35_add_imx_ssi(0, &pcm043_ssi_pdata);
 384
 385         imx35_add_imx_uart1(&uart_pdata);
 386
 387         i2c_register_board_info(0, pcm043_i2c_devices,
 388                         ARRAY_SIZE(pcm043_i2c_devices));
 389
 390         imx35_add_imx_i2c0(&pcm043_i2c0_data);
 391
 392         imx35_add_ipu_core(&mx3_ipu_data);
 393         imx35_add_mx3_sdc_fb(&mx3fb_pdata);
 394
 395         if (otg_mode_host) {
 396                 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
 397                                 ULPI_OTG_DRVVBUS_EXT);
 398                 if (otg_pdata.otg)
 399                         imx35_add_mxc_ehci_otg(&otg_pdata);
 400         }
 401         imx35_add_mxc_ehci_hs(&usbh1_pdata);
 402
 403         if (!otg_mode_host)
 404                 imx35_add_fsl_usb2_udc(&otg_device_pdata);
 405
 406         imx35_add_flexcan1(NULL);
 407         imx35_add_sdhci_esdhc_imx(0, &sd1_pdata);
 408 }
 409
 410 static void __init pcm043_timer_init(void)
 411 {
 412         mx35_clocks_init();
 413 }
 414
 415 struct sys_timer pcm043_timer = {
 416         .init   = pcm043_timer_init,
 417 };
 418
 419 MACHINE_START(PCM043, "Phytec Phycore pcm043")
 420         /* Maintainer: Pengutronix */
 421         .boot_params = MX3x_PHYS_OFFSET + 0x100,
 422         .map_io = mx35_map_io,
 423         .init_early = imx35_init_early,
 424         .init_irq = mx35_init_irq,
 425         .timer = &pcm043_timer,
 426         .init_machine = pcm043_init,
 427 MACHINE_END