arch/arm/mach-integrator/integrator_ap.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_ap.c
   3  *
   4  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <linux/types.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/slab.h>
  26 #include <linux/string.h>
  27 #include <linux/syscore_ops.h>
  28 #include <linux/amba/bus.h>
  29 #include <linux/amba/kmi.h>
  30 #include <linux/clocksource.h>
  31 #include <linux/clockchips.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/io.h>
  34 #include <linux/mtd/physmap.h>
  35
  36 #include <mach/hardware.h>
  37 #include <mach/platform.h>
  38 #include <asm/hardware/arm_timer.h>
  39 #include <asm/irq.h>
  40 #include <asm/setup.h>
  41 #include <asm/param.h>          /* HZ */
  42 #include <asm/mach-types.h>
  43
  44 #include <mach/lm.h>
  45
  46 #include <asm/mach/arch.h>
  47 #include <asm/mach/irq.h>
  48 #include <asm/mach/map.h>
  49 #include <asm/mach/time.h>
  50
  51 #include <plat/fpga-irq.h>
  52
  53 #include "common.h"
  54
  55 /*
  56  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  57  * is the (PA >> 12).
  58  *
  59  * Setup a VA for the Integrator interrupt controller (for header #0,
  60  * just for now).
  61  */
  62 #define VA_IC_BASE      __io_address(INTEGRATOR_IC_BASE)
  63 #define VA_SC_BASE      __io_address(INTEGRATOR_SC_BASE)
  64 #define VA_EBI_BASE     __io_address(INTEGRATOR_EBI_BASE)
  65 #define VA_CMIC_BASE    __io_address(INTEGRATOR_HDR_IC)
  66
  67 /*
  68  * Logical      Physical
  69  * e8000000     40000000        PCI memory              PHYS_PCI_MEM_BASE       (max 512M)
  70  * ec000000     61000000        PCI config space        PHYS_PCI_CONFIG_BASE    (max 16M)
  71  * ed000000     62000000        PCI V3 regs             PHYS_PCI_V3_BASE        (max 64k)
  72  * ee000000     60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
  73  * ef000000                     Cache flush
  74  * f1000000     10000000        Core module registers
  75  * f1100000     11000000        System controller registers
  76  * f1200000     12000000        EBI registers
  77  * f1300000     13000000        Counter/Timer
  78  * f1400000     14000000        Interrupt controller
  79  * f1600000     16000000        UART 0
  80  * f1700000     17000000        UART 1
  81  * f1a00000     1a000000        Debug LEDs
  82  * f1b00000     1b000000        GPIO
  83  */
  84
  85 static struct map_desc ap_io_desc[] __initdata = {
  86         {
  87                 .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
  88                 .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
  89                 .length         = SZ_4K,
  90                 .type           = MT_DEVICE
  91         }, {
  92                 .virtual        = IO_ADDRESS(INTEGRATOR_SC_BASE),
  93                 .pfn            = __phys_to_pfn(INTEGRATOR_SC_BASE),
  94                 .length         = SZ_4K,
  95                 .type           = MT_DEVICE
  96         }, {
  97                 .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
  98                 .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
  99                 .length         = SZ_4K,
 100                 .type           = MT_DEVICE
 101         }, {
 102                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
 103                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
 104                 .length         = SZ_4K,
 105                 .type           = MT_DEVICE
 106         }, {
 107                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
 108                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
 109                 .length         = SZ_4K,
 110                 .type           = MT_DEVICE
 111         }, {
 112                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
 113                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
 114                 .length         = SZ_4K,
 115                 .type           = MT_DEVICE
 116         }, {
 117                 .virtual        = IO_ADDRESS(INTEGRATOR_UART1_BASE),
 118                 .pfn            = __phys_to_pfn(INTEGRATOR_UART1_BASE),
 119                 .length         = SZ_4K,
 120                 .type           = MT_DEVICE
 121         }, {
 122                 .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
 123                 .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
 124                 .length         = SZ_4K,
 125                 .type           = MT_DEVICE
 126         }, {
 127                 .virtual        = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
 128                 .pfn            = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
 129                 .length         = SZ_4K,
 130                 .type           = MT_DEVICE
 131         }, {
 132                 .virtual        = PCI_MEMORY_VADDR,
 133                 .pfn            = __phys_to_pfn(PHYS_PCI_MEM_BASE),
 134                 .length         = SZ_16M,
 135                 .type           = MT_DEVICE
 136         }, {
 137                 .virtual        = PCI_CONFIG_VADDR,
 138                 .pfn            = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
 139                 .length         = SZ_16M,
 140                 .type           = MT_DEVICE
 141         }, {
 142                 .virtual        = PCI_V3_VADDR,
 143                 .pfn            = __phys_to_pfn(PHYS_PCI_V3_BASE),
 144                 .length         = SZ_64K,
 145                 .type           = MT_DEVICE
 146         }, {
 147                 .virtual        = PCI_IO_VADDR,
 148                 .pfn            = __phys_to_pfn(PHYS_PCI_IO_BASE),
 149                 .length         = SZ_64K,
 150                 .type           = MT_DEVICE
 151         }
 152 };
 153
 154 static void __init ap_map_io(void)
 155 {
 156         iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
 157 }
 158
 159 #define INTEGRATOR_SC_VALID_INT 0x003fffff
 160
 161 static struct fpga_irq_data sc_irq_data = {
 162         .base           = VA_IC_BASE,
 163         .irq_start      = 0,
 164         .chip.name      = "SC",
 165 };
 166
 167 static void __init ap_init_irq(void)
 168 {
 169         /* Disable all interrupts initially. */
 170         /* Do the core module ones */
 171         writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 172
 173         /* do the header card stuff next */
 174         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 175         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 176
 177         fpga_irq_init(-1, INTEGRATOR_SC_VALID_INT, &sc_irq_data);
 178 }
 179
 180 #ifdef CONFIG_PM
 181 static unsigned long ic_irq_enable;
 182
 183 static int irq_suspend(void)
 184 {
 185         ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
 186         return 0;
 187 }
 188
 189 static void irq_resume(void)
 190 {
 191         /* disable all irq sources */
 192         writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 193         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 194         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 195
 196         writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
 197 }
 198 #else
 199 #define irq_suspend NULL
 200 #define irq_resume NULL
 201 #endif
 202
 203 static struct syscore_ops irq_syscore_ops = {
 204         .suspend        = irq_suspend,
 205         .resume         = irq_resume,
 206 };
 207
 208 static int __init irq_syscore_init(void)
 209 {
 210         register_syscore_ops(&irq_syscore_ops);
 211
 212         return 0;
 213 }
 214
 215 device_initcall(irq_syscore_init);
 216
 217 /*
 218  * Flash handling.
 219  */
 220 #define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
 221 #define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
 222 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
 223 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
 224
 225 static int ap_flash_init(struct platform_device *dev)
 226 {
 227         u32 tmp;
 228
 229         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
 230
 231         tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
 232         writel(tmp, EBI_CSR1);
 233
 234         if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
 235                 writel(0xa05f, EBI_LOCK);
 236                 writel(tmp, EBI_CSR1);
 237                 writel(0, EBI_LOCK);
 238         }
 239         return 0;
 240 }
 241
 242 static void ap_flash_exit(struct platform_device *dev)
 243 {
 244         u32 tmp;
 245
 246         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
 247
 248         tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
 249         writel(tmp, EBI_CSR1);
 250
 251         if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
 252                 writel(0xa05f, EBI_LOCK);
 253                 writel(tmp, EBI_CSR1);
 254                 writel(0, EBI_LOCK);
 255         }
 256 }
 257
 258 static void ap_flash_set_vpp(struct platform_device *pdev, int on)
 259 {
 260         void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
 261
 262         writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
 263 }
 264
 265 static struct physmap_flash_data ap_flash_data = {
 266         .width          = 4,
 267         .init           = ap_flash_init,
 268         .exit           = ap_flash_exit,
 269         .set_vpp        = ap_flash_set_vpp,
 270 };
 271
 272 static struct resource cfi_flash_resource = {
 273         .start          = INTEGRATOR_FLASH_BASE,
 274         .end            = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
 275         .flags          = IORESOURCE_MEM,
 276 };
 277
 278 static struct platform_device cfi_flash_device = {
 279         .name           = "physmap-flash",
 280         .id             = 0,
 281         .dev            = {
 282                 .platform_data  = &ap_flash_data,
 283         },
 284         .num_resources  = 1,
 285         .resource       = &cfi_flash_resource,
 286 };
 287
 288 static void __init ap_init(void)
 289 {
 290         unsigned long sc_dec;
 291         int i;
 292
 293         platform_device_register(&cfi_flash_device);
 294
 295         sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
 296         for (i = 0; i < 4; i++) {
 297                 struct lm_device *lmdev;
 298
 299                 if ((sc_dec & (16 << i)) == 0)
 300                         continue;
 301
 302                 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
 303                 if (!lmdev)
 304                         continue;
 305
 306                 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
 307                 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
 308                 lmdev->resource.flags = IORESOURCE_MEM;
 309                 lmdev->irq = IRQ_AP_EXPINT0 + i;
 310                 lmdev->id = i;
 311
 312                 lm_device_register(lmdev);
 313         }
 314 }
 315
 316 /*
 317  * Where is the timer (VA)?
 318  */
 319 #define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
 320 #define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
 321 #define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
 322
 323 /*
 324  * How long is the timer interval?
 325  */
 326 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 327 #if TIMER_INTERVAL >= 0x100000
 328 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 329 #elif TIMER_INTERVAL >= 0x10000
 330 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 331 #else
 332 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 333 #endif
 334
 335 static unsigned long timer_reload;
 336
 337 static void integrator_clocksource_init(u32 khz)
 338 {
 339         void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
 340         u32 ctrl = TIMER_CTRL_ENABLE;
 341
 342         if (khz >= 1500) {
 343                 khz /= 16;
 344                 ctrl = TIMER_CTRL_DIV16;
 345         }
 346
 347         writel(ctrl, base + TIMER_CTRL);
 348         writel(0xffff, base + TIMER_LOAD);
 349
 350         clocksource_mmio_init(base + TIMER_VALUE, "timer2",
 351                 khz * 1000, 200, 16, clocksource_mmio_readl_down);
 352 }
 353
 354 static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
 355
 356 /*
 357  * IRQ handler for the timer
 358  */
 359 static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
 360 {
 361         struct clock_event_device *evt = dev_id;
 362
 363         /* clear the interrupt */
 364         writel(1, clkevt_base + TIMER_INTCLR);
 365
 366         evt->event_handler(evt);
 367
 368         return IRQ_HANDLED;
 369 }
 370
 371 static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
 372 {
 373         u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
 374
 375         BUG_ON(mode == CLOCK_EVT_MODE_ONESHOT);
 376
 377         if (mode == CLOCK_EVT_MODE_PERIODIC) {
 378                 writel(ctrl, clkevt_base + TIMER_CTRL);
 379                 writel(timer_reload, clkevt_base + TIMER_LOAD);
 380                 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
 381         }
 382
 383         writel(ctrl, clkevt_base + TIMER_CTRL);
 384 }
 385
 386 static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
 387 {
 388         unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
 389
 390         writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 391         writel(next, clkevt_base + TIMER_LOAD);
 392         writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 393
 394         return 0;
 395 }
 396
 397 static struct clock_event_device integrator_clockevent = {
 398         .name           = "timer1",
 399         .shift          = 34,
 400         .features       = CLOCK_EVT_FEAT_PERIODIC,
 401         .set_mode       = clkevt_set_mode,
 402         .set_next_event = clkevt_set_next_event,
 403         .rating         = 300,
 404         .cpumask        = cpu_all_mask,
 405 };
 406
 407 static struct irqaction integrator_timer_irq = {
 408         .name           = "timer",
 409         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 410         .handler        = integrator_timer_interrupt,
 411         .dev_id         = &integrator_clockevent,
 412 };
 413
 414 static void integrator_clockevent_init(u32 khz)
 415 {
 416         struct clock_event_device *evt = &integrator_clockevent;
 417         unsigned int ctrl = 0;
 418
 419         if (khz * 1000 > 0x100000 * HZ) {
 420                 khz /= 256;
 421                 ctrl |= TIMER_CTRL_DIV256;
 422         } else if (khz * 1000 > 0x10000 * HZ) {
 423                 khz /= 16;
 424                 ctrl |= TIMER_CTRL_DIV16;
 425         }
 426
 427         timer_reload = khz * 1000 / HZ;
 428         writel(ctrl, clkevt_base + TIMER_CTRL);
 429
 430         evt->irq = IRQ_TIMERINT1;
 431         evt->mult = div_sc(khz, NSEC_PER_MSEC, evt->shift);
 432         evt->max_delta_ns = clockevent_delta2ns(0xffff, evt);
 433         evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
 434
 435         setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
 436         clockevents_register_device(evt);
 437 }
 438
 439 /*
 440  * Set up timer(s).
 441  */
 442 static void __init ap_init_timer(void)
 443 {
 444         u32 khz = TICKS_PER_uSEC * 1000;
 445
 446         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 447         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 448         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 449
 450         integrator_clocksource_init(khz);
 451         integrator_clockevent_init(khz);
 452 }
 453
 454 static struct sys_timer ap_timer = {
 455         .init           = ap_init_timer,
 456 };
 457
 458 MACHINE_START(INTEGRATOR, "ARM-Integrator")
 459         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 460         .boot_params    = 0x00000100,
 461         .reserve        = integrator_reserve,
 462         .map_io         = ap_map_io,
 463         .init_early     = integrator_init_early,
 464         .init_irq       = ap_init_irq,
 465         .timer          = &ap_timer,
 466         .init_machine   = ap_init,
 467 MACHINE_END