Merge remote-tracking branch 's5p/for-next'
[linux-2.6/next.git] / arch / arm / mach-mx5 / cpu.c
blob86f87da59c641e9012b7faccaadd80bbe0b8a44e
1 /*
2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
11 * This file contains the CPU initialization code.
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <mach/hardware.h>
19 #include <asm/io.h>
21 static int cpu_silicon_rev = -1;
23 #define IIM_SREV 0x24
24 #define MX50_HW_ADADIG_DIGPROG 0xB0
26 static int get_mx51_srev(void)
28 void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
29 u32 rev = readl(iim_base + IIM_SREV) & 0xff;
31 if (rev == 0x0)
32 return IMX_CHIP_REVISION_2_0;
33 else if (rev == 0x10)
34 return IMX_CHIP_REVISION_3_0;
35 return 0;
39 * Returns:
40 * the silicon revision of the cpu
41 * -EINVAL - not a mx51
43 int mx51_revision(void)
45 if (!cpu_is_mx51())
46 return -EINVAL;
48 if (cpu_silicon_rev == -1)
49 cpu_silicon_rev = get_mx51_srev();
51 return cpu_silicon_rev;
53 EXPORT_SYMBOL(mx51_revision);
55 void mx51_display_revision(void)
57 int rev;
58 char *srev;
59 rev = mx51_revision();
61 switch (rev) {
62 case IMX_CHIP_REVISION_2_0:
63 srev = IMX_CHIP_REVISION_2_0_STRING;
64 break;
65 case IMX_CHIP_REVISION_3_0:
66 srev = IMX_CHIP_REVISION_3_0_STRING;
67 break;
68 default:
69 srev = IMX_CHIP_REVISION_UNKNOWN_STRING;
71 printk(KERN_INFO "CPU identified as i.MX51, silicon rev %s\n", srev);
73 EXPORT_SYMBOL(mx51_display_revision);
75 #ifdef CONFIG_NEON
78 * All versions of the silicon before Rev. 3 have broken NEON implementations.
79 * Dependent on link order - so the assumption is that vfp_init is called
80 * before us.
82 static int __init mx51_neon_fixup(void)
84 if (!cpu_is_mx51())
85 return 0;
87 if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) {
88 elf_hwcap &= ~HWCAP_NEON;
89 pr_info("Turning off NEON support, detected broken NEON implementation\n");
91 return 0;
94 late_initcall(mx51_neon_fixup);
95 #endif
97 static int get_mx53_srev(void)
99 void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
100 u32 rev = readl(iim_base + IIM_SREV) & 0xff;
102 switch (rev) {
103 case 0x0:
104 return IMX_CHIP_REVISION_1_0;
105 case 0x2:
106 return IMX_CHIP_REVISION_2_0;
107 case 0x3:
108 return IMX_CHIP_REVISION_2_1;
109 default:
110 return IMX_CHIP_REVISION_UNKNOWN;
115 * Returns:
116 * the silicon revision of the cpu
117 * -EINVAL - not a mx53
119 int mx53_revision(void)
121 if (!cpu_is_mx53())
122 return -EINVAL;
124 if (cpu_silicon_rev == -1)
125 cpu_silicon_rev = get_mx53_srev();
127 return cpu_silicon_rev;
129 EXPORT_SYMBOL(mx53_revision);
131 static int get_mx50_srev(void)
133 void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K);
134 u32 rev;
136 if (!anatop) {
137 cpu_silicon_rev = -EINVAL;
138 return 0;
141 rev = readl(anatop + MX50_HW_ADADIG_DIGPROG);
142 rev &= 0xff;
144 iounmap(anatop);
145 if (rev == 0x0)
146 return IMX_CHIP_REVISION_1_0;
147 else if (rev == 0x1)
148 return IMX_CHIP_REVISION_1_1;
149 return 0;
153 * Returns:
154 * the silicon revision of the cpu
155 * -EINVAL - not a mx50
157 int mx50_revision(void)
159 if (!cpu_is_mx50())
160 return -EINVAL;
162 if (cpu_silicon_rev == -1)
163 cpu_silicon_rev = get_mx50_srev();
165 return cpu_silicon_rev;
167 EXPORT_SYMBOL(mx50_revision);
169 void mx53_display_revision(void)
171 int rev;
172 char *srev;
173 rev = mx53_revision();
175 switch (rev) {
176 case IMX_CHIP_REVISION_1_0:
177 srev = IMX_CHIP_REVISION_1_0_STRING;
178 break;
179 case IMX_CHIP_REVISION_2_0:
180 srev = IMX_CHIP_REVISION_2_0_STRING;
181 break;
182 case IMX_CHIP_REVISION_2_1:
183 srev = IMX_CHIP_REVISION_2_1_STRING;
184 break;
185 default:
186 srev = IMX_CHIP_REVISION_UNKNOWN_STRING;
188 printk(KERN_INFO "CPU identified as i.MX53, silicon rev %s\n", srev);
190 EXPORT_SYMBOL(mx53_display_revision);
192 static int __init post_cpu_init(void)
194 unsigned int reg;
195 void __iomem *base;
197 if (cpu_is_mx51() || cpu_is_mx53()) {
198 if (cpu_is_mx51())
199 base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
200 else
201 base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
203 __raw_writel(0x0, base + 0x40);
204 __raw_writel(0x0, base + 0x44);
205 __raw_writel(0x0, base + 0x48);
206 __raw_writel(0x0, base + 0x4C);
207 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
208 __raw_writel(reg, base + 0x50);
210 if (cpu_is_mx51())
211 base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
212 else
213 base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
215 __raw_writel(0x0, base + 0x40);
216 __raw_writel(0x0, base + 0x44);
217 __raw_writel(0x0, base + 0x48);
218 __raw_writel(0x0, base + 0x4C);
219 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
220 __raw_writel(reg, base + 0x50);
223 return 0;
226 postcore_initcall(post_cpu_init);