arch/arm/mach-shmobile/intc-sh73a0.c

   1 /*
   2  * sh73a0 processor support - INTC hardware block
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  18  */
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/irq.h>
  23 #include <linux/io.h>
  24 #include <linux/sh_intc.h>
  25 #include <asm/hardware/gic.h>
  26 #include <asm/mach-types.h>
  27 #include <asm/mach/arch.h>
  28
  29 enum {
  30         UNUSED = 0,
  31
  32         /* interrupt sources INTCS */
  33         PINTCS_PINT1, PINTCS_PINT2,
  34         RTDMAC_0_DEI0, RTDMAC_0_DEI1, RTDMAC_0_DEI2, RTDMAC_0_DEI3,
  35         CEU, MFI, BBIF2, VPU, TSIF1, _3DG_SGX543, _2DDMAC_2DDM0,
  36         RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR,
  37         KEYSC_KEY, VINT, MSIOF,
  38         TMU0_TUNI00, TMU0_TUNI01, TMU0_TUNI02,
  39         CMT0, TSIF0, CMT2, LMB, MSUG, MSU_MSU, MSU_MSU2,
  40         CTI, RWDT0, ICB, PEP, ASA, JPU_JPEG, LCDC, LCRC,
  41         RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9,
  42         RTDMAC_3_DEI10, RTDMAC_3_DEI11,
  43         FRC, GCU, LCDC1, CSIRX,
  44         DSITX0_DSITX00, DSITX0_DSITX01,
  45         SPU2_SPU0, SPU2_SPU1, FSI,
  46         TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12,
  47         TSIF2, CMT4, MFIS2, CPORTS2R, TSG, DMASCH1, SCUW,
  48         VIO60, VIO61, CEU21, CSI21, DSITX1_DSITX10, DSITX1_DSITX11,
  49         DISP, DSRV, EMUX2_EMUX20I, EMUX2_EMUX21I,
  50         MSTIF0_MST00I, MSTIF0_MST01I, MSTIF1_MST10I, MSTIF1_MST11I,
  51         SPUV,
  52
  53         /* interrupt groups INTCS */
  54         RTDMAC_0, RTDMAC_1, RTDMAC_2, RTDMAC_3,
  55         DSITX0, SPU2, TMU1, MSU,
  56 };
  57
  58 static struct intc_vect intcs_vectors[] = {
  59         INTCS_VECT(PINTCS_PINT1, 0x0600), INTCS_VECT(PINTCS_PINT2, 0x0620),
  60         INTCS_VECT(RTDMAC_0_DEI0, 0x0800), INTCS_VECT(RTDMAC_0_DEI1, 0x0820),
  61         INTCS_VECT(RTDMAC_0_DEI2, 0x0840), INTCS_VECT(RTDMAC_0_DEI3, 0x0860),
  62         INTCS_VECT(CEU, 0x0880), INTCS_VECT(MFI, 0x0900),
  63         INTCS_VECT(BBIF2, 0x0960), INTCS_VECT(VPU, 0x0980),
  64         INTCS_VECT(TSIF1, 0x09a0), INTCS_VECT(_3DG_SGX543, 0x09e0),
  65         INTCS_VECT(_2DDMAC_2DDM0, 0x0a00),
  66         INTCS_VECT(RTDMAC_1_DEI4, 0x0b80), INTCS_VECT(RTDMAC_1_DEI5, 0x0ba0),
  67         INTCS_VECT(RTDMAC_1_DADERR, 0x0bc0),
  68         INTCS_VECT(KEYSC_KEY, 0x0be0), INTCS_VECT(VINT, 0x0c80),
  69         INTCS_VECT(MSIOF, 0x0d20),
  70         INTCS_VECT(TMU0_TUNI00, 0x0e80), INTCS_VECT(TMU0_TUNI01, 0x0ea0),
  71         INTCS_VECT(TMU0_TUNI02, 0x0ec0),
  72         INTCS_VECT(CMT0, 0x0f00), INTCS_VECT(TSIF0, 0x0f20),
  73         INTCS_VECT(CMT2, 0x0f40), INTCS_VECT(LMB, 0x0f60),
  74         INTCS_VECT(MSUG, 0x0f80),
  75         INTCS_VECT(MSU_MSU, 0x0fa0), INTCS_VECT(MSU_MSU2, 0x0fc0),
  76         INTCS_VECT(CTI, 0x0400), INTCS_VECT(RWDT0, 0x0440),
  77         INTCS_VECT(ICB, 0x0480), INTCS_VECT(PEP, 0x04a0),
  78         INTCS_VECT(ASA, 0x04c0), INTCS_VECT(JPU_JPEG, 0x0560),
  79         INTCS_VECT(LCDC, 0x0580), INTCS_VECT(LCRC, 0x05a0),
  80         INTCS_VECT(RTDMAC_2_DEI6, 0x1300), INTCS_VECT(RTDMAC_2_DEI7, 0x1320),
  81         INTCS_VECT(RTDMAC_2_DEI8, 0x1340), INTCS_VECT(RTDMAC_2_DEI9, 0x1360),
  82         INTCS_VECT(RTDMAC_3_DEI10, 0x1380), INTCS_VECT(RTDMAC_3_DEI11, 0x13a0),
  83         INTCS_VECT(FRC, 0x1700), INTCS_VECT(GCU, 0x1760),
  84         INTCS_VECT(LCDC1, 0x1780), INTCS_VECT(CSIRX, 0x17a0),
  85         INTCS_VECT(DSITX0_DSITX00, 0x17c0), INTCS_VECT(DSITX0_DSITX01, 0x17e0),
  86         INTCS_VECT(SPU2_SPU0, 0x1800), INTCS_VECT(SPU2_SPU1, 0x1820),
  87         INTCS_VECT(FSI, 0x1840),
  88         INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920),
  89         INTCS_VECT(TMU1_TUNI12, 0x1940),
  90         INTCS_VECT(TSIF2, 0x1960), INTCS_VECT(CMT4, 0x1980),
  91         INTCS_VECT(MFIS2, 0x1a00), INTCS_VECT(CPORTS2R, 0x1a20),
  92         INTCS_VECT(TSG, 0x1ae0), INTCS_VECT(DMASCH1, 0x1b00),
  93         INTCS_VECT(SCUW, 0x1b40),
  94         INTCS_VECT(VIO60, 0x1b60), INTCS_VECT(VIO61, 0x1b80),
  95         INTCS_VECT(CEU21, 0x1ba0), INTCS_VECT(CSI21, 0x1be0),
  96         INTCS_VECT(DSITX1_DSITX10, 0x1c00), INTCS_VECT(DSITX1_DSITX11, 0x1c20),
  97         INTCS_VECT(DISP, 0x1c40), INTCS_VECT(DSRV, 0x1c60),
  98         INTCS_VECT(EMUX2_EMUX20I, 0x1c80), INTCS_VECT(EMUX2_EMUX21I, 0x1ca0),
  99         INTCS_VECT(MSTIF0_MST00I, 0x1cc0), INTCS_VECT(MSTIF0_MST01I, 0x1ce0),
 100         INTCS_VECT(MSTIF1_MST10I, 0x1d00), INTCS_VECT(MSTIF1_MST11I, 0x1d20),
 101         INTCS_VECT(SPUV, 0x2300),
 102 };
 103
 104 static struct intc_group intcs_groups[] __initdata = {
 105         INTC_GROUP(RTDMAC_0, RTDMAC_0_DEI0, RTDMAC_0_DEI1,
 106                    RTDMAC_0_DEI2, RTDMAC_0_DEI3),
 107         INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR),
 108         INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI6, RTDMAC_2_DEI7,
 109                    RTDMAC_2_DEI8, RTDMAC_2_DEI9),
 110         INTC_GROUP(RTDMAC_3, RTDMAC_3_DEI10, RTDMAC_3_DEI11),
 111         INTC_GROUP(TMU1, TMU1_TUNI12, TMU1_TUNI11, TMU1_TUNI10),
 112         INTC_GROUP(DSITX0, DSITX0_DSITX00, DSITX0_DSITX01),
 113         INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
 114         INTC_GROUP(MSU, MSU_MSU, MSU_MSU2),
 115 };
 116
 117 static struct intc_mask_reg intcs_mask_registers[] = {
 118         { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
 119           { 0, 0, 0, CEU,
 120             0, 0, 0, 0 } },
 121         { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
 122           { 0, 0, 0, VPU,
 123             BBIF2, 0, 0, MFI } },
 124         { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
 125           { 0, 0, 0, _2DDMAC_2DDM0,
 126             0, ASA, PEP, ICB } },
 127         { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
 128           { 0, 0, 0, CTI,
 129             JPU_JPEG, 0, LCRC, LCDC } },
 130         { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
 131           { KEYSC_KEY, RTDMAC_1_DADERR, RTDMAC_1_DEI5, RTDMAC_1_DEI4,
 132             RTDMAC_0_DEI3, RTDMAC_0_DEI2, RTDMAC_0_DEI1, RTDMAC_0_DEI0 } },
 133         { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
 134           { 0, 0, MSIOF, 0,
 135             _3DG_SGX543, 0, 0, 0 } },
 136         { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
 137           { 0, TMU0_TUNI02, TMU0_TUNI01, TMU0_TUNI00,
 138             0, 0, 0, 0 } },
 139         { 0xffd201a0, 0xffd201e0, 8, /* IMR8SA / IMCR8SA */
 140           { 0, 0, 0, 0,
 141             0, MSU_MSU, MSU_MSU2, MSUG } },
 142         { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
 143           { 0, RWDT0, CMT2, CMT0,
 144             0, 0, 0, 0 } },
 145         { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
 146           { 0, 0, 0, 0,
 147             0, TSIF1, LMB, TSIF0 } },
 148         { 0xffd201b0, 0xffd201f0, 8, /* IMR12SA / IMCR12SA */
 149           { 0, 0, 0, 0,
 150             0, 0, PINTCS_PINT2, PINTCS_PINT1 } },
 151         { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */
 152           { RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9,
 153             RTDMAC_3_DEI10, RTDMAC_3_DEI11, 0, 0 } },
 154         { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */
 155           { FRC, 0, 0, GCU,
 156             LCDC1, CSIRX, DSITX0_DSITX00, DSITX0_DSITX01 } },
 157         { 0xffd50194, 0xffd501d4, 8, /* IMR5SA3 / IMCR5SA3 */
 158           { SPU2_SPU0, SPU2_SPU1, FSI, 0,
 159             0, 0, 0, 0 } },
 160         { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */
 161           { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, 0,
 162             TSIF2, CMT4, 0, 0 } },
 163         { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
 164           { MFIS2, CPORTS2R, 0, 0,
 165             0, 0, 0, TSG } },
 166         { 0xffd501a0, 0xffd501e0, 8, /* IMR8SA3 / IMCR8SA3 */
 167           { DMASCH1, 0, SCUW, VIO60,
 168             VIO61, CEU21, 0, CSI21 } },
 169         { 0xffd501a4, 0xffd501e4, 8, /* IMR9SA3 / IMCR9SA3 */
 170           { DSITX1_DSITX10, DSITX1_DSITX11, DISP, DSRV,
 171             EMUX2_EMUX20I, EMUX2_EMUX21I, MSTIF0_MST00I, MSTIF0_MST01I } },
 172         { 0xffd501a8, 0xffd501e8, 8, /* IMR10SA3 / IMCR10SA3 */
 173           { MSTIF0_MST00I, MSTIF0_MST01I, 0, 0,
 174             0, 0, 0, 0  } },
 175         { 0xffd60180, 0xffd601c0, 8, /* IMR0SA4 / IMCR0SA4 */
 176           { SPUV, 0, 0, 0,
 177             0, 0, 0, 0  } },
 178 };
 179
 180 /* Priority is needed for INTCA to receive the INTCS interrupt */
 181 static struct intc_prio_reg intcs_prio_registers[] = {
 182         { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC_2DDM0, ICB } },
 183         { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } },
 184         { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } },
 185         { 0xffd2000c, 0, 16, 4, /* IPRDS */ { PINTCS_PINT1, PINTCS_PINT2,
 186                                               0, 0 } },
 187         { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_0, CEU, MFI, VPU } },
 188         { 0xffd20014, 0, 16, 4, /* IPRFS */ { KEYSC_KEY, RTDMAC_1,
 189                                               CMT2, CMT0 } },
 190         { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_TUNI00, TMU0_TUNI01,
 191                                               TMU0_TUNI02, TSIF1 } },
 192         { 0xffd2001c, 0, 16, 4, /* IPRHS */ { VINT, 0, 0, 0 } },
 193         { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, 0 } },
 194         { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX543, MSUG, MSU } },
 195         { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, ASA, LMB, PEP } },
 196         { 0xffd20030, 0, 16, 4, /* IPRMS */ { 0, 0, 0, RWDT0 } },
 197         { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC_2, 0, 0, 0 } },
 198         { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC_3, 0, 0, 0 } },
 199         { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { FRC, 0, 0, 0 } },
 200         { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX0, 0 } },
 201         { 0xffd50028, 0, 16, 4, /* IPRKS3 */ { SPU2, 0, FSI, 0 } },
 202         { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, TSIF2 } },
 203         { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, 0, 0, 0 } },
 204         { 0xffd50038, 0, 16, 4, /* IPROS3 */ { MFIS2, CPORTS2R, 0, 0 } },
 205         { 0xffd50040, 0, 16, 4, /* IPRQS3 */ { DMASCH1, 0, SCUW, VIO60 } },
 206         { 0xffd50044, 0, 16, 4, /* IPRRS3 */ { VIO61, CEU21, 0, CSI21 } },
 207         { 0xffd50048, 0, 16, 4, /* IPRSS3 */ { DSITX1_DSITX10, DSITX1_DSITX11,
 208                                                DISP, DSRV } },
 209         { 0xffd5004c, 0, 16, 4, /* IPRTS3 */ { EMUX2_EMUX20I, EMUX2_EMUX21I,
 210                                                MSTIF0_MST00I, MSTIF0_MST01I } },
 211         { 0xffd50050, 0, 16, 4, /* IPRUS3 */ { MSTIF1_MST10I, MSTIF1_MST11I,
 212                                                0, 0 } },
 213         { 0xffd60000, 0, 16, 4, /* IPRAS4 */ { SPUV, 0, 0, 0 } },
 214 };
 215
 216 static struct resource intcs_resources[] __initdata = {
 217         [0] = {
 218                 .start  = 0xffd20000,
 219                 .end    = 0xffd201ff,
 220                 .flags  = IORESOURCE_MEM,
 221         },
 222         [1] = {
 223                 .start  = 0xffd50000,
 224                 .end    = 0xffd501ff,
 225                 .flags  = IORESOURCE_MEM,
 226         },
 227         [2] = {
 228                 .start  = 0xffd60000,
 229                 .end    = 0xffd601ff,
 230                 .flags  = IORESOURCE_MEM,
 231         }
 232 };
 233
 234 static struct intc_desc intcs_desc __initdata = {
 235         .name = "sh73a0-intcs",
 236         .resource = intcs_resources,
 237         .num_resources = ARRAY_SIZE(intcs_resources),
 238         .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
 239                            intcs_prio_registers, NULL, NULL),
 240 };
 241
 242 static struct irqaction sh73a0_intcs_cascade;
 243
 244 static irqreturn_t sh73a0_intcs_demux(int irq, void *dev_id)
 245 {
 246         unsigned int evtcodeas = ioread32((void __iomem *)dev_id);
 247
 248         generic_handle_irq(intcs_evt2irq(evtcodeas));
 249
 250         return IRQ_HANDLED;
 251 }
 252
 253 static int sh73a0_set_wake(struct irq_data *data, unsigned int on)
 254 {
 255         return 0; /* always allow wakeup */
 256 }
 257
 258 void __init sh73a0_init_irq(void)
 259 {
 260         void __iomem *gic_dist_base = __io(0xf0001000);
 261         void __iomem *gic_cpu_base = __io(0xf0000100);
 262         void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
 263
 264         gic_init(0, 29, gic_dist_base, gic_cpu_base);
 265         gic_arch_extn.irq_set_wake = sh73a0_set_wake;
 266
 267         register_intc_controller(&intcs_desc);
 268
 269         /* demux using INTEVTSA */
 270         sh73a0_intcs_cascade.name = "INTCS cascade";
 271         sh73a0_intcs_cascade.handler = sh73a0_intcs_demux;
 272         sh73a0_intcs_cascade.dev_id = intevtsa;
 273         setup_irq(gic_spi(50), &sh73a0_intcs_cascade);
 274 }