arch/arm/mach-shmobile/setup-sh7372.c

   1 /*
   2  * sh7372 processor support
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  * Copyright (C) 2008  Yoshihiro Shimoda
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/uio_driver.h>
  26 #include <linux/delay.h>
  27 #include <linux/input.h>
  28 #include <linux/io.h>
  29 #include <linux/serial_sci.h>
  30 #include <linux/sh_dma.h>
  31 #include <linux/sh_intc.h>
  32 #include <linux/sh_timer.h>
  33 #include <mach/hardware.h>
  34 #include <mach/sh7372.h>
  35 #include <asm/mach-types.h>
  36 #include <asm/mach/arch.h>
  37
  38 /* SCIFA0 */
  39 static struct plat_sci_port scif0_platform_data = {
  40         .mapbase        = 0xe6c40000,
  41         .flags          = UPF_BOOT_AUTOCONF,
  42         .scscr          = SCSCR_RE | SCSCR_TE,
  43         .scbrr_algo_id  = SCBRR_ALGO_4,
  44         .type           = PORT_SCIFA,
  45         .irqs           = { evt2irq(0x0c00), evt2irq(0x0c00),
  46                             evt2irq(0x0c00), evt2irq(0x0c00) },
  47 };
  48
  49 static struct platform_device scif0_device = {
  50         .name           = "sh-sci",
  51         .id             = 0,
  52         .dev            = {
  53                 .platform_data  = &scif0_platform_data,
  54         },
  55 };
  56
  57 /* SCIFA1 */
  58 static struct plat_sci_port scif1_platform_data = {
  59         .mapbase        = 0xe6c50000,
  60         .flags          = UPF_BOOT_AUTOCONF,
  61         .scscr          = SCSCR_RE | SCSCR_TE,
  62         .scbrr_algo_id  = SCBRR_ALGO_4,
  63         .type           = PORT_SCIFA,
  64         .irqs           = { evt2irq(0x0c20), evt2irq(0x0c20),
  65                             evt2irq(0x0c20), evt2irq(0x0c20) },
  66 };
  67
  68 static struct platform_device scif1_device = {
  69         .name           = "sh-sci",
  70         .id             = 1,
  71         .dev            = {
  72                 .platform_data  = &scif1_platform_data,
  73         },
  74 };
  75
  76 /* SCIFA2 */
  77 static struct plat_sci_port scif2_platform_data = {
  78         .mapbase        = 0xe6c60000,
  79         .flags          = UPF_BOOT_AUTOCONF,
  80         .scscr          = SCSCR_RE | SCSCR_TE,
  81         .scbrr_algo_id  = SCBRR_ALGO_4,
  82         .type           = PORT_SCIFA,
  83         .irqs           = { evt2irq(0x0c40), evt2irq(0x0c40),
  84                             evt2irq(0x0c40), evt2irq(0x0c40) },
  85 };
  86
  87 static struct platform_device scif2_device = {
  88         .name           = "sh-sci",
  89         .id             = 2,
  90         .dev            = {
  91                 .platform_data  = &scif2_platform_data,
  92         },
  93 };
  94
  95 /* SCIFA3 */
  96 static struct plat_sci_port scif3_platform_data = {
  97         .mapbase        = 0xe6c70000,
  98         .flags          = UPF_BOOT_AUTOCONF,
  99         .scscr          = SCSCR_RE | SCSCR_TE,
 100         .scbrr_algo_id  = SCBRR_ALGO_4,
 101         .type           = PORT_SCIFA,
 102         .irqs           = { evt2irq(0x0c60), evt2irq(0x0c60),
 103                             evt2irq(0x0c60), evt2irq(0x0c60) },
 104 };
 105
 106 static struct platform_device scif3_device = {
 107         .name           = "sh-sci",
 108         .id             = 3,
 109         .dev            = {
 110                 .platform_data  = &scif3_platform_data,
 111         },
 112 };
 113
 114 /* SCIFA4 */
 115 static struct plat_sci_port scif4_platform_data = {
 116         .mapbase        = 0xe6c80000,
 117         .flags          = UPF_BOOT_AUTOCONF,
 118         .scscr          = SCSCR_RE | SCSCR_TE,
 119         .scbrr_algo_id  = SCBRR_ALGO_4,
 120         .type           = PORT_SCIFA,
 121         .irqs           = { evt2irq(0x0d20), evt2irq(0x0d20),
 122                             evt2irq(0x0d20), evt2irq(0x0d20) },
 123 };
 124
 125 static struct platform_device scif4_device = {
 126         .name           = "sh-sci",
 127         .id             = 4,
 128         .dev            = {
 129                 .platform_data  = &scif4_platform_data,
 130         },
 131 };
 132
 133 /* SCIFA5 */
 134 static struct plat_sci_port scif5_platform_data = {
 135         .mapbase        = 0xe6cb0000,
 136         .flags          = UPF_BOOT_AUTOCONF,
 137         .scscr          = SCSCR_RE | SCSCR_TE,
 138         .scbrr_algo_id  = SCBRR_ALGO_4,
 139         .type           = PORT_SCIFA,
 140         .irqs           = { evt2irq(0x0d40), evt2irq(0x0d40),
 141                             evt2irq(0x0d40), evt2irq(0x0d40) },
 142 };
 143
 144 static struct platform_device scif5_device = {
 145         .name           = "sh-sci",
 146         .id             = 5,
 147         .dev            = {
 148                 .platform_data  = &scif5_platform_data,
 149         },
 150 };
 151
 152 /* SCIFB */
 153 static struct plat_sci_port scif6_platform_data = {
 154         .mapbase        = 0xe6c30000,
 155         .flags          = UPF_BOOT_AUTOCONF,
 156         .scscr          = SCSCR_RE | SCSCR_TE,
 157         .scbrr_algo_id  = SCBRR_ALGO_4,
 158         .type           = PORT_SCIFB,
 159         .irqs           = { evt2irq(0x0d60), evt2irq(0x0d60),
 160                             evt2irq(0x0d60), evt2irq(0x0d60) },
 161 };
 162
 163 static struct platform_device scif6_device = {
 164         .name           = "sh-sci",
 165         .id             = 6,
 166         .dev            = {
 167                 .platform_data  = &scif6_platform_data,
 168         },
 169 };
 170
 171 /* CMT */
 172 static struct sh_timer_config cmt2_platform_data = {
 173         .name = "CMT2",
 174         .channel_offset = 0x40,
 175         .timer_bit = 5,
 176         .clockevent_rating = 125,
 177         .clocksource_rating = 125,
 178 };
 179
 180 static struct resource cmt2_resources[] = {
 181         [0] = {
 182                 .name   = "CMT2",
 183                 .start  = 0xe6130040,
 184                 .end    = 0xe613004b,
 185                 .flags  = IORESOURCE_MEM,
 186         },
 187         [1] = {
 188                 .start  = evt2irq(0x0b80), /* CMT2 */
 189                 .flags  = IORESOURCE_IRQ,
 190         },
 191 };
 192
 193 static struct platform_device cmt2_device = {
 194         .name           = "sh_cmt",
 195         .id             = 2,
 196         .dev = {
 197                 .platform_data  = &cmt2_platform_data,
 198         },
 199         .resource       = cmt2_resources,
 200         .num_resources  = ARRAY_SIZE(cmt2_resources),
 201 };
 202
 203 /* TMU */
 204 static struct sh_timer_config tmu00_platform_data = {
 205         .name = "TMU00",
 206         .channel_offset = 0x4,
 207         .timer_bit = 0,
 208         .clockevent_rating = 200,
 209 };
 210
 211 static struct resource tmu00_resources[] = {
 212         [0] = {
 213                 .name   = "TMU00",
 214                 .start  = 0xfff60008,
 215                 .end    = 0xfff60013,
 216                 .flags  = IORESOURCE_MEM,
 217         },
 218         [1] = {
 219                 .start  = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
 220                 .flags  = IORESOURCE_IRQ,
 221         },
 222 };
 223
 224 static struct platform_device tmu00_device = {
 225         .name           = "sh_tmu",
 226         .id             = 0,
 227         .dev = {
 228                 .platform_data  = &tmu00_platform_data,
 229         },
 230         .resource       = tmu00_resources,
 231         .num_resources  = ARRAY_SIZE(tmu00_resources),
 232 };
 233
 234 static struct sh_timer_config tmu01_platform_data = {
 235         .name = "TMU01",
 236         .channel_offset = 0x10,
 237         .timer_bit = 1,
 238         .clocksource_rating = 200,
 239 };
 240
 241 static struct resource tmu01_resources[] = {
 242         [0] = {
 243                 .name   = "TMU01",
 244                 .start  = 0xfff60014,
 245                 .end    = 0xfff6001f,
 246                 .flags  = IORESOURCE_MEM,
 247         },
 248         [1] = {
 249                 .start  = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
 250                 .flags  = IORESOURCE_IRQ,
 251         },
 252 };
 253
 254 static struct platform_device tmu01_device = {
 255         .name           = "sh_tmu",
 256         .id             = 1,
 257         .dev = {
 258                 .platform_data  = &tmu01_platform_data,
 259         },
 260         .resource       = tmu01_resources,
 261         .num_resources  = ARRAY_SIZE(tmu01_resources),
 262 };
 263
 264 /* I2C */
 265 static struct resource iic0_resources[] = {
 266         [0] = {
 267                 .name   = "IIC0",
 268                 .start  = 0xFFF20000,
 269                 .end    = 0xFFF20425 - 1,
 270                 .flags  = IORESOURCE_MEM,
 271         },
 272         [1] = {
 273                 .start  = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
 274                 .end    = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
 275                 .flags  = IORESOURCE_IRQ,
 276         },
 277 };
 278
 279 static struct platform_device iic0_device = {
 280         .name           = "i2c-sh_mobile",
 281         .id             = 0, /* "i2c0" clock */
 282         .num_resources  = ARRAY_SIZE(iic0_resources),
 283         .resource       = iic0_resources,
 284 };
 285
 286 static struct resource iic1_resources[] = {
 287         [0] = {
 288                 .name   = "IIC1",
 289                 .start  = 0xE6C20000,
 290                 .end    = 0xE6C20425 - 1,
 291                 .flags  = IORESOURCE_MEM,
 292         },
 293         [1] = {
 294                 .start  = evt2irq(0x780), /* IIC1_ALI1 */
 295                 .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
 296                 .flags  = IORESOURCE_IRQ,
 297         },
 298 };
 299
 300 static struct platform_device iic1_device = {
 301         .name           = "i2c-sh_mobile",
 302         .id             = 1, /* "i2c1" clock */
 303         .num_resources  = ARRAY_SIZE(iic1_resources),
 304         .resource       = iic1_resources,
 305 };
 306
 307 /* DMA */
 308 /* Transmit sizes and respective CHCR register values */
 309 enum {
 310         XMIT_SZ_8BIT            = 0,
 311         XMIT_SZ_16BIT           = 1,
 312         XMIT_SZ_32BIT           = 2,
 313         XMIT_SZ_64BIT           = 7,
 314         XMIT_SZ_128BIT          = 3,
 315         XMIT_SZ_256BIT          = 4,
 316         XMIT_SZ_512BIT          = 5,
 317 };
 318
 319 /* log2(size / 8) - used to calculate number of transfers */
 320 #define TS_SHIFT {                      \
 321         [XMIT_SZ_8BIT]          = 0,    \
 322         [XMIT_SZ_16BIT]         = 1,    \
 323         [XMIT_SZ_32BIT]         = 2,    \
 324         [XMIT_SZ_64BIT]         = 3,    \
 325         [XMIT_SZ_128BIT]        = 4,    \
 326         [XMIT_SZ_256BIT]        = 5,    \
 327         [XMIT_SZ_512BIT]        = 6,    \
 328 }
 329
 330 #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
 331                          (((i) & 0xc) << (20 - 2)))
 332
 333 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
 334         {
 335                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 336                 .addr           = 0xe6c40020,
 337                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 338                 .mid_rid        = 0x21,
 339         }, {
 340                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 341                 .addr           = 0xe6c40024,
 342                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 343                 .mid_rid        = 0x22,
 344         }, {
 345                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 346                 .addr           = 0xe6c50020,
 347                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 348                 .mid_rid        = 0x25,
 349         }, {
 350                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 351                 .addr           = 0xe6c50024,
 352                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 353                 .mid_rid        = 0x26,
 354         }, {
 355                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 356                 .addr           = 0xe6c60020,
 357                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 358                 .mid_rid        = 0x29,
 359         }, {
 360                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 361                 .addr           = 0xe6c60024,
 362                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 363                 .mid_rid        = 0x2a,
 364         }, {
 365                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 366                 .addr           = 0xe6c70020,
 367                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 368                 .mid_rid        = 0x2d,
 369         }, {
 370                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 371                 .addr           = 0xe6c70024,
 372                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 373                 .mid_rid        = 0x2e,
 374         }, {
 375                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 376                 .addr           = 0xe6c80020,
 377                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 378                 .mid_rid        = 0x39,
 379         }, {
 380                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 381                 .addr           = 0xe6c80024,
 382                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 383                 .mid_rid        = 0x3a,
 384         }, {
 385                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 386                 .addr           = 0xe6cb0020,
 387                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 388                 .mid_rid        = 0x35,
 389         }, {
 390                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 391                 .addr           = 0xe6cb0024,
 392                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 393                 .mid_rid        = 0x36,
 394         }, {
 395                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 396                 .addr           = 0xe6c30040,
 397                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 398                 .mid_rid        = 0x3d,
 399         }, {
 400                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 401                 .addr           = 0xe6c30060,
 402                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 403                 .mid_rid        = 0x3e,
 404         }, {
 405                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 406                 .addr           = 0xe6850030,
 407                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 408                 .mid_rid        = 0xc1,
 409         }, {
 410                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 411                 .addr           = 0xe6850030,
 412                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 413                 .mid_rid        = 0xc2,
 414         }, {
 415                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 416                 .addr           = 0xe6860030,
 417                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 418                 .mid_rid        = 0xc9,
 419         }, {
 420                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 421                 .addr           = 0xe6860030,
 422                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 423                 .mid_rid        = 0xca,
 424         }, {
 425                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 426                 .addr           = 0xe6870030,
 427                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 428                 .mid_rid        = 0xcd,
 429         }, {
 430                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 431                 .addr           = 0xe6870030,
 432                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 433                 .mid_rid        = 0xce,
 434         }, {
 435                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 436                 .addr           = 0xe6bd0034,
 437                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
 438                 .mid_rid        = 0xd1,
 439         }, {
 440                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 441                 .addr           = 0xe6bd0034,
 442                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
 443                 .mid_rid        = 0xd2,
 444         },
 445 };
 446
 447 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
 448         {
 449                 .offset = 0,
 450                 .dmars = 0,
 451                 .dmars_bit = 0,
 452         }, {
 453                 .offset = 0x10,
 454                 .dmars = 0,
 455                 .dmars_bit = 8,
 456         }, {
 457                 .offset = 0x20,
 458                 .dmars = 4,
 459                 .dmars_bit = 0,
 460         }, {
 461                 .offset = 0x30,
 462                 .dmars = 4,
 463                 .dmars_bit = 8,
 464         }, {
 465                 .offset = 0x50,
 466                 .dmars = 8,
 467                 .dmars_bit = 0,
 468         }, {
 469                 .offset = 0x60,
 470                 .dmars = 8,
 471                 .dmars_bit = 8,
 472         }
 473 };
 474
 475 static const unsigned int ts_shift[] = TS_SHIFT;
 476
 477 static struct sh_dmae_pdata dma_platform_data = {
 478         .slave          = sh7372_dmae_slaves,
 479         .slave_num      = ARRAY_SIZE(sh7372_dmae_slaves),
 480         .channel        = sh7372_dmae_channels,
 481         .channel_num    = ARRAY_SIZE(sh7372_dmae_channels),
 482         .ts_low_shift   = 3,
 483         .ts_low_mask    = 0x18,
 484         .ts_high_shift  = (20 - 2),     /* 2 bits for shifted low TS */
 485         .ts_high_mask   = 0x00300000,
 486         .ts_shift       = ts_shift,
 487         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 488         .dmaor_init     = DMAOR_DME,
 489 };
 490
 491 /* Resource order important! */
 492 static struct resource sh7372_dmae0_resources[] = {
 493         {
 494                 /* Channel registers and DMAOR */
 495                 .start  = 0xfe008020,
 496                 .end    = 0xfe00808f,
 497                 .flags  = IORESOURCE_MEM,
 498         },
 499         {
 500                 /* DMARSx */
 501                 .start  = 0xfe009000,
 502                 .end    = 0xfe00900b,
 503                 .flags  = IORESOURCE_MEM,
 504         },
 505         {
 506                 /* DMA error IRQ */
 507                 .start  = evt2irq(0x20c0),
 508                 .end    = evt2irq(0x20c0),
 509                 .flags  = IORESOURCE_IRQ,
 510         },
 511         {
 512                 /* IRQ for channels 0-5 */
 513                 .start  = evt2irq(0x2000),
 514                 .end    = evt2irq(0x20a0),
 515                 .flags  = IORESOURCE_IRQ,
 516         },
 517 };
 518
 519 /* Resource order important! */
 520 static struct resource sh7372_dmae1_resources[] = {
 521         {
 522                 /* Channel registers and DMAOR */
 523                 .start  = 0xfe018020,
 524                 .end    = 0xfe01808f,
 525                 .flags  = IORESOURCE_MEM,
 526         },
 527         {
 528                 /* DMARSx */
 529                 .start  = 0xfe019000,
 530                 .end    = 0xfe01900b,
 531                 .flags  = IORESOURCE_MEM,
 532         },
 533         {
 534                 /* DMA error IRQ */
 535                 .start  = evt2irq(0x21c0),
 536                 .end    = evt2irq(0x21c0),
 537                 .flags  = IORESOURCE_IRQ,
 538         },
 539         {
 540                 /* IRQ for channels 0-5 */
 541                 .start  = evt2irq(0x2100),
 542                 .end    = evt2irq(0x21a0),
 543                 .flags  = IORESOURCE_IRQ,
 544         },
 545 };
 546
 547 /* Resource order important! */
 548 static struct resource sh7372_dmae2_resources[] = {
 549         {
 550                 /* Channel registers and DMAOR */
 551                 .start  = 0xfe028020,
 552                 .end    = 0xfe02808f,
 553                 .flags  = IORESOURCE_MEM,
 554         },
 555         {
 556                 /* DMARSx */
 557                 .start  = 0xfe029000,
 558                 .end    = 0xfe02900b,
 559                 .flags  = IORESOURCE_MEM,
 560         },
 561         {
 562                 /* DMA error IRQ */
 563                 .start  = evt2irq(0x22c0),
 564                 .end    = evt2irq(0x22c0),
 565                 .flags  = IORESOURCE_IRQ,
 566         },
 567         {
 568                 /* IRQ for channels 0-5 */
 569                 .start  = evt2irq(0x2200),
 570                 .end    = evt2irq(0x22a0),
 571                 .flags  = IORESOURCE_IRQ,
 572         },
 573 };
 574
 575 static struct platform_device dma0_device = {
 576         .name           = "sh-dma-engine",
 577         .id             = 0,
 578         .resource       = sh7372_dmae0_resources,
 579         .num_resources  = ARRAY_SIZE(sh7372_dmae0_resources),
 580         .dev            = {
 581                 .platform_data  = &dma_platform_data,
 582         },
 583 };
 584
 585 static struct platform_device dma1_device = {
 586         .name           = "sh-dma-engine",
 587         .id             = 1,
 588         .resource       = sh7372_dmae1_resources,
 589         .num_resources  = ARRAY_SIZE(sh7372_dmae1_resources),
 590         .dev            = {
 591                 .platform_data  = &dma_platform_data,
 592         },
 593 };
 594
 595 static struct platform_device dma2_device = {
 596         .name           = "sh-dma-engine",
 597         .id             = 2,
 598         .resource       = sh7372_dmae2_resources,
 599         .num_resources  = ARRAY_SIZE(sh7372_dmae2_resources),
 600         .dev            = {
 601                 .platform_data  = &dma_platform_data,
 602         },
 603 };
 604
 605 /* VPU */
 606 static struct uio_info vpu_platform_data = {
 607         .name = "VPU5HG",
 608         .version = "0",
 609         .irq = intcs_evt2irq(0x980),
 610 };
 611
 612 static struct resource vpu_resources[] = {
 613         [0] = {
 614                 .name   = "VPU",
 615                 .start  = 0xfe900000,
 616                 .end    = 0xfe900157,
 617                 .flags  = IORESOURCE_MEM,
 618         },
 619 };
 620
 621 static struct platform_device vpu_device = {
 622         .name           = "uio_pdrv_genirq",
 623         .id             = 0,
 624         .dev = {
 625                 .platform_data  = &vpu_platform_data,
 626         },
 627         .resource       = vpu_resources,
 628         .num_resources  = ARRAY_SIZE(vpu_resources),
 629 };
 630
 631 /* VEU0 */
 632 static struct uio_info veu0_platform_data = {
 633         .name = "VEU0",
 634         .version = "0",
 635         .irq = intcs_evt2irq(0x700),
 636 };
 637
 638 static struct resource veu0_resources[] = {
 639         [0] = {
 640                 .name   = "VEU0",
 641                 .start  = 0xfe920000,
 642                 .end    = 0xfe9200cb,
 643                 .flags  = IORESOURCE_MEM,
 644         },
 645 };
 646
 647 static struct platform_device veu0_device = {
 648         .name           = "uio_pdrv_genirq",
 649         .id             = 1,
 650         .dev = {
 651                 .platform_data  = &veu0_platform_data,
 652         },
 653         .resource       = veu0_resources,
 654         .num_resources  = ARRAY_SIZE(veu0_resources),
 655 };
 656
 657 /* VEU1 */
 658 static struct uio_info veu1_platform_data = {
 659         .name = "VEU1",
 660         .version = "0",
 661         .irq = intcs_evt2irq(0x720),
 662 };
 663
 664 static struct resource veu1_resources[] = {
 665         [0] = {
 666                 .name   = "VEU1",
 667                 .start  = 0xfe924000,
 668                 .end    = 0xfe9240cb,
 669                 .flags  = IORESOURCE_MEM,
 670         },
 671 };
 672
 673 static struct platform_device veu1_device = {
 674         .name           = "uio_pdrv_genirq",
 675         .id             = 2,
 676         .dev = {
 677                 .platform_data  = &veu1_platform_data,
 678         },
 679         .resource       = veu1_resources,
 680         .num_resources  = ARRAY_SIZE(veu1_resources),
 681 };
 682
 683 /* VEU2 */
 684 static struct uio_info veu2_platform_data = {
 685         .name = "VEU2",
 686         .version = "0",
 687         .irq = intcs_evt2irq(0x740),
 688 };
 689
 690 static struct resource veu2_resources[] = {
 691         [0] = {
 692                 .name   = "VEU2",
 693                 .start  = 0xfe928000,
 694                 .end    = 0xfe928307,
 695                 .flags  = IORESOURCE_MEM,
 696         },
 697 };
 698
 699 static struct platform_device veu2_device = {
 700         .name           = "uio_pdrv_genirq",
 701         .id             = 3,
 702         .dev = {
 703                 .platform_data  = &veu2_platform_data,
 704         },
 705         .resource       = veu2_resources,
 706         .num_resources  = ARRAY_SIZE(veu2_resources),
 707 };
 708
 709 /* VEU3 */
 710 static struct uio_info veu3_platform_data = {
 711         .name = "VEU3",
 712         .version = "0",
 713         .irq = intcs_evt2irq(0x760),
 714 };
 715
 716 static struct resource veu3_resources[] = {
 717         [0] = {
 718                 .name   = "VEU3",
 719                 .start  = 0xfe92c000,
 720                 .end    = 0xfe92c307,
 721                 .flags  = IORESOURCE_MEM,
 722         },
 723 };
 724
 725 static struct platform_device veu3_device = {
 726         .name           = "uio_pdrv_genirq",
 727         .id             = 4,
 728         .dev = {
 729                 .platform_data  = &veu3_platform_data,
 730         },
 731         .resource       = veu3_resources,
 732         .num_resources  = ARRAY_SIZE(veu3_resources),
 733 };
 734
 735 /* JPU */
 736 static struct uio_info jpu_platform_data = {
 737         .name = "JPU",
 738         .version = "0",
 739         .irq = intcs_evt2irq(0x560),
 740 };
 741
 742 static struct resource jpu_resources[] = {
 743         [0] = {
 744                 .name   = "JPU",
 745                 .start  = 0xfe980000,
 746                 .end    = 0xfe9902d3,
 747                 .flags  = IORESOURCE_MEM,
 748         },
 749 };
 750
 751 static struct platform_device jpu_device = {
 752         .name           = "uio_pdrv_genirq",
 753         .id             = 5,
 754         .dev = {
 755                 .platform_data  = &jpu_platform_data,
 756         },
 757         .resource       = jpu_resources,
 758         .num_resources  = ARRAY_SIZE(jpu_resources),
 759 };
 760
 761 /* SPU2DSP0 */
 762 static struct uio_info spu0_platform_data = {
 763         .name = "SPU2DSP0",
 764         .version = "0",
 765         .irq = evt2irq(0x1800),
 766 };
 767
 768 static struct resource spu0_resources[] = {
 769         [0] = {
 770                 .name   = "SPU2DSP0",
 771                 .start  = 0xfe200000,
 772                 .end    = 0xfe2fffff,
 773                 .flags  = IORESOURCE_MEM,
 774         },
 775 };
 776
 777 static struct platform_device spu0_device = {
 778         .name           = "uio_pdrv_genirq",
 779         .id             = 6,
 780         .dev = {
 781                 .platform_data  = &spu0_platform_data,
 782         },
 783         .resource       = spu0_resources,
 784         .num_resources  = ARRAY_SIZE(spu0_resources),
 785 };
 786
 787 /* SPU2DSP1 */
 788 static struct uio_info spu1_platform_data = {
 789         .name = "SPU2DSP1",
 790         .version = "0",
 791         .irq = evt2irq(0x1820),
 792 };
 793
 794 static struct resource spu1_resources[] = {
 795         [0] = {
 796                 .name   = "SPU2DSP1",
 797                 .start  = 0xfe300000,
 798                 .end    = 0xfe3fffff,
 799                 .flags  = IORESOURCE_MEM,
 800         },
 801 };
 802
 803 static struct platform_device spu1_device = {
 804         .name           = "uio_pdrv_genirq",
 805         .id             = 7,
 806         .dev = {
 807                 .platform_data  = &spu1_platform_data,
 808         },
 809         .resource       = spu1_resources,
 810         .num_resources  = ARRAY_SIZE(spu1_resources),
 811 };
 812
 813 static struct platform_device *sh7372_early_devices[] __initdata = {
 814         &scif0_device,
 815         &scif1_device,
 816         &scif2_device,
 817         &scif3_device,
 818         &scif4_device,
 819         &scif5_device,
 820         &scif6_device,
 821         &cmt2_device,
 822         &tmu00_device,
 823         &tmu01_device,
 824 };
 825
 826 static struct platform_device *sh7372_late_devices[] __initdata = {
 827         &iic0_device,
 828         &iic1_device,
 829         &dma0_device,
 830         &dma1_device,
 831         &dma2_device,
 832         &vpu_device,
 833         &veu0_device,
 834         &veu1_device,
 835         &veu2_device,
 836         &veu3_device,
 837         &jpu_device,
 838         &spu0_device,
 839         &spu1_device,
 840 };
 841
 842 void __init sh7372_add_standard_devices(void)
 843 {
 844         sh7372_init_pm_domain(&sh7372_a4lc);
 845         sh7372_init_pm_domain(&sh7372_a4mp);
 846         sh7372_init_pm_domain(&sh7372_d4);
 847         sh7372_init_pm_domain(&sh7372_a3rv);
 848         sh7372_init_pm_domain(&sh7372_a3ri);
 849         sh7372_init_pm_domain(&sh7372_a3sg);
 850
 851         platform_add_devices(sh7372_early_devices,
 852                             ARRAY_SIZE(sh7372_early_devices));
 853
 854         platform_add_devices(sh7372_late_devices,
 855                             ARRAY_SIZE(sh7372_late_devices));
 856
 857         sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device);
 858         sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device);
 859         sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device);
 860 }
 861
 862 void __init sh7372_add_early_devices(void)
 863 {
 864         early_platform_add_devices(sh7372_early_devices,
 865                                    ARRAY_SIZE(sh7372_early_devices));
 866 }