| blob | 2df55042f166362317b9e2208b45dab9125e76c2 |
1 comment "Processor Type"
3 # Select CPU types depending on the architecture selected. This selects
4 # which CPUs we support in the kernel image, and the compiler instruction
5 # optimiser behaviour.
7 # ARM610
8 config CPU_ARM610
9 bool "Support ARM610 processor" if ARCH_RPC
10 select CPU_32v3
11 select CPU_CACHE_V3
12 select CPU_CACHE_VIVT
13 select CPU_CP15_MMU
14 select CPU_COPY_V3 if MMU
15 select CPU_TLB_V3 if MMU
16 select CPU_PABRT_LEGACY
17 help
18 The ARM610 is the successor to the ARM3 processor
19 and was produced by VLSI Technology Inc.
21 Say Y if you want support for the ARM610 processor.
22 Otherwise, say N.
24 # ARM7TDMI
25 config CPU_ARM7TDMI
26 bool "Support ARM7TDMI processor"
27 depends on !MMU
28 select CPU_32v4T
29 select CPU_ABRT_LV4T
30 select CPU_PABRT_LEGACY
31 select CPU_CACHE_V4
32 help
33 A 32-bit RISC microprocessor based on the ARM7 processor core
34 which has no memory control unit and cache.
36 Say Y if you want support for the ARM7TDMI processor.
37 Otherwise, say N.
39 # ARM710
40 config CPU_ARM710
41 bool "Support ARM710 processor" if ARCH_RPC
42 select CPU_32v3
43 select CPU_CACHE_V3
44 select CPU_CACHE_VIVT
45 select CPU_CP15_MMU
46 select CPU_COPY_V3 if MMU
47 select CPU_TLB_V3 if MMU
48 select CPU_PABRT_LEGACY
49 help
50 A 32-bit RISC microprocessor based on the ARM7 processor core
51 designed by Advanced RISC Machines Ltd. The ARM710 is the
52 successor to the ARM610 processor. It was released in
53 July 1994 by VLSI Technology Inc.
55 Say Y if you want support for the ARM710 processor.
56 Otherwise, say N.
58 # ARM720T
59 config CPU_ARM720T
60 bool "Support ARM720T processor" if ARCH_INTEGRATOR
61 select CPU_32v4T
62 select CPU_ABRT_LV4T
63 select CPU_PABRT_LEGACY
64 select CPU_CACHE_V4
65 select CPU_CACHE_VIVT
66 select CPU_CP15_MMU
67 select CPU_COPY_V4WT if MMU
68 select CPU_TLB_V4WT if MMU
69 help
70 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
71 MMU built around an ARM7TDMI core.
73 Say Y if you want support for the ARM720T processor.
74 Otherwise, say N.
76 # ARM740T
77 config CPU_ARM740T
78 bool "Support ARM740T processor" if ARCH_INTEGRATOR
79 depends on !MMU
80 select CPU_32v4T
81 select CPU_ABRT_LV4T
82 select CPU_PABRT_LEGACY
83 select CPU_CACHE_V3 # although the core is v4t
84 select CPU_CP15_MPU
85 help
86 A 32-bit RISC processor with 8KB cache or 4KB variants,
87 write buffer and MPU(Protection Unit) built around
88 an ARM7TDMI core.
90 Say Y if you want support for the ARM740T processor.
91 Otherwise, say N.
93 # ARM9TDMI
94 config CPU_ARM9TDMI
95 bool "Support ARM9TDMI processor"
96 depends on !MMU
97 select CPU_32v4T
98 select CPU_ABRT_NOMMU
99 select CPU_PABRT_LEGACY
100 select CPU_CACHE_V4
101 help
102 A 32-bit RISC microprocessor based on the ARM9 processor core
103 which has no memory control unit and cache.
105 Say Y if you want support for the ARM9TDMI processor.
106 Otherwise, say N.
108 # ARM920T
109 config CPU_ARM920T
110 bool "Support ARM920T processor" if ARCH_INTEGRATOR
111 select CPU_32v4T
112 select CPU_ABRT_EV4T
113 select CPU_PABRT_LEGACY
114 select CPU_CACHE_V4WT
115 select CPU_CACHE_VIVT
116 select CPU_CP15_MMU
117 select CPU_COPY_V4WB if MMU
118 select CPU_TLB_V4WBI if MMU
119 help
120 The ARM920T is licensed to be produced by numerous vendors,
121 and is used in the Cirrus EP93xx and the Samsung S3C2410.
123 Say Y if you want support for the ARM920T processor.
124 Otherwise, say N.
126 # ARM922T
127 config CPU_ARM922T
128 bool "Support ARM922T processor" if ARCH_INTEGRATOR
129 select CPU_32v4T
130 select CPU_ABRT_EV4T
131 select CPU_PABRT_LEGACY
132 select CPU_CACHE_V4WT
133 select CPU_CACHE_VIVT
134 select CPU_CP15_MMU
135 select CPU_COPY_V4WB if MMU
136 select CPU_TLB_V4WBI if MMU
137 help
138 The ARM922T is a version of the ARM920T, but with smaller
139 instruction and data caches. It is used in Altera's
140 Excalibur XA device family and Micrel's KS8695 Centaur.
142 Say Y if you want support for the ARM922T processor.
143 Otherwise, say N.
145 # ARM925T
146 config CPU_ARM925T
147 bool "Support ARM925T processor" if ARCH_OMAP1
148 select CPU_32v4T
149 select CPU_ABRT_EV4T
150 select CPU_PABRT_LEGACY
151 select CPU_CACHE_V4WT
152 select CPU_CACHE_VIVT
153 select CPU_CP15_MMU
154 select CPU_COPY_V4WB if MMU
155 select CPU_TLB_V4WBI if MMU
156 help
157 The ARM925T is a mix between the ARM920T and ARM926T, but with
158 different instruction and data caches. It is used in TI's OMAP
159 device family.
161 Say Y if you want support for the ARM925T processor.
162 Otherwise, say N.
164 # ARM926T
165 config CPU_ARM926T
166 bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
167 select CPU_32v5
168 select CPU_ABRT_EV5TJ
169 select CPU_PABRT_LEGACY
170 select CPU_CACHE_VIVT
171 select CPU_CP15_MMU
172 select CPU_COPY_V4WB if MMU
173 select CPU_TLB_V4WBI if MMU
174 help
175 This is a variant of the ARM920. It has slightly different
176 instruction sequences for cache and TLB operations. Curiously,
177 there is no documentation on it at the ARM corporate website.
179 Say Y if you want support for the ARM926T processor.
180 Otherwise, say N.
182 # FA526
183 config CPU_FA526
184 bool
185 select CPU_32v4
186 select CPU_ABRT_EV4
187 select CPU_PABRT_LEGACY
188 select CPU_CACHE_VIVT
189 select CPU_CP15_MMU
190 select CPU_CACHE_FA
191 select CPU_COPY_FA if MMU
192 select CPU_TLB_FA if MMU
193 help
194 The FA526 is a version of the ARMv4 compatible processor with
195 Branch Target Buffer, Unified TLB and cache line size 16.
197 Say Y if you want support for the FA526 processor.
198 Otherwise, say N.
200 # ARM940T
201 config CPU_ARM940T
202 bool "Support ARM940T processor" if ARCH_INTEGRATOR
203 depends on !MMU
204 select CPU_32v4T
205 select CPU_ABRT_NOMMU
206 select CPU_PABRT_LEGACY
207 select CPU_CACHE_VIVT
208 select CPU_CP15_MPU
209 help
210 ARM940T is a member of the ARM9TDMI family of general-
211 purpose microprocessors with MPU and separate 4KB
212 instruction and 4KB data cases, each with a 4-word line
213 length.
215 Say Y if you want support for the ARM940T processor.
216 Otherwise, say N.
218 # ARM946E-S
219 config CPU_ARM946E
220 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
221 depends on !MMU
222 select CPU_32v5
223 select CPU_ABRT_NOMMU
224 select CPU_PABRT_LEGACY
225 select CPU_CACHE_VIVT
226 select CPU_CP15_MPU
227 help
228 ARM946E-S is a member of the ARM9E-S family of high-
229 performance, 32-bit system-on-chip processor solutions.
230 The TCM and ARMv5TE 32-bit instruction set is supported.
232 Say Y if you want support for the ARM946E-S processor.
233 Otherwise, say N.
235 # ARM1020 - needs validating
236 config CPU_ARM1020
237 bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
238 select CPU_32v5
239 select CPU_ABRT_EV4T
240 select CPU_PABRT_LEGACY
241 select CPU_CACHE_V4WT
242 select CPU_CACHE_VIVT
243 select CPU_CP15_MMU
244 select CPU_COPY_V4WB if MMU
245 select CPU_TLB_V4WBI if MMU
246 help
247 The ARM1020 is the 32K cached version of the ARM10 processor,
248 with an addition of a floating-point unit.
250 Say Y if you want support for the ARM1020 processor.
251 Otherwise, say N.
253 # ARM1020E - needs validating
254 config CPU_ARM1020E
255 bool "Support ARM1020E processor" if ARCH_INTEGRATOR
256 select CPU_32v5
257 select CPU_ABRT_EV4T
258 select CPU_PABRT_LEGACY
259 select CPU_CACHE_V4WT
260 select CPU_CACHE_VIVT
261 select CPU_CP15_MMU
262 select CPU_COPY_V4WB if MMU
263 select CPU_TLB_V4WBI if MMU
264 depends on n
266 # ARM1022E
267 config CPU_ARM1022
268 bool "Support ARM1022E processor" if ARCH_INTEGRATOR
269 select CPU_32v5
270 select CPU_ABRT_EV4T
271 select CPU_PABRT_LEGACY
272 select CPU_CACHE_VIVT
273 select CPU_CP15_MMU
274 select CPU_COPY_V4WB if MMU # can probably do better
275 select CPU_TLB_V4WBI if MMU
276 help
277 The ARM1022E is an implementation of the ARMv5TE architecture
278 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
279 embedded trace macrocell, and a floating-point unit.
281 Say Y if you want support for the ARM1022E processor.
282 Otherwise, say N.
284 # ARM1026EJ-S
285 config CPU_ARM1026
286 bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
287 select CPU_32v5
288 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
289 select CPU_PABRT_LEGACY
290 select CPU_CACHE_VIVT
291 select CPU_CP15_MMU
292 select CPU_COPY_V4WB if MMU # can probably do better
293 select CPU_TLB_V4WBI if MMU
294 help
295 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
296 based upon the ARM10 integer core.
298 Say Y if you want support for the ARM1026EJ-S processor.
299 Otherwise, say N.
301 # SA110
302 config CPU_SA110
303 bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
304 select CPU_32v3 if ARCH_RPC
305 select CPU_32v4 if !ARCH_RPC
306 select CPU_ABRT_EV4
307 select CPU_PABRT_LEGACY
308 select CPU_CACHE_V4WB
309 select CPU_CACHE_VIVT
310 select CPU_CP15_MMU
311 select CPU_COPY_V4WB if MMU
312 select CPU_TLB_V4WB if MMU
313 help
314 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
315 is available at five speeds ranging from 100 MHz to 233 MHz.
316 More information is available at
317 <http://developer.intel.com/design/strong/sa110.htm>.
319 Say Y if you want support for the SA-110 processor.
320 Otherwise, say N.
322 # SA1100
323 config CPU_SA1100
324 bool
325 select CPU_32v4
326 select CPU_ABRT_EV4
327 select CPU_PABRT_LEGACY
328 select CPU_CACHE_V4WB
329 select CPU_CACHE_VIVT
330 select CPU_CP15_MMU
331 select CPU_TLB_V4WB if MMU
333 # XScale
334 config CPU_XSCALE
335 bool
336 select CPU_32v5
337 select CPU_ABRT_EV5T
338 select CPU_PABRT_LEGACY
339 select CPU_CACHE_VIVT
340 select CPU_CP15_MMU
341 select CPU_TLB_V4WBI if MMU
343 # XScale Core Version 3
344 config CPU_XSC3
345 bool
346 select CPU_32v5
347 select CPU_ABRT_EV5T
348 select CPU_PABRT_LEGACY
349 select CPU_CACHE_VIVT
350 select CPU_CP15_MMU
351 select CPU_TLB_V4WBI if MMU
352 select IO_36
354 # Marvell PJ1 (Mohawk)
355 config CPU_MOHAWK
356 bool
357 select CPU_32v5
358 select CPU_ABRT_EV5T
359 select CPU_PABRT_LEGACY
360 select CPU_CACHE_VIVT
361 select CPU_CP15_MMU
362 select CPU_TLB_V4WBI if MMU
363 select CPU_COPY_V4WB if MMU
365 # Feroceon
366 config CPU_FEROCEON
367 bool
368 select CPU_32v5
369 select CPU_ABRT_EV5T
370 select CPU_PABRT_LEGACY
371 select CPU_CACHE_VIVT
372 select CPU_CP15_MMU
373 select CPU_COPY_FEROCEON if MMU
374 select CPU_TLB_FEROCEON if MMU
376 config CPU_FEROCEON_OLD_ID
377 bool "Accept early Feroceon cores with an ARM926 ID"
378 depends on CPU_FEROCEON && !CPU_ARM926T
379 default y
380 help
381 This enables the usage of some old Feroceon cores
382 for which the CPU ID is equal to the ARM926 ID.
383 Relevant for Feroceon-1850 and early Feroceon-2850.
385 # Marvell PJ4
386 config CPU_PJ4
387 bool
388 select CPU_V7
389 select ARM_THUMBEE
391 # ARMv6
392 config CPU_V6
393 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
394 select CPU_32v6
395 select CPU_ABRT_EV6
396 select CPU_PABRT_V6
397 select CPU_CACHE_V6
398 select CPU_CACHE_VIPT
399 select CPU_CP15_MMU
400 select CPU_HAS_ASID if MMU
401 select CPU_COPY_V6 if MMU
402 select CPU_TLB_V6 if MMU
404 # ARMv6k
405 config CPU_V6K
406 bool "Support ARM V6K processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
407 select CPU_32v6
408 select CPU_32v6K
409 select CPU_ABRT_EV6
410 select CPU_PABRT_V6
411 select CPU_CACHE_V6
412 select CPU_CACHE_VIPT
413 select CPU_CP15_MMU
414 select CPU_HAS_ASID if MMU
415 select CPU_COPY_V6 if MMU
416 select CPU_TLB_V6 if MMU
418 # ARMv7
419 config CPU_V7
420 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
421 select CPU_32v6K
422 select CPU_32v7
423 select CPU_ABRT_EV7
424 select CPU_PABRT_V7
425 select CPU_CACHE_V7
426 select CPU_CACHE_VIPT
427 select CPU_CP15_MMU
428 select CPU_HAS_ASID if MMU
429 select CPU_COPY_V6 if MMU
430 select CPU_TLB_V7 if MMU
432 # Figure out what processor architecture version we should be using.
433 # This defines the compiler instruction set which depends on the machine type.
434 config CPU_32v3
435 bool
436 select TLS_REG_EMUL if SMP || !MMU
437 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
438 select CPU_USE_DOMAINS if MMU
440 config CPU_32v4
441 bool
442 select TLS_REG_EMUL if SMP || !MMU
443 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
444 select CPU_USE_DOMAINS if MMU
446 config CPU_32v4T
447 bool
448 select TLS_REG_EMUL if SMP || !MMU
449 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
450 select CPU_USE_DOMAINS if MMU
452 config CPU_32v5
453 bool
454 select TLS_REG_EMUL if SMP || !MMU
455 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
456 select CPU_USE_DOMAINS if MMU
458 config CPU_32v6
459 bool
460 select TLS_REG_EMUL if !CPU_32v6K && !MMU
461 select CPU_USE_DOMAINS if CPU_V6 && MMU
463 config CPU_32v6K
464 bool
466 config CPU_32v7
467 bool
469 # The abort model
470 config CPU_ABRT_NOMMU
471 bool
473 config CPU_ABRT_EV4
474 bool
476 config CPU_ABRT_EV4T
477 bool
479 config CPU_ABRT_LV4T
480 bool
482 config CPU_ABRT_EV5T
483 bool
485 config CPU_ABRT_EV5TJ
486 bool
488 config CPU_ABRT_EV6
489 bool
491 config CPU_ABRT_EV7
492 bool
494 config CPU_PABRT_LEGACY
495 bool
497 config CPU_PABRT_V6
498 bool
500 config CPU_PABRT_V7
501 bool
503 # The cache model
504 config CPU_CACHE_V3
505 bool
507 config CPU_CACHE_V4
508 bool
510 config CPU_CACHE_V4WT
511 bool
513 config CPU_CACHE_V4WB
514 bool
516 config CPU_CACHE_V6
517 bool
519 config CPU_CACHE_V7
520 bool
522 config CPU_CACHE_VIVT
523 bool
525 config CPU_CACHE_VIPT
526 bool
528 config CPU_CACHE_FA
529 bool
531 if MMU
532 # The copy-page model
533 config CPU_COPY_V3
534 bool
536 config CPU_COPY_V4WT
537 bool
539 config CPU_COPY_V4WB
540 bool
542 config CPU_COPY_FEROCEON
543 bool
545 config CPU_COPY_FA
546 bool
548 config CPU_COPY_V6
549 bool
551 # This selects the TLB model
552 config CPU_TLB_V3
553 bool
554 help
555 ARM Architecture Version 3 TLB.
557 config CPU_TLB_V4WT
558 bool
559 help
560 ARM Architecture Version 4 TLB with writethrough cache.
562 config CPU_TLB_V4WB
563 bool
564 help
565 ARM Architecture Version 4 TLB with writeback cache.
567 config CPU_TLB_V4WBI
568 bool
569 help
570 ARM Architecture Version 4 TLB with writeback cache and invalidate
571 instruction cache entry.
573 config CPU_TLB_FEROCEON
574 bool
575 help
576 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
578 config CPU_TLB_FA
579 bool
580 help
581 Faraday ARM FA526 architecture, unified TLB with writeback cache
582 and invalidate instruction cache entry. Branch target buffer is
583 also supported.
585 config CPU_TLB_V6
586 bool
588 config CPU_TLB_V7
589 bool
591 config VERIFY_PERMISSION_FAULT
592 bool
593 endif
595 config CPU_HAS_ASID
596 bool
597 help
598 This indicates whether the CPU has the ASID register; used to
599 tag TLB and possibly cache entries.
601 config CPU_CP15
602 bool
603 help
604 Processor has the CP15 register.
606 config CPU_CP15_MMU
607 bool
608 select CPU_CP15
609 help
610 Processor has the CP15 register, which has MMU related registers.
612 config CPU_CP15_MPU
613 bool
614 select CPU_CP15
615 help
616 Processor has the CP15 register, which has MPU related registers.
618 config CPU_USE_DOMAINS
619 bool
620 help
621 This option enables or disables the use of domain switching
622 via the set_fs() function.
624 #
625 # CPU supports 36-bit I/O
626 #
627 config IO_36
628 bool
630 comment "Processor Features"
632 config ARM_LPAE
633 bool "Support for the Large Physical Address Extension"
634 depends on MMU && CPU_V7
635 help
636 Say Y if you have an ARMv7 processor supporting the LPAE page table
637 format and you would like to access memory beyond the 4GB limit.
639 config ARCH_PHYS_ADDR_T_64BIT
640 def_bool ARM_LPAE
642 config ARCH_DMA_ADDR_T_64BIT
643 def_bool ARM_LPAE
645 config ARM_THUMB
646 bool "Support Thumb user binaries"
647 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON
648 default y
649 help
650 Say Y if you want to include kernel support for running user space
651 Thumb binaries.
653 The Thumb instruction set is a compressed form of the standard ARM
654 instruction set resulting in smaller binaries at the expense of
655 slightly less efficient code.
657 If you don't know what this all is, saying Y is a safe choice.
659 config ARM_THUMBEE
660 bool "Enable ThumbEE CPU extension"
661 depends on CPU_V7
662 help
663 Say Y here if you have a CPU with the ThumbEE extension and code to
664 make use of it. Say N for code that can run on CPUs without ThumbEE.
666 config SWP_EMULATE
667 bool "Emulate SWP/SWPB instructions"
668 depends on !CPU_USE_DOMAINS && CPU_V7
669 select HAVE_PROC_CPU if PROC_FS
670 default y if SMP
671 help
672 ARMv6 architecture deprecates use of the SWP/SWPB instructions.
673 ARMv7 multiprocessing extensions introduce the ability to disable
674 these instructions, triggering an undefined instruction exception
675 when executed. Say Y here to enable software emulation of these
676 instructions for userspace (not kernel) using LDREX/STREX.
677 Also creates /proc/cpu/swp_emulation for statistics.
679 In some older versions of glibc [<=2.8] SWP is used during futex
680 trylock() operations with the assumption that the code will not
681 be preempted. This invalid assumption may be more likely to fail
682 with SWP emulation enabled, leading to deadlock of the user
683 application.
685 NOTE: when accessing uncached shared regions, LDREX/STREX rely
686 on an external transaction monitoring block called a global
687 monitor to maintain update atomicity. If your system does not
688 implement a global monitor, this option can cause programs that
689 perform SWP operations to uncached memory to deadlock.
691 If unsure, say Y.
693 config CPU_BIG_ENDIAN
694 bool "Build big-endian kernel"
695 depends on ARCH_SUPPORTS_BIG_ENDIAN
696 help
697 Say Y if you plan on running a kernel in big-endian mode.
698 Note that your board must be properly built and your board
699 port must properly enable any big-endian related features
700 of your chipset/board/processor.
702 config CPU_ENDIAN_BE8
703 bool
704 depends on CPU_BIG_ENDIAN
705 default CPU_V6 || CPU_V6K || CPU_V7
706 help
707 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
709 config CPU_ENDIAN_BE32
710 bool
711 depends on CPU_BIG_ENDIAN
712 default !CPU_ENDIAN_BE8
713 help
714 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
716 config CPU_HIGH_VECTOR
717 depends on !MMU && CPU_CP15 && !CPU_ARM740T
718 bool "Select the High exception vector"
719 help
720 Say Y here to select high exception vector(0xFFFF0000~).
721 The exception vector can be vary depending on the platform
722 design in nommu mode. If your platform needs to select
723 high exception vector, say Y.
724 Otherwise or if you are unsure, say N, and the low exception
725 vector (0x00000000~) will be used.
727 config CPU_ICACHE_DISABLE
728 bool "Disable I-Cache (I-bit)"
729 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
730 help
731 Say Y here to disable the processor instruction cache. Unless
732 you have a reason not to or are unsure, say N.
734 config CPU_DCACHE_DISABLE
735 bool "Disable D-Cache (C-bit)"
736 depends on CPU_CP15
737 help
738 Say Y here to disable the processor data cache. Unless
739 you have a reason not to or are unsure, say N.
741 config CPU_DCACHE_SIZE
742 hex
743 depends on CPU_ARM740T || CPU_ARM946E
744 default 0x00001000 if CPU_ARM740T
745 default 0x00002000 # default size for ARM946E-S
746 help
747 Some cores are synthesizable to have various sized cache. For
748 ARM946E-S case, it can vary from 0KB to 1MB.
749 To support such cache operations, it is efficient to know the size
750 before compile time.
751 If your SoC is configured to have a different size, define the value
752 here with proper conditions.
754 config CPU_DCACHE_WRITETHROUGH
755 bool "Force write through D-cache"
756 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
757 default y if CPU_ARM925T
758 help
759 Say Y here to use the data cache in writethrough mode. Unless you
760 specifically require this or are unsure, say N.
762 config CPU_CACHE_ROUND_ROBIN
763 bool "Round robin I and D cache replacement algorithm"
764 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
765 help
766 Say Y here to use the predictable round-robin cache replacement
767 policy. Unless you specifically require this or are unsure, say N.
769 config CPU_BPREDICT_DISABLE
770 bool "Disable branch prediction"
771 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
772 help
773 Say Y here to disable branch prediction. If unsure, say N.
775 config TLS_REG_EMUL
776 bool
777 help
778 An SMP system using a pre-ARMv6 processor (there are apparently
779 a few prototypes like that in existence) and therefore access to
780 that required register must be emulated.
782 config NEEDS_SYSCALL_FOR_CMPXCHG
783 bool
784 help
785 SMP on a pre-ARMv6 processor? Well OK then.
786 Forget about fast user space cmpxchg support.
787 It is just not possible.
789 config DMA_CACHE_RWFO
790 bool "Enable read/write for ownership DMA cache maintenance"
791 depends on CPU_V6K && SMP
792 default y
793 help
794 The Snoop Control Unit on ARM11MPCore does not detect the
795 cache maintenance operations and the dma_{map,unmap}_area()
796 functions may leave stale cache entries on other CPUs. By
797 enabling this option, Read or Write For Ownership in the ARMv6
798 DMA cache maintenance functions is performed. These LDR/STR
799 instructions change the cache line state to shared or modified
800 so that the cache operation has the desired effect.
802 Note that the workaround is only valid on processors that do
803 not perform speculative loads into the D-cache. For such
804 processors, if cache maintenance operations are not broadcast
805 in hardware, other workarounds are needed (e.g. cache
806 maintenance broadcasting in software via FIQ).
808 config OUTER_CACHE
809 bool
811 config OUTER_CACHE_SYNC
812 bool
813 help
814 The outer cache has a outer_cache_fns.sync function pointer
815 that can be used to drain the write buffer of the outer cache.
817 config CACHE_FEROCEON_L2
818 bool "Enable the Feroceon L2 cache controller"
819 depends on ARCH_KIRKWOOD || ARCH_MV78XX0
820 default y
821 select OUTER_CACHE
822 help
823 This option enables the Feroceon L2 cache controller.
825 config CACHE_FEROCEON_L2_WRITETHROUGH
826 bool "Force Feroceon L2 cache write through"
827 depends on CACHE_FEROCEON_L2
828 help
829 Say Y here to use the Feroceon L2 cache in writethrough mode.
830 Unless you specifically require this, say N for writeback mode.
832 config CACHE_L2X0
833 bool "Enable the L2x0 outer cache controller"
834 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
835 REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
836 ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
837 ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \
838 ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX
839 default y
840 select OUTER_CACHE
841 select OUTER_CACHE_SYNC
842 help
843 This option enables the L2x0 PrimeCell.
845 config CACHE_PL310
846 bool
847 depends on CACHE_L2X0
848 default y if CPU_V7 && !(CPU_V6 || CPU_V6K)
849 help
850 This option enables optimisations for the PL310 cache
851 controller.
853 config CACHE_TAUROS2
854 bool "Enable the Tauros2 L2 cache controller"
855 depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
856 default y
857 select OUTER_CACHE
858 help
859 This option enables the Tauros2 L2 cache controller (as
860 found on PJ1/PJ4).
862 config CACHE_XSC3L2
863 bool "Enable the L2 cache on XScale3"
864 depends on CPU_XSC3
865 default y
866 select OUTER_CACHE
867 help
868 This option enables the L2 cache on XScale3.
870 config ARM_L1_CACHE_SHIFT_6
871 bool
872 help
873 Setting ARM L1 cache line size to 64 Bytes.
875 config ARM_L1_CACHE_SHIFT
876 int
877 default 6 if ARM_L1_CACHE_SHIFT_6
878 default 5
880 config ARM_DMA_MEM_BUFFERABLE
881 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
882 depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
883 MACH_REALVIEW_PB11MP)
884 default y if CPU_V6 || CPU_V6K || CPU_V7
885 help
886 Historically, the kernel has used strongly ordered mappings to
887 provide DMA coherent memory. With the advent of ARMv7, mapping
888 memory with differing types results in unpredictable behaviour,
889 so on these CPUs, this option is forced on.
891 Multiple mappings with differing attributes is also unpredictable
892 on ARMv6 CPUs, but since they do not have aggressive speculative
893 prefetch, no harm appears to occur.
895 However, drivers may be missing the necessary barriers for ARMv6,
896 and therefore turning this on may result in unpredictable driver
897 behaviour. Therefore, we offer this as an option.
899 You are recommended say 'Y' here and debug any affected drivers.
901 config ARCH_HAS_BARRIERS
902 bool
903 help
904 This option allows the use of custom mandatory barriers
905 included via the mach/barriers.h file.