2 * linux/arch/arm/mm/proc-arm720.S: MMU functions for ARM720
4 * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
5 * Rob Scott (rscott@mtrob.fdns.net)
6 * Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd.
7 * hacked for non-paged-MM by Hyok S. Choi, 2004.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * These are the low level assembler for performing cache and TLB
25 * functions on the ARM720T. The ARM720T has a writethrough IDC
26 * cache, so we don't need to clean it.
29 * 05-09-2000 SJH Created by moving 720 specific functions
30 * out of 'proc-arm6,7.S' per RMK discussion
31 * 07-25-2000 SJH Added idle function.
32 * 08-25-2000 DBS Updated for integration of ARM Ltd version.
33 * 04-20-2004 HSC modified for non-paged memory management mode.
35 #include <linux/linkage.h>
36 #include <linux/init.h>
37 #include <asm/assembler.h>
38 #include <asm/asm-offsets.h>
39 #include <asm/hwcap.h>
40 #include <asm/pgtable-hwdef.h>
41 #include <asm/pgtable.h>
42 #include <asm/ptrace.h>
44 #include "proc-macros.S"
47 * Function: arm720_proc_init (void)
48 * : arm720_proc_fin (void)
50 * Notes : This processor does not require these
52 ENTRY(cpu_arm720_dcache_clean_area)
53 ENTRY(cpu_arm720_proc_init)
56 ENTRY(cpu_arm720_proc_fin)
57 mrc p15, 0, r0, c1, c0, 0
58 bic r0, r0, #0x1000 @ ...i............
59 bic r0, r0, #0x000e @ ............wca.
60 mcr p15, 0, r0, c1, c0, 0 @ disable caches
64 * Function: arm720_proc_do_idle(void)
65 * Params : r0 = unused
66 * Purpose : put the processor in proper idle mode
68 ENTRY(cpu_arm720_do_idle)
72 * Function: arm720_switch_mm(unsigned long pgd_phys)
73 * Params : pgd_phys Physical address of page table
74 * Purpose : Perform a task switch, saving the old process' state and restoring
77 ENTRY(cpu_arm720_switch_mm)
80 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
81 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
82 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
87 * Function: arm720_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
88 * Params : r0 = Address to set
90 * Purpose : Set a PTE and flush it out of any WB cache
93 ENTRY(cpu_arm720_set_pte_ext)
95 armv3_set_pte_ext wc_disable=0
100 * Function: arm720_reset
101 * Params : r0 = address to jump to
102 * Notes : This sets up everything for a reset
104 ENTRY(cpu_arm720_reset)
106 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
108 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
110 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
111 bic ip, ip, #0x000f @ ............wcam
112 bic ip, ip, #0x2100 @ ..v....s........
113 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
118 .type __arm710_setup, #function
121 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
123 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
125 mrc p15, 0, r0, c1, c0 @ get control register
126 ldr r5, arm710_cr1_clear
128 ldr r5, arm710_cr1_set
130 mov pc, lr @ __ret (head.S)
131 .size __arm710_setup, . - __arm710_setup
135 * .RVI ZFRS BLDP WCAM
136 * .... 0001 ..11 1101
139 .type arm710_cr1_clear, #object
140 .type arm710_cr1_set, #object
146 .type __arm720_setup, #function
149 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
151 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
155 mrc p15, 0, r0, c1, c0 @ get control register
158 mov pc, lr @ __ret (head.S)
159 .size __arm720_setup, . - __arm720_setup
163 * .RVI ZFRS BLDP WCAM
164 * ..1. 1001 ..11 1101
167 .type arm720_crval, #object
169 crval clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130
172 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
173 define_processor_functions arm720, dabort=v4t_late_abort, pabort=legacy_pabort
177 string cpu_arch_name, "armv4t"
178 string cpu_elf_name, "v4"
179 string cpu_arm710_name, "ARM710T"
180 string cpu_arm720_name, "ARM720T"
185 * See <asm/procinfo.h> for a definition of this structure.
188 .section ".proc.info.init", #alloc, #execinstr
190 .macro arm720_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cpu_flush:req
191 .type __\name\()_proc_info,#object
192 __\name\()_proc_info:
195 .long PMD_TYPE_SECT | \
196 PMD_SECT_BUFFERABLE | \
197 PMD_SECT_CACHEABLE | \
199 PMD_SECT_AP_WRITE | \
201 .long PMD_TYPE_SECT | \
203 PMD_SECT_AP_WRITE | \
205 b \cpu_flush @ cpu_flush
206 .long cpu_arch_name @ arch_name
207 .long cpu_elf_name @ elf_name
208 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB @ elf_hwcap
210 .long arm720_processor_functions
214 .size __\name\()_proc_info, . - __\name\()_proc_info
217 arm720_proc_info arm710, 0x41807100, 0xffffff00, cpu_arm710_name, __arm710_setup
218 arm720_proc_info arm720, 0x41807200, 0xffffff00, cpu_arm720_name, __arm720_setup