arch/arm/plat-s3c24xx/s3c2412-iotiming.c

   1 /* linux/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
   2  *
   3  * Copyright (c) 2006-2008 Simtec Electronics
   4  *      http://armlinux.simtec.co.uk/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * S3C2412/S3C2443 (PL093 based) IO timing support
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12 */
  13
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/ioport.h>
  18 #include <linux/cpufreq.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/delay.h>
  22 #include <linux/clk.h>
  23 #include <linux/err.h>
  24 #include <linux/slab.h>
  25
  26 #include <linux/amba/pl093.h>
  27
  28 #include <asm/mach/arch.h>
  29 #include <asm/mach/map.h>
  30
  31 #include <mach/regs-s3c2412-mem.h>
  32
  33 #include <plat/cpu.h>
  34 #include <plat/cpu-freq-core.h>
  35 #include <plat/clock.h>
  36
  37 #define print_ns(x) ((x) / 10), ((x) % 10)
  38
  39 /**
  40  * s3c2412_print_timing - print timing infromation via printk.
  41  * @pfx: The prefix to print each line with.
  42  * @iot: The IO timing information
  43  */
  44 static void s3c2412_print_timing(const char *pfx, struct s3c_iotimings *iot)
  45 {
  46         struct s3c2412_iobank_timing *bt;
  47         unsigned int bank;
  48
  49         for (bank = 0; bank < MAX_BANKS; bank++) {
  50                 bt = iot->bank[bank].io_2412;
  51                 if (!bt)
  52                         continue;
  53
  54                 printk(KERN_DEBUG "%s: %d: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d"
  55                        "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", pfx, bank,
  56                        print_ns(bt->idcy),
  57                        print_ns(bt->wstrd),
  58                        print_ns(bt->wstwr),
  59                        print_ns(bt->wstoen),
  60                        print_ns(bt->wstwen),
  61                        print_ns(bt->wstbrd));
  62         }
  63 }
  64
  65 /**
  66  * to_div - turn a cycle length into a divisor setting.
  67  * @cyc_tns: The cycle time in 10ths of nanoseconds.
  68  * @clk_tns: The clock period in 10ths of nanoseconds.
  69  */
  70 static inline unsigned int to_div(unsigned int cyc_tns, unsigned int clk_tns)
  71 {
  72         return cyc_tns ? DIV_ROUND_UP(cyc_tns, clk_tns) : 0;
  73 }
  74
  75 /**
  76  * calc_timing - calculate timing divisor value and check in range.
  77  * @hwtm: The hardware timing in 10ths of nanoseconds.
  78  * @clk_tns: The clock period in 10ths of nanoseconds.
  79  * @err: Pointer to err variable to update in event of failure.
  80  */
  81 static unsigned int calc_timing(unsigned int hwtm, unsigned int clk_tns,
  82                                 unsigned int *err)
  83 {
  84         unsigned int ret = to_div(hwtm, clk_tns);
  85
  86         if (ret > 0xf)
  87                 *err = -EINVAL;
  88
  89         return ret;
  90 }
  91
  92 /**
  93  * s3c2412_calc_bank - calculate the bank divisor settings.
  94  * @cfg: The current frequency configuration.
  95  * @bt: The bank timing.
  96  */
  97 static int s3c2412_calc_bank(struct s3c_cpufreq_config *cfg,
  98                              struct s3c2412_iobank_timing *bt)
  99 {
 100         unsigned int hclk = cfg->freq.hclk_tns;
 101         int err = 0;
 102
 103         bt->smbidcyr = calc_timing(bt->idcy, hclk, &err);
 104         bt->smbwstrd = calc_timing(bt->wstrd, hclk, &err);
 105         bt->smbwstwr = calc_timing(bt->wstwr, hclk, &err);
 106         bt->smbwstoen = calc_timing(bt->wstoen, hclk, &err);
 107         bt->smbwstwen = calc_timing(bt->wstwen, hclk, &err);
 108         bt->smbwstbrd = calc_timing(bt->wstbrd, hclk, &err);
 109
 110         return err;
 111 }
 112
 113 /**
 114  * s3c2412_iotiming_debugfs - debugfs show io bank timing information
 115  * @seq: The seq_file to write output to using seq_printf().
 116  * @cfg: The current configuration.
 117  * @iob: The IO bank information to decode.
 118 */
 119 void s3c2412_iotiming_debugfs(struct seq_file *seq,
 120                               struct s3c_cpufreq_config *cfg,
 121                               union s3c_iobank *iob)
 122 {
 123         struct s3c2412_iobank_timing *bt = iob->io_2412;
 124
 125         seq_printf(seq,
 126                    "\tRead: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d"
 127                    "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n",
 128                    print_ns(bt->idcy),
 129                    print_ns(bt->wstrd),
 130                    print_ns(bt->wstwr),
 131                    print_ns(bt->wstoen),
 132                    print_ns(bt->wstwen),
 133                    print_ns(bt->wstbrd));
 134 }
 135
 136 /**
 137  * s3c2412_iotiming_calc - calculate all the bank divisor settings.
 138  * @cfg: The current frequency configuration.
 139  * @iot: The bank timing information.
 140  *
 141  * Calculate the timing information for all the banks that are
 142  * configured as IO, using s3c2412_calc_bank().
 143  */
 144 int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg,
 145                           struct s3c_iotimings *iot)
 146 {
 147         struct s3c2412_iobank_timing *bt;
 148         int bank;
 149         int ret;
 150
 151         for (bank = 0; bank < MAX_BANKS; bank++) {
 152                 bt = iot->bank[bank].io_2412;
 153                 if (!bt)
 154                         continue;
 155
 156                 ret = s3c2412_calc_bank(cfg, bt);
 157                 if (ret) {
 158                         printk(KERN_ERR "%s: cannot calculate bank %d io\n",
 159                                __func__, bank);
 160                         goto err;
 161                 }
 162         }
 163
 164         return 0;
 165  err:
 166         return ret;
 167 }
 168
 169 /**
 170  * s3c2412_iotiming_set - set the timing information
 171  * @cfg: The current frequency configuration.
 172  * @iot: The bank timing information.
 173  *
 174  * Set the IO bank information from the details calculated earlier from
 175  * calling s3c2412_iotiming_calc().
 176  */
 177 void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
 178                           struct s3c_iotimings *iot)
 179 {
 180         struct s3c2412_iobank_timing *bt;
 181         void __iomem *regs;
 182         int bank;
 183
 184         /* set the io timings from the specifier */
 185
 186         for (bank = 0; bank < MAX_BANKS; bank++) {
 187                 bt = iot->bank[bank].io_2412;
 188                 if (!bt)
 189                         continue;
 190
 191                 regs = S3C2412_SSMC_BANK(bank);
 192
 193                 __raw_writel(bt->smbidcyr, regs + SMBIDCYR);
 194                 __raw_writel(bt->smbwstrd, regs + SMBWSTRDR);
 195                 __raw_writel(bt->smbwstwr, regs + SMBWSTWRR);
 196                 __raw_writel(bt->smbwstoen, regs + SMBWSTOENR);
 197                 __raw_writel(bt->smbwstwen, regs + SMBWSTWENR);
 198                 __raw_writel(bt->smbwstbrd, regs + SMBWSTBRDR);
 199         }
 200 }
 201
 202 static inline unsigned int s3c2412_decode_timing(unsigned int clock, u32 reg)
 203 {
 204         return (reg & 0xf) * clock;
 205 }
 206
 207 static void s3c2412_iotiming_getbank(struct s3c_cpufreq_config *cfg,
 208                                      struct s3c2412_iobank_timing *bt,
 209                                      unsigned int bank)
 210 {
 211         unsigned long clk = cfg->freq.hclk_tns;  /* ssmc clock??? */
 212         void __iomem *regs = S3C2412_SSMC_BANK(bank);
 213
 214         bt->idcy = s3c2412_decode_timing(clk, __raw_readl(regs + SMBIDCYR));
 215         bt->wstrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTRDR));
 216         bt->wstoen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTOENR));
 217         bt->wstwen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTWENR));
 218         bt->wstbrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTBRDR));
 219 }
 220
 221 /**
 222  * bank_is_io - return true if bank is (possibly) IO.
 223  * @bank: The bank number.
 224  * @bankcfg: The value of S3C2412_EBI_BANKCFG.
 225  */
 226 static inline bool bank_is_io(unsigned int bank, u32 bankcfg)
 227 {
 228         if (bank < 2)
 229                 return true;
 230
 231         return !(bankcfg & (1 << bank));
 232 }
 233
 234 int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
 235                          struct s3c_iotimings *timings)
 236 {
 237         struct s3c2412_iobank_timing *bt;
 238         u32 bankcfg = __raw_readl(S3C2412_EBI_BANKCFG);
 239         unsigned int bank;
 240
 241         /* look through all banks to see what is currently set. */
 242
 243         for (bank = 0; bank < MAX_BANKS; bank++) {
 244                 if (!bank_is_io(bank, bankcfg))
 245                         continue;
 246
 247                 bt = kzalloc(sizeof(struct s3c2412_iobank_timing), GFP_KERNEL);
 248                 if (!bt) {
 249                         printk(KERN_ERR "%s: no memory for bank\n", __func__);
 250                         return -ENOMEM;
 251                 }
 252
 253                 timings->bank[bank].io_2412 = bt;
 254                 s3c2412_iotiming_getbank(cfg, bt, bank);
 255         }
 256
 257         s3c2412_print_timing("get", timings);
 258         return 0;
 259 }
 260
 261 /* this is in here as it is so small, it doesn't currently warrant a file
 262  * to itself. We expect that any s3c24xx needing this is going to also
 263  * need the iotiming support.
 264  */
 265 void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
 266 {
 267         struct s3c_cpufreq_board *board = cfg->board;
 268         u32 refresh;
 269
 270         WARN_ON(board == NULL);
 271
 272         /* Reduce both the refresh time (in ns) and the frequency (in MHz)
 273          * down to ensure that we do not overflow 32 bit numbers.
 274          *
 275          * This should work for HCLK up to 133MHz and refresh period up
 276          * to 30usec.
 277          */
 278
 279         refresh = (cfg->freq.hclk / 100) * (board->refresh / 10);
 280         refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale  */
 281         refresh &= ((1 << 16) - 1);
 282
 283         s3c_freq_dbg("%s: refresh value %u\n", __func__, (unsigned int)refresh);
 284
 285         __raw_writel(refresh, S3C2412_REFRESH);
 286 }