2 * P1020 RDB Device Tree Source
4 * Copyright 2009-2011 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
12 /include/ "p1020si.dtsi"
15 model = "fsl,P1020RDB";
16 compatible = "fsl,P1020RDB";
29 device_type = "memory";
34 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
35 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
36 0x1 0x0 0x0 0xffa00000 0x00040000
37 0x2 0x0 0x0 0xffb00000 0x00020000>;
42 compatible = "cfi-flash";
43 reg = <0x0 0x0 0x1000000>;
48 /* This location must not be altered */
49 /* 256KB for Vitesse 7385 Switch firmware */
50 reg = <0x0 0x00040000>;
51 label = "NOR (RO) Vitesse-7385 Firmware";
56 /* 256KB for DTB Image */
57 reg = <0x00040000 0x00040000>;
58 label = "NOR (RO) DTB Image";
63 /* 3.5 MB for Linux Kernel Image */
64 reg = <0x00080000 0x00380000>;
65 label = "NOR (RO) Linux Kernel Image";
70 /* 11MB for JFFS2 based Root file System */
71 reg = <0x00400000 0x00b00000>;
72 label = "NOR (RW) JFFS2 Root File System";
76 /* This location must not be altered */
77 /* 512KB for u-boot Bootloader Image */
78 /* 512KB for u-boot Environment Variables */
79 reg = <0x00f00000 0x00100000>;
80 label = "NOR (RO) U-Boot Image";
88 compatible = "fsl,p1020-fcm-nand",
90 reg = <0x1 0x0 0x40000>;
93 /* This location must not be altered */
94 /* 1MB for u-boot Bootloader Image */
95 reg = <0x0 0x00100000>;
96 label = "NAND (RO) U-Boot Image";
101 /* 1MB for DTB Image */
102 reg = <0x00100000 0x00100000>;
103 label = "NAND (RO) DTB Image";
108 /* 4MB for Linux Kernel Image */
109 reg = <0x00200000 0x00400000>;
110 label = "NAND (RO) Linux Kernel Image";
115 /* 4MB for Compressed Root file System Image */
116 reg = <0x00600000 0x00400000>;
117 label = "NAND (RO) Compressed RFS Image";
122 /* 7MB for JFFS2 based Root file System */
123 reg = <0x00a00000 0x00700000>;
124 label = "NAND (RW) JFFS2 Root File System";
128 /* 15MB for JFFS2 based Root file System */
129 reg = <0x01100000 0x00f00000>;
130 label = "NAND (RW) Writable User area";
135 #address-cells = <1>;
137 compatible = "vitesse-7385";
138 reg = <0x2 0x0 0x20000>;
146 compatible = "dallas,ds1339";
154 #address-cells = <1>;
156 compatible = "fsl,espi-flash";
158 linux,modalias = "fsl_m25p80";
160 spi-max-frequency = <50000000>;
164 /* 512KB for u-boot Bootloader Image */
165 reg = <0x0 0x00080000>;
166 label = "SPI (RO) U-Boot Image";
171 /* 512KB for DTB Image */
172 reg = <0x00080000 0x00080000>;
173 label = "SPI (RO) DTB Image";
178 /* 4MB for Linux Kernel Image */
179 reg = <0x00100000 0x00400000>;
180 label = "SPI (RO) Linux Kernel Image";
185 /* 4MB for Compressed RFS Image */
186 reg = <0x00500000 0x00400000>;
187 label = "SPI (RO) Compressed RFS Image";
192 /* 7MB for JFFS2 based RFS */
193 reg = <0x00900000 0x00700000>;
194 label = "SPI (RW) JFFS2 RFS";
201 phy0: ethernet-phy@0 {
202 interrupt-parent = <&mpic>;
207 phy1: ethernet-phy@1 {
208 interrupt-parent = <&mpic>;
218 device_type = "tbi-phy";
222 enet0: ethernet@b0000 {
223 fixed-link = <1 1 1000 0 0>;
224 phy-connection-type = "rgmii-id";
228 enet1: ethernet@b1000 {
229 phy-handle = <&phy0>;
230 tbi-handle = <&tbi0>;
231 phy-connection-type = "sgmii";
235 enet2: ethernet@b2000 {
236 phy-handle = <&phy1>;
237 phy-connection-type = "rgmii-id";
245 /* USB2 is shared with localbus, so it must be disabled
246 by default. We can't put 'status = "disabled";' here
247 since U-Boot doesn't clear the status property when
248 it enables USB2. OTOH, U-Boot does create a new node
249 when there isn't any. So, just comment it out.
257 pci0: pcie@ffe09000 {
258 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
259 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
260 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
263 0000 0x0 0x0 0x1 &mpic 0x4 0x1
264 0000 0x0 0x0 0x2 &mpic 0x5 0x1
265 0000 0x0 0x0 0x3 &mpic 0x6 0x1
266 0000 0x0 0x0 0x4 &mpic 0x7 0x1
269 reg = <0x0 0x0 0x0 0x0 0x0>;
271 #address-cells = <3>;
273 ranges = <0x2000000 0x0 0xa0000000
274 0x2000000 0x0 0xa0000000
283 pci1: pcie@ffe0a000 {
284 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
285 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
286 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
289 0000 0x0 0x0 0x1 &mpic 0x0 0x1
290 0000 0x0 0x0 0x2 &mpic 0x1 0x1
291 0000 0x0 0x0 0x3 &mpic 0x2 0x1
292 0000 0x0 0x0 0x4 &mpic 0x3 0x1
295 reg = <0x0 0x0 0x0 0x0 0x0>;
297 #address-cells = <3>;
299 ranges = <0x2000000 0x0 0x80000000
300 0x2000000 0x0 0x80000000