arch/powerpc/include/asm/lppaca.h

   1 /*
   2  * lppaca.h
   3  * Copyright (C) 2001  Mike Corrigan IBM Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19 #ifndef _ASM_POWERPC_LPPACA_H
  20 #define _ASM_POWERPC_LPPACA_H
  21 #ifdef __KERNEL__
  22
  23 /* These definitions relate to hypervisors that only exist when using
  24  * a server type processor
  25  */
  26 #ifdef CONFIG_PPC_BOOK3S
  27
  28 //=============================================================================
  29 //
  30 //      This control block contains the data that is shared between the
  31 //      hypervisor (PLIC) and the OS.
  32 //
  33 //
  34 //----------------------------------------------------------------------------
  35 #include <linux/cache.h>
  36 #include <linux/threads.h>
  37 #include <asm/types.h>
  38 #include <asm/mmu.h>
  39
  40 /*
  41  * We only have to have statically allocated lppaca structs on
  42  * legacy iSeries, which supports at most 64 cpus.
  43  */
  44 #ifdef CONFIG_PPC_ISERIES
  45 #if NR_CPUS < 64
  46 #define NR_LPPACAS      NR_CPUS
  47 #else
  48 #define NR_LPPACAS      64
  49 #endif
  50 #else /* not iSeries */
  51 #define NR_LPPACAS      1
  52 #endif
  53
  54
  55 /* The Hypervisor barfs if the lppaca crosses a page boundary.  A 1k
  56  * alignment is sufficient to prevent this */
  57 struct lppaca {
  58 //=============================================================================
  59 // CACHE_LINE_1 0x0000 - 0x007F Contains read-only data
  60 // NOTE: The xDynXyz fields are fields that will be dynamically changed by
  61 // PLIC when preparing to bring a processor online or when dispatching a
  62 // virtual processor!
  63 //=============================================================================
  64         u32     desc;                   // Eye catcher 0xD397D781       x00-x03
  65         u16     size;                   // Size of this struct          x04-x05
  66         u16     reserved1;              // Reserved                     x06-x07
  67         u16     reserved2:14;           // Reserved                     x08-x09
  68         u8      shared_proc:1;          // Shared processor indicator   ...
  69         u8      secondary_thread:1;     // Secondary thread indicator   ...
  70         volatile u8 dyn_proc_status:8;  // Dynamic Status of this proc  x0A-x0A
  71         u8      secondary_thread_count; // Secondary thread count       x0B-x0B
  72         volatile u16 dyn_hv_phys_proc_index;// Dynamic HV Physical Proc Index0C-x0D
  73         volatile u16 dyn_hv_log_proc_index;// Dynamic HV Logical Proc Indexx0E-x0F
  74         u32     decr_val;               // Value for Decr programming   x10-x13
  75         u32     pmc_val;                // Value for PMC regs           x14-x17
  76         volatile u32 dyn_hw_node_id;    // Dynamic Hardware Node id     x18-x1B
  77         volatile u32 dyn_hw_proc_id;    // Dynamic Hardware Proc Id     x1C-x1F
  78         volatile u32 dyn_pir;           // Dynamic ProcIdReg value      x20-x23
  79         u32     dsei_data;              // DSEI data                    x24-x27
  80         u64     sprg3;                  // SPRG3 value                  x28-x2F
  81         u8      reserved3[40];          // Reserved                     x30-x57
  82         volatile u8 vphn_assoc_counts[8]; // Virtual processor home node
  83                                         // associativity change counters x58-x5F
  84         u8      reserved4[32];          // Reserved                     x60-x7F
  85
  86 //=============================================================================
  87 // CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data
  88 //=============================================================================
  89         // This Dword contains a byte for each type of interrupt that can occur.
  90         // The IPI is a count while the others are just a binary 1 or 0.
  91         union {
  92                 u64     any_int;
  93                 struct {
  94                         u16     reserved;       // Reserved - cleared by #mpasmbl
  95                         u8      xirr_int;       // Indicates xXirrValue is valid or Immed IO
  96                         u8      ipi_cnt;        // IPI Count
  97                         u8      decr_int;       // DECR interrupt occurred
  98                         u8      pdc_int;        // PDC interrupt occurred
  99                         u8      quantum_int;    // Interrupt quantum reached
 100                         u8      old_plic_deferred_ext_int;      // Old PLIC has a deferred XIRR pending
 101                 } fields;
 102         } int_dword;
 103
 104         // Whenever any fields in this Dword are set then PLIC will defer the
 105         // processing of external interrupts.  Note that PLIC will store the
 106         // XIRR directly into the xXirrValue field so that another XIRR will
 107         // not be presented until this one clears.  The layout of the low
 108         // 4-bytes of this Dword is up to SLIC - PLIC just checks whether the
 109         // entire Dword is zero or not.  A non-zero value in the low order
 110         // 2-bytes will result in SLIC being granted the highest thread
 111         // priority upon return.  A 0 will return to SLIC as medium priority.
 112         u64     plic_defer_ints_area;   // Entire Dword
 113
 114         // Used to pass the real SRR0/1 from PLIC to SLIC as well as to
 115         // pass the target SRR0/1 from SLIC to PLIC on a SetAsrAndRfid.
 116         u64     saved_srr0;             // Saved SRR0                   x10-x17
 117         u64     saved_srr1;             // Saved SRR1                   x18-x1F
 118
 119         // Used to pass parms from the OS to PLIC for SetAsrAndRfid
 120         u64     saved_gpr3;             // Saved GPR3                   x20-x27
 121         u64     saved_gpr4;             // Saved GPR4                   x28-x2F
 122         union {
 123                 u64     saved_gpr5;     /* Saved GPR5               x30-x37 */
 124                 struct {
 125                         u8      cede_latency_hint;  /*                  x30 */
 126                         u8      reserved[7];        /*              x31-x36 */
 127                 } fields;
 128         } gpr5_dword;
 129
 130
 131         u8      dtl_enable_mask;        // Dispatch Trace Log mask      x38-x38
 132         u8      donate_dedicated_cpu;   // Donate dedicated CPU cycles  x39-x39
 133         u8      fpregs_in_use;          // FP regs in use               x3A-x3A
 134         u8      pmcregs_in_use;         // PMC regs in use              x3B-x3B
 135         volatile u32 saved_decr;        // Saved Decr Value             x3C-x3F
 136         volatile u64 emulated_time_base;// Emulated TB for this thread  x40-x47
 137         volatile u64 cur_plic_latency;  // Unaccounted PLIC latency     x48-x4F
 138         u64     tot_plic_latency;       // Accumulated PLIC latency     x50-x57
 139         u64     wait_state_cycles;      // Wait cycles for this proc    x58-x5F
 140         u64     end_of_quantum;         // TB at end of quantum         x60-x67
 141         u64     pdc_saved_sprg1;        // Saved SPRG1 for PMC int      x68-x6F
 142         u64     pdc_saved_srr0;         // Saved SRR0 for PMC int       x70-x77
 143         volatile u32 virtual_decr;      // Virtual DECR for shared procsx78-x7B
 144         u16     slb_count;              // # of SLBs to maintain        x7C-x7D
 145         u8      idle;                   // Indicate OS is idle          x7E
 146         u8      vmxregs_in_use;         // VMX registers in use         x7F
 147
 148
 149 //=============================================================================
 150 // CACHE_LINE_3 0x0100 - 0x017F: This line is shared with other processors
 151 //=============================================================================
 152         // This is the yield_count.  An "odd" value (low bit on) means that
 153         // the processor is yielded (either because of an OS yield or a PLIC
 154         // preempt).  An even value implies that the processor is currently
 155         // executing.
 156         // NOTE: This value will ALWAYS be zero for dedicated processors and
 157         // will NEVER be zero for shared processors (ie, initialized to a 1).
 158         volatile u32 yield_count;       // PLIC increments each dispatchx00-x03
 159         volatile u32 dispersion_count;  // dispatch changed phys cpu    x04-x07
 160         volatile u64 cmo_faults;        // CMO page fault count         x08-x0F
 161         volatile u64 cmo_fault_time;    // CMO page fault time          x10-x17
 162         u8      reserved7[104];         // Reserved                     x18-x7F
 163
 164 //=============================================================================
 165 // CACHE_LINE_4-5 0x0180 - 0x027F Contains PMC interrupt data
 166 //=============================================================================
 167         u32     page_ins;               // CMO Hint - # page ins by OS  x00-x03
 168         u8      reserved8[148];         // Reserved                     x04-x97
 169         volatile u64 dtl_idx;           // Dispatch Trace Log head idx  x98-x9F
 170         u8      reserved9[96];          // Reserved                     xA0-xFF
 171 } __attribute__((__aligned__(0x400)));
 172
 173 extern struct lppaca lppaca[];
 174
 175 #define lppaca_of(cpu)  (*paca[cpu].lppaca_ptr)
 176
 177 /*
 178  * SLB shadow buffer structure as defined in the PAPR.  The save_area
 179  * contains adjacent ESID and VSID pairs for each shadowed SLB.  The
 180  * ESID is stored in the lower 64bits, then the VSID.
 181  */
 182 struct slb_shadow {
 183         u32     persistent;             // Number of persistent SLBs    x00-x03
 184         u32     buffer_length;          // Total shadow buffer length   x04-x07
 185         u64     reserved;               // Alignment                    x08-x0f
 186         struct  {
 187                 u64     esid;
 188                 u64     vsid;
 189         } save_area[SLB_NUM_BOLTED];    //                              x10-x40
 190 } ____cacheline_aligned;
 191
 192 extern struct slb_shadow slb_shadow[];
 193
 194 /*
 195  * Layout of entries in the hypervisor's dispatch trace log buffer.
 196  */
 197 struct dtl_entry {
 198         u8      dispatch_reason;
 199         u8      preempt_reason;
 200         u16     processor_id;
 201         u32     enqueue_to_dispatch_time;
 202         u32     ready_to_enqueue_time;
 203         u32     waiting_to_ready_time;
 204         u64     timebase;
 205         u64     fault_addr;
 206         u64     srr0;
 207         u64     srr1;
 208 };
 209
 210 #define DISPATCH_LOG_BYTES      4096    /* bytes per cpu */
 211 #define N_DISPATCH_LOG          (DISPATCH_LOG_BYTES / sizeof(struct dtl_entry))
 212
 213 extern struct kmem_cache *dtl_cache;
 214
 215 /*
 216  * When CONFIG_VIRT_CPU_ACCOUNTING = y, the cpu accounting code controls
 217  * reading from the dispatch trace log.  If other code wants to consume
 218  * DTL entries, it can set this pointer to a function that will get
 219  * called once for each DTL entry that gets processed.
 220  */
 221 extern void (*dtl_consumer)(struct dtl_entry *entry, u64 index);
 222
 223 #endif /* CONFIG_PPC_BOOK3S */
 224 #endif /* __KERNEL__ */
 225 #endif /* _ASM_POWERPC_LPPACA_H */