arch/powerpc/include/asm/system.h

   1 /*
   2  * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
   3  */
   4 #ifndef _ASM_POWERPC_SYSTEM_H
   5 #define _ASM_POWERPC_SYSTEM_H
   6
   7 #include <linux/kernel.h>
   8 #include <linux/irqflags.h>
   9
  10 #include <asm/hw_irq.h>
  11
  12 /*
  13  * Memory barrier.
  14  * The sync instruction guarantees that all memory accesses initiated
  15  * by this processor have been performed (with respect to all other
  16  * mechanisms that access memory).  The eieio instruction is a barrier
  17  * providing an ordering (separately) for (a) cacheable stores and (b)
  18  * loads and stores to non-cacheable memory (e.g. I/O devices).
  19  *
  20  * mb() prevents loads and stores being reordered across this point.
  21  * rmb() prevents loads being reordered across this point.
  22  * wmb() prevents stores being reordered across this point.
  23  * read_barrier_depends() prevents data-dependent loads being reordered
  24  *      across this point (nop on PPC).
  25  *
  26  * *mb() variants without smp_ prefix must order all types of memory
  27  * operations with one another. sync is the only instruction sufficient
  28  * to do this.
  29  *
  30  * For the smp_ barriers, ordering is for cacheable memory operations
  31  * only. We have to use the sync instruction for smp_mb(), since lwsync
  32  * doesn't order loads with respect to previous stores.  Lwsync can be
  33  * used for smp_rmb() and smp_wmb().
  34  *
  35  * However, on CPUs that don't support lwsync, lwsync actually maps to a
  36  * heavy-weight sync, so smp_wmb() can be a lighter-weight eieio.
  37  */
  38 #define mb()   __asm__ __volatile__ ("sync" : : : "memory")
  39 #define rmb()  __asm__ __volatile__ ("sync" : : : "memory")
  40 #define wmb()  __asm__ __volatile__ ("sync" : : : "memory")
  41 #define read_barrier_depends()  do { } while(0)
  42
  43 #define set_mb(var, value)      do { var = value; mb(); } while (0)
  44
  45 #ifdef __KERNEL__
  46 #define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */
  47 #ifdef CONFIG_SMP
  48
  49 #ifdef __SUBARCH_HAS_LWSYNC
  50 #    define SMPWMB      LWSYNC
  51 #else
  52 #    define SMPWMB      eieio
  53 #endif
  54
  55 #define smp_mb()        mb()
  56 #define smp_rmb()       __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory")
  57 #define smp_wmb()       __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory")
  58 #define smp_read_barrier_depends()      read_barrier_depends()
  59 #else
  60 #define smp_mb()        barrier()
  61 #define smp_rmb()       barrier()
  62 #define smp_wmb()       barrier()
  63 #define smp_read_barrier_depends()      do { } while(0)
  64 #endif /* CONFIG_SMP */
  65
  66 /*
  67  * This is a barrier which prevents following instructions from being
  68  * started until the value of the argument x is known.  For example, if
  69  * x is a variable loaded from memory, this prevents following
  70  * instructions from being executed until the load has been performed.
  71  */
  72 #define data_barrier(x) \
  73         asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
  74
  75 struct task_struct;
  76 struct pt_regs;
  77
  78 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
  79
  80 extern int (*__debugger)(struct pt_regs *regs);
  81 extern int (*__debugger_ipi)(struct pt_regs *regs);
  82 extern int (*__debugger_bpt)(struct pt_regs *regs);
  83 extern int (*__debugger_sstep)(struct pt_regs *regs);
  84 extern int (*__debugger_iabr_match)(struct pt_regs *regs);
  85 extern int (*__debugger_dabr_match)(struct pt_regs *regs);
  86 extern int (*__debugger_fault_handler)(struct pt_regs *regs);
  87
  88 #define DEBUGGER_BOILERPLATE(__NAME) \
  89 static inline int __NAME(struct pt_regs *regs) \
  90 { \
  91         if (unlikely(__ ## __NAME)) \
  92                 return __ ## __NAME(regs); \
  93         return 0; \
  94 }
  95
  96 DEBUGGER_BOILERPLATE(debugger)
  97 DEBUGGER_BOILERPLATE(debugger_ipi)
  98 DEBUGGER_BOILERPLATE(debugger_bpt)
  99 DEBUGGER_BOILERPLATE(debugger_sstep)
 100 DEBUGGER_BOILERPLATE(debugger_iabr_match)
 101 DEBUGGER_BOILERPLATE(debugger_dabr_match)
 102 DEBUGGER_BOILERPLATE(debugger_fault_handler)
 103
 104 #else
 105 static inline int debugger(struct pt_regs *regs) { return 0; }
 106 static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
 107 static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
 108 static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
 109 static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
 110 static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
 111 static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
 112 #endif
 113
 114 extern int set_dabr(unsigned long dabr);
 115 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 116 extern void do_send_trap(struct pt_regs *regs, unsigned long address,
 117                          unsigned long error_code, int signal_code, int brkpt);
 118 #else
 119 extern void do_dabr(struct pt_regs *regs, unsigned long address,
 120                     unsigned long error_code);
 121 #endif
 122 extern void print_backtrace(unsigned long *);
 123 extern void flush_instruction_cache(void);
 124 extern void hard_reset_now(void);
 125 extern void poweroff_now(void);
 126
 127 #ifdef CONFIG_6xx
 128 extern long _get_L2CR(void);
 129 extern long _get_L3CR(void);
 130 extern void _set_L2CR(unsigned long);
 131 extern void _set_L3CR(unsigned long);
 132 #else
 133 #define _get_L2CR()     0L
 134 #define _get_L3CR()     0L
 135 #define _set_L2CR(val)  do { } while(0)
 136 #define _set_L3CR(val)  do { } while(0)
 137 #endif
 138
 139 extern void via_cuda_init(void);
 140 extern void read_rtc_time(void);
 141 extern void pmac_find_display(void);
 142 extern void giveup_fpu(struct task_struct *);
 143 extern void disable_kernel_fp(void);
 144 extern void enable_kernel_fp(void);
 145 extern void flush_fp_to_thread(struct task_struct *);
 146 extern void enable_kernel_altivec(void);
 147 extern void giveup_altivec(struct task_struct *);
 148 extern void load_up_altivec(struct task_struct *);
 149 extern int emulate_altivec(struct pt_regs *);
 150 extern void __giveup_vsx(struct task_struct *);
 151 extern void giveup_vsx(struct task_struct *);
 152 extern void enable_kernel_spe(void);
 153 extern void giveup_spe(struct task_struct *);
 154 extern void load_up_spe(struct task_struct *);
 155 extern int fix_alignment(struct pt_regs *);
 156 extern void cvt_fd(float *from, double *to);
 157 extern void cvt_df(double *from, float *to);
 158
 159 #ifndef CONFIG_SMP
 160 extern void discard_lazy_cpu_state(void);
 161 #else
 162 static inline void discard_lazy_cpu_state(void)
 163 {
 164 }
 165 #endif
 166
 167 #ifdef CONFIG_ALTIVEC
 168 extern void flush_altivec_to_thread(struct task_struct *);
 169 #else
 170 static inline void flush_altivec_to_thread(struct task_struct *t)
 171 {
 172 }
 173 #endif
 174
 175 #ifdef CONFIG_VSX
 176 extern void flush_vsx_to_thread(struct task_struct *);
 177 #else
 178 static inline void flush_vsx_to_thread(struct task_struct *t)
 179 {
 180 }
 181 #endif
 182
 183 #ifdef CONFIG_SPE
 184 extern void flush_spe_to_thread(struct task_struct *);
 185 #else
 186 static inline void flush_spe_to_thread(struct task_struct *t)
 187 {
 188 }
 189 #endif
 190
 191 extern int call_rtas(const char *, int, int, unsigned long *, ...);
 192 extern void cacheable_memzero(void *p, unsigned int nb);
 193 extern void *cacheable_memcpy(void *, const void *, unsigned int);
 194 extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
 195 extern void bad_page_fault(struct pt_regs *, unsigned long, int);
 196 extern int die(const char *, struct pt_regs *, long);
 197 extern void _exception(int, struct pt_regs *, int, unsigned long);
 198 extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 199
 200 #ifdef CONFIG_BOOKE_WDT
 201 extern u32 booke_wdt_enabled;
 202 extern u32 booke_wdt_period;
 203 #endif /* CONFIG_BOOKE_WDT */
 204
 205 struct device_node;
 206 extern void note_scsi_host(struct device_node *, void *);
 207
 208 extern struct task_struct *__switch_to(struct task_struct *,
 209         struct task_struct *);
 210 #define switch_to(prev, next, last)     ((last) = __switch_to((prev), (next)))
 211
 212 struct thread_struct;
 213 extern struct task_struct *_switch(struct thread_struct *prev,
 214                                    struct thread_struct *next);
 215
 216 extern unsigned int rtas_data;
 217 extern int mem_init_done;       /* set on boot once kmalloc can be called */
 218 extern int init_bootmem_done;   /* set once bootmem is available */
 219 extern phys_addr_t memory_limit;
 220 extern unsigned long klimit;
 221 extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
 222
 223 extern int powersave_nap;       /* set if nap mode can be used in idle loop */
 224
 225 /*
 226  * Atomic exchange
 227  *
 228  * Changes the memory location '*ptr' to be val and returns
 229  * the previous value stored there.
 230  */
 231 static __always_inline unsigned long
 232 __xchg_u32(volatile void *p, unsigned long val)
 233 {
 234         unsigned long prev;
 235
 236         __asm__ __volatile__(
 237         PPC_RELEASE_BARRIER
 238 "1:     lwarx   %0,0,%2 \n"
 239         PPC405_ERR77(0,%2)
 240 "       stwcx.  %3,0,%2 \n\
 241         bne-    1b"
 242         PPC_ACQUIRE_BARRIER
 243         : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
 244         : "r" (p), "r" (val)
 245         : "cc", "memory");
 246
 247         return prev;
 248 }
 249
 250 /*
 251  * Atomic exchange
 252  *
 253  * Changes the memory location '*ptr' to be val and returns
 254  * the previous value stored there.
 255  */
 256 static __always_inline unsigned long
 257 __xchg_u32_local(volatile void *p, unsigned long val)
 258 {
 259         unsigned long prev;
 260
 261         __asm__ __volatile__(
 262 "1:     lwarx   %0,0,%2 \n"
 263         PPC405_ERR77(0,%2)
 264 "       stwcx.  %3,0,%2 \n\
 265         bne-    1b"
 266         : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
 267         : "r" (p), "r" (val)
 268         : "cc", "memory");
 269
 270         return prev;
 271 }
 272
 273 #ifdef CONFIG_PPC64
 274 static __always_inline unsigned long
 275 __xchg_u64(volatile void *p, unsigned long val)
 276 {
 277         unsigned long prev;
 278
 279         __asm__ __volatile__(
 280         PPC_RELEASE_BARRIER
 281 "1:     ldarx   %0,0,%2 \n"
 282         PPC405_ERR77(0,%2)
 283 "       stdcx.  %3,0,%2 \n\
 284         bne-    1b"
 285         PPC_ACQUIRE_BARRIER
 286         : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
 287         : "r" (p), "r" (val)
 288         : "cc", "memory");
 289
 290         return prev;
 291 }
 292
 293 static __always_inline unsigned long
 294 __xchg_u64_local(volatile void *p, unsigned long val)
 295 {
 296         unsigned long prev;
 297
 298         __asm__ __volatile__(
 299 "1:     ldarx   %0,0,%2 \n"
 300         PPC405_ERR77(0,%2)
 301 "       stdcx.  %3,0,%2 \n\
 302         bne-    1b"
 303         : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
 304         : "r" (p), "r" (val)
 305         : "cc", "memory");
 306
 307         return prev;
 308 }
 309 #endif
 310
 311 /*
 312  * This function doesn't exist, so you'll get a linker error
 313  * if something tries to do an invalid xchg().
 314  */
 315 extern void __xchg_called_with_bad_pointer(void);
 316
 317 static __always_inline unsigned long
 318 __xchg(volatile void *ptr, unsigned long x, unsigned int size)
 319 {
 320         switch (size) {
 321         case 4:
 322                 return __xchg_u32(ptr, x);
 323 #ifdef CONFIG_PPC64
 324         case 8:
 325                 return __xchg_u64(ptr, x);
 326 #endif
 327         }
 328         __xchg_called_with_bad_pointer();
 329         return x;
 330 }
 331
 332 static __always_inline unsigned long
 333 __xchg_local(volatile void *ptr, unsigned long x, unsigned int size)
 334 {
 335         switch (size) {
 336         case 4:
 337                 return __xchg_u32_local(ptr, x);
 338 #ifdef CONFIG_PPC64
 339         case 8:
 340                 return __xchg_u64_local(ptr, x);
 341 #endif
 342         }
 343         __xchg_called_with_bad_pointer();
 344         return x;
 345 }
 346 #define xchg(ptr,x)                                                          \
 347   ({                                                                         \
 348      __typeof__(*(ptr)) _x_ = (x);                                           \
 349      (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
 350   })
 351
 352 #define xchg_local(ptr,x)                                                    \
 353   ({                                                                         \
 354      __typeof__(*(ptr)) _x_ = (x);                                           \
 355      (__typeof__(*(ptr))) __xchg_local((ptr),                                \
 356                 (unsigned long)_x_, sizeof(*(ptr)));                         \
 357   })
 358
 359 /*
 360  * Compare and exchange - if *p == old, set it to new,
 361  * and return the old value of *p.
 362  */
 363 #define __HAVE_ARCH_CMPXCHG     1
 364
 365 static __always_inline unsigned long
 366 __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
 367 {
 368         unsigned int prev;
 369
 370         __asm__ __volatile__ (
 371         PPC_RELEASE_BARRIER
 372 "1:     lwarx   %0,0,%2         # __cmpxchg_u32\n\
 373         cmpw    0,%0,%3\n\
 374         bne-    2f\n"
 375         PPC405_ERR77(0,%2)
 376 "       stwcx.  %4,0,%2\n\
 377         bne-    1b"
 378         PPC_ACQUIRE_BARRIER
 379         "\n\
 380 2:"
 381         : "=&r" (prev), "+m" (*p)
 382         : "r" (p), "r" (old), "r" (new)
 383         : "cc", "memory");
 384
 385         return prev;
 386 }
 387
 388 static __always_inline unsigned long
 389 __cmpxchg_u32_local(volatile unsigned int *p, unsigned long old,
 390                         unsigned long new)
 391 {
 392         unsigned int prev;
 393
 394         __asm__ __volatile__ (
 395 "1:     lwarx   %0,0,%2         # __cmpxchg_u32\n\
 396         cmpw    0,%0,%3\n\
 397         bne-    2f\n"
 398         PPC405_ERR77(0,%2)
 399 "       stwcx.  %4,0,%2\n\
 400         bne-    1b"
 401         "\n\
 402 2:"
 403         : "=&r" (prev), "+m" (*p)
 404         : "r" (p), "r" (old), "r" (new)
 405         : "cc", "memory");
 406
 407         return prev;
 408 }
 409
 410 #ifdef CONFIG_PPC64
 411 static __always_inline unsigned long
 412 __cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
 413 {
 414         unsigned long prev;
 415
 416         __asm__ __volatile__ (
 417         PPC_RELEASE_BARRIER
 418 "1:     ldarx   %0,0,%2         # __cmpxchg_u64\n\
 419         cmpd    0,%0,%3\n\
 420         bne-    2f\n\
 421         stdcx.  %4,0,%2\n\
 422         bne-    1b"
 423         PPC_ACQUIRE_BARRIER
 424         "\n\
 425 2:"
 426         : "=&r" (prev), "+m" (*p)
 427         : "r" (p), "r" (old), "r" (new)
 428         : "cc", "memory");
 429
 430         return prev;
 431 }
 432
 433 static __always_inline unsigned long
 434 __cmpxchg_u64_local(volatile unsigned long *p, unsigned long old,
 435                         unsigned long new)
 436 {
 437         unsigned long prev;
 438
 439         __asm__ __volatile__ (
 440 "1:     ldarx   %0,0,%2         # __cmpxchg_u64\n\
 441         cmpd    0,%0,%3\n\
 442         bne-    2f\n\
 443         stdcx.  %4,0,%2\n\
 444         bne-    1b"
 445         "\n\
 446 2:"
 447         : "=&r" (prev), "+m" (*p)
 448         : "r" (p), "r" (old), "r" (new)
 449         : "cc", "memory");
 450
 451         return prev;
 452 }
 453 #endif
 454
 455 /* This function doesn't exist, so you'll get a linker error
 456    if something tries to do an invalid cmpxchg().  */
 457 extern void __cmpxchg_called_with_bad_pointer(void);
 458
 459 static __always_inline unsigned long
 460 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
 461           unsigned int size)
 462 {
 463         switch (size) {
 464         case 4:
 465                 return __cmpxchg_u32(ptr, old, new);
 466 #ifdef CONFIG_PPC64
 467         case 8:
 468                 return __cmpxchg_u64(ptr, old, new);
 469 #endif
 470         }
 471         __cmpxchg_called_with_bad_pointer();
 472         return old;
 473 }
 474
 475 static __always_inline unsigned long
 476 __cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
 477           unsigned int size)
 478 {
 479         switch (size) {
 480         case 4:
 481                 return __cmpxchg_u32_local(ptr, old, new);
 482 #ifdef CONFIG_PPC64
 483         case 8:
 484                 return __cmpxchg_u64_local(ptr, old, new);
 485 #endif
 486         }
 487         __cmpxchg_called_with_bad_pointer();
 488         return old;
 489 }
 490
 491 #define cmpxchg(ptr, o, n)                                               \
 492   ({                                                                     \
 493      __typeof__(*(ptr)) _o_ = (o);                                       \
 494      __typeof__(*(ptr)) _n_ = (n);                                       \
 495      (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
 496                                     (unsigned long)_n_, sizeof(*(ptr))); \
 497   })
 498
 499
 500 #define cmpxchg_local(ptr, o, n)                                         \
 501   ({                                                                     \
 502      __typeof__(*(ptr)) _o_ = (o);                                       \
 503      __typeof__(*(ptr)) _n_ = (n);                                       \
 504      (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_,     \
 505                                     (unsigned long)_n_, sizeof(*(ptr))); \
 506   })
 507
 508 #ifdef CONFIG_PPC64
 509 /*
 510  * We handle most unaligned accesses in hardware. On the other hand
 511  * unaligned DMA can be very expensive on some ppc64 IO chips (it does
 512  * powers of 2 writes until it reaches sufficient alignment).
 513  *
 514  * Based on this we disable the IP header alignment in network drivers.
 515  */
 516 #define NET_IP_ALIGN    0
 517
 518 #define cmpxchg64(ptr, o, n)                                            \
 519   ({                                                                    \
 520         BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
 521         cmpxchg((ptr), (o), (n));                                       \
 522   })
 523 #define cmpxchg64_local(ptr, o, n)                                      \
 524   ({                                                                    \
 525         BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
 526         cmpxchg_local((ptr), (o), (n));                                 \
 527   })
 528 #else
 529 #include <asm-generic/cmpxchg-local.h>
 530 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
 531 #endif
 532
 533 extern unsigned long arch_align_stack(unsigned long sp);
 534
 535 /* Used in very early kernel initialization. */
 536 extern unsigned long reloc_offset(void);
 537 extern unsigned long add_reloc_offset(unsigned long);
 538 extern void reloc_got2(unsigned long);
 539
 540 #define PTRRELOC(x)     ((typeof(x)) add_reloc_offset((unsigned long)(x)))
 541
 542 extern struct dentry *powerpc_debugfs_root;
 543
 544 #endif /* __KERNEL__ */
 545 #endif /* _ASM_POWERPC_SYSTEM_H */