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Merge remote-tracking branch 's5p/for-next'
[linux-2.6/next.git] / drivers / scsi / lpfc / lpfc_hw.h
blob046edc4ab35f7a858dc6c536b06c41c2cb3defe8
1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2004-2010 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *******************************************************************/
20
21 #define FDMI_DID 0xfffffaU
22 #define NameServer_DID 0xfffffcU
23 #define SCR_DID 0xfffffdU
24 #define Fabric_DID 0xfffffeU
25 #define Bcast_DID 0xffffffU
26 #define Mask_DID 0xffffffU
27 #define CT_DID_MASK 0xffff00U
28 #define Fabric_DID_MASK 0xfff000U
29 #define WELL_KNOWN_DID_MASK 0xfffff0U
30
31 #define PT2PT_LocalID 1
32 #define PT2PT_RemoteID 2
33
34 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
35 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
36 #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */
37 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
38
39 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
40 0 */
41
42 #define FCELSSIZE 1024 /* maximum ELS transfer size */
43
44 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
45 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
46 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
47 #define LPFC_FCP_NEXT_RING 3
48
49 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
50 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
51 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
52 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
53 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
54 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
55 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
56 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
57 #define SLI2_IOCB_CMD_R3_ENTRIES 0
58 #define SLI2_IOCB_RSP_R3_ENTRIES 0
59 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
60 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
61
62 #define SLI2_IOCB_CMD_SIZE 32
63 #define SLI2_IOCB_RSP_SIZE 32
64 #define SLI3_IOCB_CMD_SIZE 128
65 #define SLI3_IOCB_RSP_SIZE 64
66
67 #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff
68 #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff
69
70 /* vendor ID used in SCSI netlink calls */
71 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
72
73 /* Common Transport structures and definitions */
74
75 union CtRevisionId {
76 /* Structure is in Big Endian format */
77 struct {
78 uint32_t Revision:8;
79 uint32_t InId:24;
80 } bits;
81 uint32_t word;
82 };
83
84 union CtCommandResponse {
85 /* Structure is in Big Endian format */
86 struct {
87 uint32_t CmdRsp:16;
88 uint32_t Size:16;
89 } bits;
90 uint32_t word;
91 };
92
93 #define FC4_FEATURE_INIT 0x2
94 #define FC4_FEATURE_TARGET 0x1
95
96 struct lpfc_sli_ct_request {
97 /* Structure is in Big Endian format */
98 union CtRevisionId RevisionId;
99 uint8_t FsType;
100 uint8_t FsSubType;
101 uint8_t Options;
102 uint8_t Rsrvd1;
103 union CtCommandResponse CommandResponse;
104 uint8_t Rsrvd2;
105 uint8_t ReasonCode;
106 uint8_t Explanation;
107 uint8_t VendorUnique;
108
109 union {
110 uint32_t PortID;
111 struct gid {
112 uint8_t PortType; /* for GID_PT requests */
113 uint8_t DomainScope;
114 uint8_t AreaScope;
115 uint8_t Fc4Type; /* for GID_FT requests */
116 } gid;
117 struct rft {
118 uint32_t PortId; /* For RFT_ID requests */
119
120 #ifdef __BIG_ENDIAN_BITFIELD
121 uint32_t rsvd0:16;
122 uint32_t rsvd1:7;
123 uint32_t fcpReg:1; /* Type 8 */
124 uint32_t rsvd2:2;
125 uint32_t ipReg:1; /* Type 5 */
126 uint32_t rsvd3:5;
127 #else /* __LITTLE_ENDIAN_BITFIELD */
128 uint32_t rsvd0:16;
129 uint32_t fcpReg:1; /* Type 8 */
130 uint32_t rsvd1:7;
131 uint32_t rsvd3:5;
132 uint32_t ipReg:1; /* Type 5 */
133 uint32_t rsvd2:2;
134 #endif
135
136 uint32_t rsvd[7];
137 } rft;
138 struct rnn {
139 uint32_t PortId; /* For RNN_ID requests */
140 uint8_t wwnn[8];
141 } rnn;
142 struct rsnn { /* For RSNN_ID requests */
143 uint8_t wwnn[8];
144 uint8_t len;
145 uint8_t symbname[255];
146 } rsnn;
147 struct da_id { /* For DA_ID requests */
148 uint32_t port_id;
149 } da_id;
150 struct rspn { /* For RSPN_ID requests */
151 uint32_t PortId;
152 uint8_t len;
153 uint8_t symbname[255];
154 } rspn;
155 struct gff {
156 uint32_t PortId;
157 } gff;
158 struct gff_acc {
159 uint8_t fbits[128];
160 } gff_acc;
161 #define FCP_TYPE_FEATURE_OFFSET 7
162 struct rff {
163 uint32_t PortId;
164 uint8_t reserved[2];
165 uint8_t fbits;
166 uint8_t type_code; /* type=8 for FCP */
167 } rff;
168 } un;
169 };
170
171 #define SLI_CT_REVISION 1
172 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
173 sizeof(struct gid))
174 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
175 sizeof(struct gff))
176 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
177 sizeof(struct rft))
178 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
179 sizeof(struct rff))
180 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
181 sizeof(struct rnn))
182 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
183 sizeof(struct rsnn))
184 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
185 sizeof(struct da_id))
186 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
187 sizeof(struct rspn))
188
189 /*
190 * FsType Definitions
191 */
192
193 #define SLI_CT_MANAGEMENT_SERVICE 0xFA
194 #define SLI_CT_TIME_SERVICE 0xFB
195 #define SLI_CT_DIRECTORY_SERVICE 0xFC
196 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
197
198 /*
199 * Directory Service Subtypes
200 */
201
202 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02
203
204 /*
205 * Response Codes
206 */
207
208 #define SLI_CT_RESPONSE_FS_RJT 0x8001
209 #define SLI_CT_RESPONSE_FS_ACC 0x8002
210
211 /*
212 * Reason Codes
213 */
214
215 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0
216 #define SLI_CT_INVALID_COMMAND 0x01
217 #define SLI_CT_INVALID_VERSION 0x02
218 #define SLI_CT_LOGICAL_ERROR 0x03
219 #define SLI_CT_INVALID_IU_SIZE 0x04
220 #define SLI_CT_LOGICAL_BUSY 0x05
221 #define SLI_CT_PROTOCOL_ERROR 0x07
222 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
223 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b
224 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
225 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
226 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
227 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
228 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
229 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
230 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
231 #define SLI_CT_VENDOR_UNIQUE 0xff
232
233 /*
234 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
235 */
236
237 #define SLI_CT_NO_PORT_ID 0x01
238 #define SLI_CT_NO_PORT_NAME 0x02
239 #define SLI_CT_NO_NODE_NAME 0x03
240 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04
241 #define SLI_CT_NO_IP_ADDRESS 0x05
242 #define SLI_CT_NO_IPA 0x06
243 #define SLI_CT_NO_FC4_TYPES 0x07
244 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
245 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
246 #define SLI_CT_NO_PORT_TYPE 0x0A
247 #define SLI_CT_ACCESS_DENIED 0x10
248 #define SLI_CT_INVALID_PORT_ID 0x11
249 #define SLI_CT_DATABASE_EMPTY 0x12
250
251 /*
252 * Name Server Command Codes
253 */
254
255 #define SLI_CTNS_GA_NXT 0x0100
256 #define SLI_CTNS_GPN_ID 0x0112
257 #define SLI_CTNS_GNN_ID 0x0113
258 #define SLI_CTNS_GCS_ID 0x0114
259 #define SLI_CTNS_GFT_ID 0x0117
260 #define SLI_CTNS_GSPN_ID 0x0118
261 #define SLI_CTNS_GPT_ID 0x011A
262 #define SLI_CTNS_GFF_ID 0x011F
263 #define SLI_CTNS_GID_PN 0x0121
264 #define SLI_CTNS_GID_NN 0x0131
265 #define SLI_CTNS_GIP_NN 0x0135
266 #define SLI_CTNS_GIPA_NN 0x0136
267 #define SLI_CTNS_GSNN_NN 0x0139
268 #define SLI_CTNS_GNN_IP 0x0153
269 #define SLI_CTNS_GIPA_IP 0x0156
270 #define SLI_CTNS_GID_FT 0x0171
271 #define SLI_CTNS_GID_PT 0x01A1
272 #define SLI_CTNS_RPN_ID 0x0212
273 #define SLI_CTNS_RNN_ID 0x0213
274 #define SLI_CTNS_RCS_ID 0x0214
275 #define SLI_CTNS_RFT_ID 0x0217
276 #define SLI_CTNS_RSPN_ID 0x0218
277 #define SLI_CTNS_RPT_ID 0x021A
278 #define SLI_CTNS_RFF_ID 0x021F
279 #define SLI_CTNS_RIP_NN 0x0235
280 #define SLI_CTNS_RIPA_NN 0x0236
281 #define SLI_CTNS_RSNN_NN 0x0239
282 #define SLI_CTNS_DA_ID 0x0300
283
284 /*
285 * Port Types
286 */
287
288 #define SLI_CTPT_N_PORT 0x01
289 #define SLI_CTPT_NL_PORT 0x02
290 #define SLI_CTPT_FNL_PORT 0x03
291 #define SLI_CTPT_IP 0x04
292 #define SLI_CTPT_FCP 0x08
293 #define SLI_CTPT_NX_PORT 0x7F
294 #define SLI_CTPT_F_PORT 0x81
295 #define SLI_CTPT_FL_PORT 0x82
296 #define SLI_CTPT_E_PORT 0x84
297
298 #define SLI_CT_LAST_ENTRY 0x80000000
299
300 /* Fibre Channel Service Parameter definitions */
301
302 #define FC_PH_4_0 6 /* FC-PH version 4.0 */
303 #define FC_PH_4_1 7 /* FC-PH version 4.1 */
304 #define FC_PH_4_2 8 /* FC-PH version 4.2 */
305 #define FC_PH_4_3 9 /* FC-PH version 4.3 */
306
307 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */
308 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */
309 #define FC_PH3 0x20 /* FC-PH-3 version */
310
311 #define FF_FRAME_SIZE 2048
312
313 struct lpfc_name {
314 union {
315 struct {
316 #ifdef __BIG_ENDIAN_BITFIELD
317 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
318 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
319 8:11 of IEEE ext */
320 #else /* __LITTLE_ENDIAN_BITFIELD */
321 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
322 8:11 of IEEE ext */
323 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
324 #endif
325
326 #define NAME_IEEE 0x1 /* IEEE name - nameType */
327 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */
328 #define NAME_FC_TYPE 0x3 /* FC native name type */
329 #define NAME_IP_TYPE 0x4 /* IP address */
330 #define NAME_CCITT_TYPE 0xC
331 #define NAME_CCITT_GR_TYPE 0xE
332 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
333 extended Lsb */
334 uint8_t IEEE[6]; /* FC IEEE address */
335 } s;
336 uint8_t wwn[8];
337 } u;
338 };
339
340 struct csp {
341 uint8_t fcphHigh; /* FC Word 0, byte 0 */
342 uint8_t fcphLow;
343 uint8_t bbCreditMsb;
344 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */
345
346 /*
347 * Word 1 Bit 31 in common service parameter is overloaded.
348 * Word 1 Bit 31 in FLOGI request is multiple NPort request
349 * Word 1 Bit 31 in FLOGI response is clean address bit
350 */
351 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
352 #ifdef __BIG_ENDIAN_BITFIELD
353 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
354 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
355 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
356 uint16_t fPort:1; /* FC Word 1, bit 28 */
357 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
358 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
359 uint16_t multicast:1; /* FC Word 1, bit 25 */
360 uint16_t broadcast:1; /* FC Word 1, bit 24 */
361
362 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
363 uint16_t simplex:1; /* FC Word 1, bit 22 */
364 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
365 uint16_t dhd:1; /* FC Word 1, bit 18 */
366 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
367 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
368 #else /* __LITTLE_ENDIAN_BITFIELD */
369 uint16_t broadcast:1; /* FC Word 1, bit 24 */
370 uint16_t multicast:1; /* FC Word 1, bit 25 */
371 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
372 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
373 uint16_t fPort:1; /* FC Word 1, bit 28 */
374 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
375 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
376 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
377
378 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
379 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
380 uint16_t dhd:1; /* FC Word 1, bit 18 */
381 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
382 uint16_t simplex:1; /* FC Word 1, bit 22 */
383 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
384 #endif
385
386 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
387 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
388 union {
389 struct {
390 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
391
392 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
393 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
394
395 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
396 } nPort;
397 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
398 } w2;
399
400 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
401 };
402
403 struct class_parms {
404 #ifdef __BIG_ENDIAN_BITFIELD
405 uint8_t classValid:1; /* FC Word 0, bit 31 */
406 uint8_t intermix:1; /* FC Word 0, bit 30 */
407 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
408 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
409 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
410 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
411 #else /* __LITTLE_ENDIAN_BITFIELD */
412 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
413 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
414 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
415 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
416 uint8_t intermix:1; /* FC Word 0, bit 30 */
417 uint8_t classValid:1; /* FC Word 0, bit 31 */
418
419 #endif
420
421 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
422
423 #ifdef __BIG_ENDIAN_BITFIELD
424 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
425 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
426 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
427 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
428 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
429 #else /* __LITTLE_ENDIAN_BITFIELD */
430 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
431 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
432 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
433 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
434 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
435 #endif
436
437 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
438
439 #ifdef __BIG_ENDIAN_BITFIELD
440 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
441 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
442 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
443 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
444 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
445 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
446 #else /* __LITTLE_ENDIAN_BITFIELD */
447 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
448 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
449 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
450 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
451 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
452 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
453 #endif
454
455 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
456 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
457 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
458
459 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
460 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
461 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
462 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
463
464 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
465 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
466 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
467 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
468 };
469
470 struct serv_parm { /* Structure is in Big Endian format */
471 struct csp cmn;
472 struct lpfc_name portName;
473 struct lpfc_name nodeName;
474 struct class_parms cls1;
475 struct class_parms cls2;
476 struct class_parms cls3;
477 struct class_parms cls4;
478 uint8_t vendorVersion[16];
479 };
480
481 /*
482 * Virtual Fabric Tagging Header
483 */
484 struct fc_vft_header {
485 uint32_t word0;
486 #define fc_vft_hdr_r_ctl_SHIFT 24
487 #define fc_vft_hdr_r_ctl_MASK 0xFF
488 #define fc_vft_hdr_r_ctl_WORD word0
489 #define fc_vft_hdr_ver_SHIFT 22
490 #define fc_vft_hdr_ver_MASK 0x3
491 #define fc_vft_hdr_ver_WORD word0
492 #define fc_vft_hdr_type_SHIFT 18
493 #define fc_vft_hdr_type_MASK 0xF
494 #define fc_vft_hdr_type_WORD word0
495 #define fc_vft_hdr_e_SHIFT 16
496 #define fc_vft_hdr_e_MASK 0x1
497 #define fc_vft_hdr_e_WORD word0
498 #define fc_vft_hdr_priority_SHIFT 13
499 #define fc_vft_hdr_priority_MASK 0x7
500 #define fc_vft_hdr_priority_WORD word0
501 #define fc_vft_hdr_vf_id_SHIFT 1
502 #define fc_vft_hdr_vf_id_MASK 0xFFF
503 #define fc_vft_hdr_vf_id_WORD word0
504 uint32_t word1;
505 #define fc_vft_hdr_hopct_SHIFT 24
506 #define fc_vft_hdr_hopct_MASK 0xFF
507 #define fc_vft_hdr_hopct_WORD word1
508 };
509
510 /*
511 * Extended Link Service LS_COMMAND codes (Payload Word 0)
512 */
513 #ifdef __BIG_ENDIAN_BITFIELD
514 #define ELS_CMD_MASK 0xffff0000
515 #define ELS_RSP_MASK 0xff000000
516 #define ELS_CMD_LS_RJT 0x01000000
517 #define ELS_CMD_ACC 0x02000000
518 #define ELS_CMD_PLOGI 0x03000000
519 #define ELS_CMD_FLOGI 0x04000000
520 #define ELS_CMD_LOGO 0x05000000
521 #define ELS_CMD_ABTX 0x06000000
522 #define ELS_CMD_RCS 0x07000000
523 #define ELS_CMD_RES 0x08000000
524 #define ELS_CMD_RSS 0x09000000
525 #define ELS_CMD_RSI 0x0A000000
526 #define ELS_CMD_ESTS 0x0B000000
527 #define ELS_CMD_ESTC 0x0C000000
528 #define ELS_CMD_ADVC 0x0D000000
529 #define ELS_CMD_RTV 0x0E000000
530 #define ELS_CMD_RLS 0x0F000000
531 #define ELS_CMD_ECHO 0x10000000
532 #define ELS_CMD_TEST 0x11000000
533 #define ELS_CMD_RRQ 0x12000000
534 #define ELS_CMD_PRLI 0x20100014
535 #define ELS_CMD_PRLO 0x21100014
536 #define ELS_CMD_PRLO_ACC 0x02100014
537 #define ELS_CMD_PDISC 0x50000000
538 #define ELS_CMD_FDISC 0x51000000
539 #define ELS_CMD_ADISC 0x52000000
540 #define ELS_CMD_FARP 0x54000000
541 #define ELS_CMD_FARPR 0x55000000
542 #define ELS_CMD_RPS 0x56000000
543 #define ELS_CMD_RPL 0x57000000
544 #define ELS_CMD_FAN 0x60000000
545 #define ELS_CMD_RSCN 0x61040000
546 #define ELS_CMD_SCR 0x62000000
547 #define ELS_CMD_RNID 0x78000000
548 #define ELS_CMD_LIRR 0x7A000000
549 #else /* __LITTLE_ENDIAN_BITFIELD */
550 #define ELS_CMD_MASK 0xffff
551 #define ELS_RSP_MASK 0xff
552 #define ELS_CMD_LS_RJT 0x01
553 #define ELS_CMD_ACC 0x02
554 #define ELS_CMD_PLOGI 0x03
555 #define ELS_CMD_FLOGI 0x04
556 #define ELS_CMD_LOGO 0x05
557 #define ELS_CMD_ABTX 0x06
558 #define ELS_CMD_RCS 0x07
559 #define ELS_CMD_RES 0x08
560 #define ELS_CMD_RSS 0x09
561 #define ELS_CMD_RSI 0x0A
562 #define ELS_CMD_ESTS 0x0B
563 #define ELS_CMD_ESTC 0x0C
564 #define ELS_CMD_ADVC 0x0D
565 #define ELS_CMD_RTV 0x0E
566 #define ELS_CMD_RLS 0x0F
567 #define ELS_CMD_ECHO 0x10
568 #define ELS_CMD_TEST 0x11
569 #define ELS_CMD_RRQ 0x12
570 #define ELS_CMD_PRLI 0x14001020
571 #define ELS_CMD_PRLO 0x14001021
572 #define ELS_CMD_PRLO_ACC 0x14001002
573 #define ELS_CMD_PDISC 0x50
574 #define ELS_CMD_FDISC 0x51
575 #define ELS_CMD_ADISC 0x52
576 #define ELS_CMD_FARP 0x54
577 #define ELS_CMD_FARPR 0x55
578 #define ELS_CMD_RPS 0x56
579 #define ELS_CMD_RPL 0x57
580 #define ELS_CMD_FAN 0x60
581 #define ELS_CMD_RSCN 0x0461
582 #define ELS_CMD_SCR 0x62
583 #define ELS_CMD_RNID 0x78
584 #define ELS_CMD_LIRR 0x7A
585 #endif
586
587 /*
588 * LS_RJT Payload Definition
589 */
590
591 struct ls_rjt { /* Structure is in Big Endian format */
592 union {
593 uint32_t lsRjtError;
594 struct {
595 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
596
597 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
598 /* LS_RJT reason codes */
599 #define LSRJT_INVALID_CMD 0x01
600 #define LSRJT_LOGICAL_ERR 0x03
601 #define LSRJT_LOGICAL_BSY 0x05
602 #define LSRJT_PROTOCOL_ERR 0x07
603 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
604 #define LSRJT_CMD_UNSUPPORTED 0x0B
605 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
606
607 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
608 /* LS_RJT reason explanation */
609 #define LSEXP_NOTHING_MORE 0x00
610 #define LSEXP_SPARM_OPTIONS 0x01
611 #define LSEXP_SPARM_ICTL 0x03
612 #define LSEXP_SPARM_RCTL 0x05
613 #define LSEXP_SPARM_RCV_SIZE 0x07
614 #define LSEXP_SPARM_CONCUR_SEQ 0x09
615 #define LSEXP_SPARM_CREDIT 0x0B
616 #define LSEXP_INVALID_PNAME 0x0D
617 #define LSEXP_INVALID_NNAME 0x0E
618 #define LSEXP_INVALID_CSP 0x0F
619 #define LSEXP_INVALID_ASSOC_HDR 0x11
620 #define LSEXP_ASSOC_HDR_REQ 0x13
621 #define LSEXP_INVALID_O_SID 0x15
622 #define LSEXP_INVALID_OX_RX 0x17
623 #define LSEXP_CMD_IN_PROGRESS 0x19
624 #define LSEXP_PORT_LOGIN_REQ 0x1E
625 #define LSEXP_INVALID_NPORT_ID 0x1F
626 #define LSEXP_INVALID_SEQ_ID 0x21
627 #define LSEXP_INVALID_XCHG 0x23
628 #define LSEXP_INACTIVE_XCHG 0x25
629 #define LSEXP_RQ_REQUIRED 0x27
630 #define LSEXP_OUT_OF_RESOURCE 0x29
631 #define LSEXP_CANT_GIVE_DATA 0x2A
632 #define LSEXP_REQ_UNSUPPORTED 0x2C
633 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
634 } b;
635 } un;
636 };
637
638 /*
639 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
640 */
641
642 typedef struct _LOGO { /* Structure is in Big Endian format */
643 union {
644 uint32_t nPortId32; /* Access nPortId as a word */
645 struct {
646 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
647 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
648 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
649 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
650 } b;
651 } un;
652 struct lpfc_name portName; /* N_port name field */
653 } LOGO;
654
655 /*
656 * FCP Login (PRLI Request / ACC) Payload Definition
657 */
658
659 #define PRLX_PAGE_LEN 0x10
660 #define TPRLO_PAGE_LEN 0x14
661
662 typedef struct _PRLI { /* Structure is in Big Endian format */
663 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
664
665 #define PRLI_FCP_TYPE 0x08
666 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
667
668 #ifdef __BIG_ENDIAN_BITFIELD
669 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
670 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
671 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
672
673 /* ACC = imagePairEstablished */
674 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
675 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
676 #else /* __LITTLE_ENDIAN_BITFIELD */
677 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
678 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
679 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
680 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
681 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
682 /* ACC = imagePairEstablished */
683 #endif
684
685 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
686 #define PRLI_NO_RESOURCES 0x2
687 #define PRLI_INIT_INCOMPLETE 0x3
688 #define PRLI_NO_SUCH_PA 0x4
689 #define PRLI_PREDEF_CONFIG 0x5
690 #define PRLI_PARTIAL_SUCCESS 0x6
691 #define PRLI_INVALID_PAGE_CNT 0x7
692 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
693
694 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
695
696 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
697
698 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
699 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
700
701 #ifdef __BIG_ENDIAN_BITFIELD
702 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
703 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
704 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
705 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
706 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
707 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
708 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
709 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
710 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
711 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
712 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
713 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
714 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
715 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
716 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
717 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
718 #else /* __LITTLE_ENDIAN_BITFIELD */
719 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
720 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
721 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
722 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
723 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
724 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
725 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
726 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
727 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
728 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
729 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
730 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
731 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
732 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
733 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
734 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
735 #endif
736 } PRLI;
737
738 /*
739 * FCP Logout (PRLO Request / ACC) Payload Definition
740 */
741
742 typedef struct _PRLO { /* Structure is in Big Endian format */
743 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
744
745 #define PRLO_FCP_TYPE 0x08
746 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
747
748 #ifdef __BIG_ENDIAN_BITFIELD
749 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
750 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
751 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
752 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
753 #else /* __LITTLE_ENDIAN_BITFIELD */
754 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
755 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
756 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
757 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
758 #endif
759
760 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
761 #define PRLO_NO_SUCH_IMAGE 0x4
762 #define PRLO_INVALID_PAGE_CNT 0x7
763
764 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
765
766 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
767
768 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
769
770 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
771 } PRLO;
772
773 typedef struct _ADISC { /* Structure is in Big Endian format */
774 uint32_t hardAL_PA;
775 struct lpfc_name portName;
776 struct lpfc_name nodeName;
777 uint32_t DID;
778 } ADISC;
779
780 typedef struct _FARP { /* Structure is in Big Endian format */
781 uint32_t Mflags:8;
782 uint32_t Odid:24;
783 #define FARP_NO_ACTION 0 /* FARP information enclosed, no
784 action */
785 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
786 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
787 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
788 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
789 supported */
790 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
791 supported */
792 uint32_t Rflags:8;
793 uint32_t Rdid:24;
794 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
795 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
796 struct lpfc_name OportName;
797 struct lpfc_name OnodeName;
798 struct lpfc_name RportName;
799 struct lpfc_name RnodeName;
800 uint8_t Oipaddr[16];
801 uint8_t Ripaddr[16];
802 } FARP;
803
804 typedef struct _FAN { /* Structure is in Big Endian format */
805 uint32_t Fdid;
806 struct lpfc_name FportName;
807 struct lpfc_name FnodeName;
808 } FAN;
809
810 typedef struct _SCR { /* Structure is in Big Endian format */
811 uint8_t resvd1;
812 uint8_t resvd2;
813 uint8_t resvd3;
814 uint8_t Function;
815 #define SCR_FUNC_FABRIC 0x01
816 #define SCR_FUNC_NPORT 0x02
817 #define SCR_FUNC_FULL 0x03
818 #define SCR_CLEAR 0xff
819 } SCR;
820
821 typedef struct _RNID_TOP_DISC {
822 struct lpfc_name portName;
823 uint8_t resvd[8];
824 uint32_t unitType;
825 #define RNID_HBA 0x7
826 #define RNID_HOST 0xa
827 #define RNID_DRIVER 0xd
828 uint32_t physPort;
829 uint32_t attachedNodes;
830 uint16_t ipVersion;
831 #define RNID_IPV4 0x1
832 #define RNID_IPV6 0x2
833 uint16_t UDPport;
834 uint8_t ipAddr[16];
835 uint16_t resvd1;
836 uint16_t flags;
837 #define RNID_TD_SUPPORT 0x1
838 #define RNID_LP_VALID 0x2
839 } RNID_TOP_DISC;
840
841 typedef struct _RNID { /* Structure is in Big Endian format */
842 uint8_t Format;
843 #define RNID_TOPOLOGY_DISC 0xdf
844 uint8_t CommonLen;
845 uint8_t resvd1;
846 uint8_t SpecificLen;
847 struct lpfc_name portName;
848 struct lpfc_name nodeName;
849 union {
850 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
851 } un;
852 } RNID;
853
854 typedef struct _RPS { /* Structure is in Big Endian format */
855 union {
856 uint32_t portNum;
857 struct lpfc_name portName;
858 } un;
859 } RPS;
860
861 typedef struct _RPS_RSP { /* Structure is in Big Endian format */
862 uint16_t rsvd1;
863 uint16_t portStatus;
864 uint32_t linkFailureCnt;
865 uint32_t lossSyncCnt;
866 uint32_t lossSignalCnt;
867 uint32_t primSeqErrCnt;
868 uint32_t invalidXmitWord;
869 uint32_t crcCnt;
870 } RPS_RSP;
871
872 struct RLS { /* Structure is in Big Endian format */
873 uint32_t rls;
874 #define rls_rsvd_SHIFT 24
875 #define rls_rsvd_MASK 0x000000ff
876 #define rls_rsvd_WORD rls
877 #define rls_did_SHIFT 0
878 #define rls_did_MASK 0x00ffffff
879 #define rls_did_WORD rls
880 };
881
882 struct RLS_RSP { /* Structure is in Big Endian format */
883 uint32_t linkFailureCnt;
884 uint32_t lossSyncCnt;
885 uint32_t lossSignalCnt;
886 uint32_t primSeqErrCnt;
887 uint32_t invalidXmitWord;
888 uint32_t crcCnt;
889 };
890
891 struct RRQ { /* Structure is in Big Endian format */
892 uint32_t rrq;
893 #define rrq_rsvd_SHIFT 24
894 #define rrq_rsvd_MASK 0x000000ff
895 #define rrq_rsvd_WORD rrq
896 #define rrq_did_SHIFT 0
897 #define rrq_did_MASK 0x00ffffff
898 #define rrq_did_WORD rrq
899 uint32_t rrq_exchg;
900 #define rrq_oxid_SHIFT 16
901 #define rrq_oxid_MASK 0xffff
902 #define rrq_oxid_WORD rrq_exchg
903 #define rrq_rxid_SHIFT 0
904 #define rrq_rxid_MASK 0xffff
905 #define rrq_rxid_WORD rrq_exchg
906 };
907
908 #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */
909 #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/
910
911 struct RTV_RSP { /* Structure is in Big Endian format */
912 uint32_t ratov;
913 uint32_t edtov;
914 uint32_t qtov;
915 #define qtov_rsvd0_SHIFT 28
916 #define qtov_rsvd0_MASK 0x0000000f
917 #define qtov_rsvd0_WORD qtov /* reserved */
918 #define qtov_edtovres_SHIFT 27
919 #define qtov_edtovres_MASK 0x00000001
920 #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */
921 #define qtov__rsvd1_SHIFT 19
922 #define qtov_rsvd1_MASK 0x0000003f
923 #define qtov_rsvd1_WORD qtov /* reserved */
924 #define qtov_rttov_SHIFT 18
925 #define qtov_rttov_MASK 0x00000001
926 #define qtov_rttov_WORD qtov /* R_T_TOV value */
927 #define qtov_rsvd2_SHIFT 0
928 #define qtov_rsvd2_MASK 0x0003ffff
929 #define qtov_rsvd2_WORD qtov /* reserved */
930 };
931
932
933 typedef struct _RPL { /* Structure is in Big Endian format */
934 uint32_t maxsize;
935 uint32_t index;
936 } RPL;
937
938 typedef struct _PORT_NUM_BLK {
939 uint32_t portNum;
940 uint32_t portID;
941 struct lpfc_name portName;
942 } PORT_NUM_BLK;
943
944 typedef struct _RPL_RSP { /* Structure is in Big Endian format */
945 uint32_t listLen;
946 uint32_t index;
947 PORT_NUM_BLK port_num_blk;
948 } RPL_RSP;
949
950 /* This is used for RSCN command */
951 typedef struct _D_ID { /* Structure is in Big Endian format */
952 union {
953 uint32_t word;
954 struct {
955 #ifdef __BIG_ENDIAN_BITFIELD
956 uint8_t resv;
957 uint8_t domain;
958 uint8_t area;
959 uint8_t id;
960 #else /* __LITTLE_ENDIAN_BITFIELD */
961 uint8_t id;
962 uint8_t area;
963 uint8_t domain;
964 uint8_t resv;
965 #endif
966 } b;
967 } un;
968 } D_ID;
969
970 #define RSCN_ADDRESS_FORMAT_PORT 0x0
971 #define RSCN_ADDRESS_FORMAT_AREA 0x1
972 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
973 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3
974 #define RSCN_ADDRESS_FORMAT_MASK 0x3
975
976 /*
977 * Structure to define all ELS Payload types
978 */
979
980 typedef struct _ELS_PKT { /* Structure is in Big Endian format */
981 uint8_t elsCode; /* FC Word 0, bit 24:31 */
982 uint8_t elsByte1;
983 uint8_t elsByte2;
984 uint8_t elsByte3;
985 union {
986 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
987 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
988 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
989 PRLI prli; /* Payload for PRLI/ACC */
990 PRLO prlo; /* Payload for PRLO/ACC */
991 ADISC adisc; /* Payload for ADISC/ACC */
992 FARP farp; /* Payload for FARP/ACC */
993 FAN fan; /* Payload for FAN */
994 SCR scr; /* Payload for SCR/ACC */
995 RNID rnid; /* Payload for RNID */
996 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
997 } un;
998 } ELS_PKT;
999
1000 /*
1001 * FDMI
1002 * HBA MAnagement Operations Command Codes
1003 */
1004 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
1005 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
1006 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
1007 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
1008 #define SLI_MGMT_RHBA 0x200 /* Register HBA */
1009 #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */
1010 #define SLI_MGMT_RPRT 0x210 /* Register Port */
1011 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */
1012 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */
1013 #define SLI_MGMT_DPRT 0x310 /* De-register Port */
1014
1015 /*
1016 * Management Service Subtypes
1017 */
1018 #define SLI_CT_FDMI_Subtypes 0x10
1019
1020 /*
1021 * HBA Management Service Reject Code
1022 */
1023 #define REJECT_CODE 0x9 /* Unable to perform command request */
1024
1025 /*
1026 * HBA Management Service Reject Reason Code
1027 * Please refer to the Reason Codes above
1028 */
1029
1030 /*
1031 * HBA Attribute Types
1032 */
1033 #define NODE_NAME 0x1
1034 #define MANUFACTURER 0x2
1035 #define SERIAL_NUMBER 0x3
1036 #define MODEL 0x4
1037 #define MODEL_DESCRIPTION 0x5
1038 #define HARDWARE_VERSION 0x6
1039 #define DRIVER_VERSION 0x7
1040 #define OPTION_ROM_VERSION 0x8
1041 #define FIRMWARE_VERSION 0x9
1042 #define OS_NAME_VERSION 0xa
1043 #define MAX_CT_PAYLOAD_LEN 0xb
1044
1045 /*
1046 * Port Attrubute Types
1047 */
1048 #define SUPPORTED_FC4_TYPES 0x1
1049 #define SUPPORTED_SPEED 0x2
1050 #define PORT_SPEED 0x3
1051 #define MAX_FRAME_SIZE 0x4
1052 #define OS_DEVICE_NAME 0x5
1053 #define HOST_NAME 0x6
1054
1055 union AttributesDef {
1056 /* Structure is in Big Endian format */
1057 struct {
1058 uint32_t AttrType:16;
1059 uint32_t AttrLen:16;
1060 } bits;
1061 uint32_t word;
1062 };
1063
1064
1065 /*
1066 * HBA Attribute Entry (8 - 260 bytes)
1067 */
1068 typedef struct {
1069 union AttributesDef ad;
1070 union {
1071 uint32_t VendorSpecific;
1072 uint8_t Manufacturer[64];
1073 uint8_t SerialNumber[64];
1074 uint8_t Model[256];
1075 uint8_t ModelDescription[256];
1076 uint8_t HardwareVersion[256];
1077 uint8_t DriverVersion[256];
1078 uint8_t OptionROMVersion[256];
1079 uint8_t FirmwareVersion[256];
1080 struct lpfc_name NodeName;
1081 uint8_t SupportFC4Types[32];
1082 uint32_t SupportSpeed;
1083 uint32_t PortSpeed;
1084 uint32_t MaxFrameSize;
1085 uint8_t OsDeviceName[256];
1086 uint8_t OsNameVersion[256];
1087 uint32_t MaxCTPayloadLen;
1088 uint8_t HostName[256];
1089 } un;
1090 } ATTRIBUTE_ENTRY;
1091
1092 /*
1093 * HBA Attribute Block
1094 */
1095 typedef struct {
1096 uint32_t EntryCnt; /* Number of HBA attribute entries */
1097 ATTRIBUTE_ENTRY Entry; /* Variable-length array */
1098 } ATTRIBUTE_BLOCK;
1099
1100 /*
1101 * Port Entry
1102 */
1103 typedef struct {
1104 struct lpfc_name PortName;
1105 } PORT_ENTRY;
1106
1107 /*
1108 * HBA Identifier
1109 */
1110 typedef struct {
1111 struct lpfc_name PortName;
1112 } HBA_IDENTIFIER;
1113
1114 /*
1115 * Registered Port List Format
1116 */
1117 typedef struct {
1118 uint32_t EntryCnt;
1119 PORT_ENTRY pe; /* Variable-length array */
1120 } REG_PORT_LIST;
1121
1122 /*
1123 * Register HBA(RHBA)
1124 */
1125 typedef struct {
1126 HBA_IDENTIFIER hi;
1127 REG_PORT_LIST rpl; /* variable-length array */
1128 /* ATTRIBUTE_BLOCK ab; */
1129 } REG_HBA;
1130
1131 /*
1132 * Register HBA Attributes (RHAT)
1133 */
1134 typedef struct {
1135 struct lpfc_name HBA_PortName;
1136 ATTRIBUTE_BLOCK ab;
1137 } REG_HBA_ATTRIBUTE;
1138
1139 /*
1140 * Register Port Attributes (RPA)
1141 */
1142 typedef struct {
1143 struct lpfc_name PortName;
1144 ATTRIBUTE_BLOCK ab;
1145 } REG_PORT_ATTRIBUTE;
1146
1147 /*
1148 * Get Registered HBA List (GRHL) Accept Payload Format
1149 */
1150 typedef struct {
1151 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */
1152 struct lpfc_name HBA_PortName; /* Variable-length array */
1153 } GRHL_ACC_PAYLOAD;
1154
1155 /*
1156 * Get Registered Port List (GRPL) Accept Payload Format
1157 */
1158 typedef struct {
1159 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */
1160 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */
1161 } GRPL_ACC_PAYLOAD;
1162
1163 /*
1164 * Get Port Attributes (GPAT) Accept Payload Format
1165 */
1166
1167 typedef struct {
1168 ATTRIBUTE_BLOCK pab;
1169 } GPAT_ACC_PAYLOAD;
1170
1171
1172 /*
1173 * Begin HBA configuration parameters.
1174 * The PCI configuration register BAR assignments are:
1175 * BAR0, offset 0x10 - SLIM base memory address
1176 * BAR1, offset 0x14 - SLIM base memory high address
1177 * BAR2, offset 0x18 - REGISTER base memory address
1178 * BAR3, offset 0x1c - REGISTER base memory high address
1179 * BAR4, offset 0x20 - BIU I/O registers
1180 * BAR5, offset 0x24 - REGISTER base io high address
1181 */
1182
1183 /* Number of rings currently used and available. */
1184 #define MAX_CONFIGURED_RINGS 3
1185 #define MAX_RINGS 4
1186
1187 /* IOCB / Mailbox is owned by FireFly */
1188 #define OWN_CHIP 1
1189
1190 /* IOCB / Mailbox is owned by Host */
1191 #define OWN_HOST 0
1192
1193 /* Number of 4-byte words in an IOCB. */
1194 #define IOCB_WORD_SZ 8
1195
1196 /* network headers for Dfctl field */
1197 #define FC_NET_HDR 0x20
1198
1199 /* Start FireFly Register definitions */
1200 #define PCI_VENDOR_ID_EMULEX 0x10df
1201 #define PCI_DEVICE_ID_FIREFLY 0x1ae5
1202 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100
1203 #define PCI_DEVICE_ID_BALIUS 0xe131
1204 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180
1205 #define PCI_DEVICE_ID_LANCER_FC 0xe200
1206 #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208
1207 #define PCI_DEVICE_ID_LANCER_FCOE 0xe260
1208 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1209 #define PCI_DEVICE_ID_SAT_SMB 0xf011
1210 #define PCI_DEVICE_ID_SAT_MID 0xf015
1211 #define PCI_DEVICE_ID_RFLY 0xf095
1212 #define PCI_DEVICE_ID_PFLY 0xf098
1213 #define PCI_DEVICE_ID_LP101 0xf0a1
1214 #define PCI_DEVICE_ID_TFLY 0xf0a5
1215 #define PCI_DEVICE_ID_BSMB 0xf0d1
1216 #define PCI_DEVICE_ID_BMID 0xf0d5
1217 #define PCI_DEVICE_ID_ZSMB 0xf0e1
1218 #define PCI_DEVICE_ID_ZMID 0xf0e5
1219 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1220 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1221 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
1222 #define PCI_DEVICE_ID_SAT 0xf100
1223 #define PCI_DEVICE_ID_SAT_SCSP 0xf111
1224 #define PCI_DEVICE_ID_SAT_DCSP 0xf112
1225 #define PCI_DEVICE_ID_FALCON 0xf180
1226 #define PCI_DEVICE_ID_SUPERFLY 0xf700
1227 #define PCI_DEVICE_ID_DRAGONFLY 0xf800
1228 #define PCI_DEVICE_ID_CENTAUR 0xf900
1229 #define PCI_DEVICE_ID_PEGASUS 0xf980
1230 #define PCI_DEVICE_ID_THOR 0xfa00
1231 #define PCI_DEVICE_ID_VIPER 0xfb00
1232 #define PCI_DEVICE_ID_LP10000S 0xfc00
1233 #define PCI_DEVICE_ID_LP11000S 0xfc10
1234 #define PCI_DEVICE_ID_LPE11000S 0xfc20
1235 #define PCI_DEVICE_ID_SAT_S 0xfc40
1236 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50
1237 #define PCI_DEVICE_ID_HELIOS 0xfd00
1238 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1239 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
1240 #define PCI_DEVICE_ID_ZEPHYR 0xfe00
1241 #define PCI_DEVICE_ID_HORNET 0xfe05
1242 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1243 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
1244 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2
1245 #define PCI_DEVICE_ID_TIGERSHARK 0x0704
1246 #define PCI_DEVICE_ID_TOMCAT 0x0714
1247
1248 #define JEDEC_ID_ADDRESS 0x0080001c
1249 #define FIREFLY_JEDEC_ID 0x1ACC
1250 #define SUPERFLY_JEDEC_ID 0x0020
1251 #define DRAGONFLY_JEDEC_ID 0x0021
1252 #define DRAGONFLY_V2_JEDEC_ID 0x0025
1253 #define CENTAUR_2G_JEDEC_ID 0x0026
1254 #define CENTAUR_1G_JEDEC_ID 0x0028
1255 #define PEGASUS_ORION_JEDEC_ID 0x0036
1256 #define PEGASUS_JEDEC_ID 0x0038
1257 #define THOR_JEDEC_ID 0x0012
1258 #define HELIOS_JEDEC_ID 0x0364
1259 #define ZEPHYR_JEDEC_ID 0x0577
1260 #define VIPER_JEDEC_ID 0x4838
1261 #define SATURN_JEDEC_ID 0x1004
1262 #define HORNET_JDEC_ID 0x2057706D
1263
1264 #define JEDEC_ID_MASK 0x0FFFF000
1265 #define JEDEC_ID_SHIFT 12
1266 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1267
1268 typedef struct { /* FireFly BIU registers */
1269 uint32_t hostAtt; /* See definitions for Host Attention
1270 register */
1271 uint32_t chipAtt; /* See definitions for Chip Attention
1272 register */
1273 uint32_t hostStatus; /* See definitions for Host Status register */
1274 uint32_t hostControl; /* See definitions for Host Control register */
1275 uint32_t buiConfig; /* See definitions for BIU configuration
1276 register */
1277 } FF_REGS;
1278
1279 /* IO Register size in bytes */
1280 #define FF_REG_AREA_SIZE 256
1281
1282 /* Host Attention Register */
1283
1284 #define HA_REG_OFFSET 0 /* Byte offset from register base address */
1285
1286 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1287 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1288 #define HA_R0ATT 0x00000008 /* Bit 3 */
1289 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1290 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1291 #define HA_R1ATT 0x00000080 /* Bit 7 */
1292 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1293 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1294 #define HA_R2ATT 0x00000800 /* Bit 11 */
1295 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1296 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1297 #define HA_R3ATT 0x00008000 /* Bit 15 */
1298 #define HA_LATT 0x20000000 /* Bit 29 */
1299 #define HA_MBATT 0x40000000 /* Bit 30 */
1300 #define HA_ERATT 0x80000000 /* Bit 31 */
1301
1302 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1303 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1304 #define HA_RXATT 0x00000008 /* Bit 3 */
1305 #define HA_RXMASK 0x0000000f
1306
1307 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1308 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1309 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1310 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1311
1312 #define HA_R0_POS 3
1313 #define HA_R1_POS 7
1314 #define HA_R2_POS 11
1315 #define HA_R3_POS 15
1316 #define HA_LE_POS 29
1317 #define HA_MB_POS 30
1318 #define HA_ER_POS 31
1319 /* Chip Attention Register */
1320
1321 #define CA_REG_OFFSET 4 /* Byte offset from register base address */
1322
1323 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1324 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1325 #define CA_R0ATT 0x00000008 /* Bit 3 */
1326 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1327 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1328 #define CA_R1ATT 0x00000080 /* Bit 7 */
1329 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1330 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1331 #define CA_R2ATT 0x00000800 /* Bit 11 */
1332 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1333 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1334 #define CA_R3ATT 0x00008000 /* Bit 15 */
1335 #define CA_MBATT 0x40000000 /* Bit 30 */
1336
1337 /* Host Status Register */
1338
1339 #define HS_REG_OFFSET 8 /* Byte offset from register base address */
1340
1341 #define HS_MBRDY 0x00400000 /* Bit 22 */
1342 #define HS_FFRDY 0x00800000 /* Bit 23 */
1343 #define HS_FFER8 0x01000000 /* Bit 24 */
1344 #define HS_FFER7 0x02000000 /* Bit 25 */
1345 #define HS_FFER6 0x04000000 /* Bit 26 */
1346 #define HS_FFER5 0x08000000 /* Bit 27 */
1347 #define HS_FFER4 0x10000000 /* Bit 28 */
1348 #define HS_FFER3 0x20000000 /* Bit 29 */
1349 #define HS_FFER2 0x40000000 /* Bit 30 */
1350 #define HS_FFER1 0x80000000 /* Bit 31 */
1351 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
1352 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
1353 #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */
1354 /* Host Control Register */
1355
1356 #define HC_REG_OFFSET 12 /* Byte offset from register base address */
1357
1358 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1359 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1360 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1361 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1362 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1363 #define HC_INITHBI 0x02000000 /* Bit 25 */
1364 #define HC_INITMB 0x04000000 /* Bit 26 */
1365 #define HC_INITFF 0x08000000 /* Bit 27 */
1366 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1367 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1368
1369 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1370 #define MSIX_DFLT_ID 0
1371 #define MSIX_RNG0_ID 0
1372 #define MSIX_RNG1_ID 1
1373 #define MSIX_RNG2_ID 2
1374 #define MSIX_RNG3_ID 3
1375
1376 #define MSIX_LINK_ID 4
1377 #define MSIX_MBOX_ID 5
1378
1379 #define MSIX_SPARE0_ID 6
1380 #define MSIX_SPARE1_ID 7
1381
1382 /* Mailbox Commands */
1383 #define MBX_SHUTDOWN 0x00 /* terminate testing */
1384 #define MBX_LOAD_SM 0x01
1385 #define MBX_READ_NV 0x02
1386 #define MBX_WRITE_NV 0x03
1387 #define MBX_RUN_BIU_DIAG 0x04
1388 #define MBX_INIT_LINK 0x05
1389 #define MBX_DOWN_LINK 0x06
1390 #define MBX_CONFIG_LINK 0x07
1391 #define MBX_CONFIG_RING 0x09
1392 #define MBX_RESET_RING 0x0A
1393 #define MBX_READ_CONFIG 0x0B
1394 #define MBX_READ_RCONFIG 0x0C
1395 #define MBX_READ_SPARM 0x0D
1396 #define MBX_READ_STATUS 0x0E
1397 #define MBX_READ_RPI 0x0F
1398 #define MBX_READ_XRI 0x10
1399 #define MBX_READ_REV 0x11
1400 #define MBX_READ_LNK_STAT 0x12
1401 #define MBX_REG_LOGIN 0x13
1402 #define MBX_UNREG_LOGIN 0x14
1403 #define MBX_CLEAR_LA 0x16
1404 #define MBX_DUMP_MEMORY 0x17
1405 #define MBX_DUMP_CONTEXT 0x18
1406 #define MBX_RUN_DIAGS 0x19
1407 #define MBX_RESTART 0x1A
1408 #define MBX_UPDATE_CFG 0x1B
1409 #define MBX_DOWN_LOAD 0x1C
1410 #define MBX_DEL_LD_ENTRY 0x1D
1411 #define MBX_RUN_PROGRAM 0x1E
1412 #define MBX_SET_MASK 0x20
1413 #define MBX_SET_VARIABLE 0x21
1414 #define MBX_UNREG_D_ID 0x23
1415 #define MBX_KILL_BOARD 0x24
1416 #define MBX_CONFIG_FARP 0x25
1417 #define MBX_BEACON 0x2A
1418 #define MBX_CONFIG_MSI 0x30
1419 #define MBX_HEARTBEAT 0x31
1420 #define MBX_WRITE_VPARMS 0x32
1421 #define MBX_ASYNCEVT_ENABLE 0x33
1422 #define MBX_READ_EVENT_LOG_STATUS 0x37
1423 #define MBX_READ_EVENT_LOG 0x38
1424 #define MBX_WRITE_EVENT_LOG 0x39
1425
1426 #define MBX_PORT_CAPABILITIES 0x3B
1427 #define MBX_PORT_IOV_CONTROL 0x3C
1428
1429 #define MBX_CONFIG_HBQ 0x7C
1430 #define MBX_LOAD_AREA 0x81
1431 #define MBX_RUN_BIU_DIAG64 0x84
1432 #define MBX_CONFIG_PORT 0x88
1433 #define MBX_READ_SPARM64 0x8D
1434 #define MBX_READ_RPI64 0x8F
1435 #define MBX_REG_LOGIN64 0x93
1436 #define MBX_READ_TOPOLOGY 0x95
1437 #define MBX_REG_VPI 0x96
1438 #define MBX_UNREG_VPI 0x97
1439
1440 #define MBX_WRITE_WWN 0x98
1441 #define MBX_SET_DEBUG 0x99
1442 #define MBX_LOAD_EXP_ROM 0x9C
1443 #define MBX_SLI4_CONFIG 0x9B
1444 #define MBX_SLI4_REQ_FTRS 0x9D
1445 #define MBX_MAX_CMDS 0x9E
1446 #define MBX_RESUME_RPI 0x9E
1447 #define MBX_SLI2_CMD_MASK 0x80
1448 #define MBX_REG_VFI 0x9F
1449 #define MBX_REG_FCFI 0xA0
1450 #define MBX_UNREG_VFI 0xA1
1451 #define MBX_UNREG_FCFI 0xA2
1452 #define MBX_INIT_VFI 0xA3
1453 #define MBX_INIT_VPI 0xA4
1454
1455 #define MBX_AUTH_PORT 0xF8
1456 #define MBX_SECURITY_MGMT 0xF9
1457
1458 /* IOCB Commands */
1459
1460 #define CMD_RCV_SEQUENCE_CX 0x01
1461 #define CMD_XMIT_SEQUENCE_CR 0x02
1462 #define CMD_XMIT_SEQUENCE_CX 0x03
1463 #define CMD_XMIT_BCAST_CN 0x04
1464 #define CMD_XMIT_BCAST_CX 0x05
1465 #define CMD_QUE_RING_BUF_CN 0x06
1466 #define CMD_QUE_XRI_BUF_CX 0x07
1467 #define CMD_IOCB_CONTINUE_CN 0x08
1468 #define CMD_RET_XRI_BUF_CX 0x09
1469 #define CMD_ELS_REQUEST_CR 0x0A
1470 #define CMD_ELS_REQUEST_CX 0x0B
1471 #define CMD_RCV_ELS_REQ_CX 0x0D
1472 #define CMD_ABORT_XRI_CN 0x0E
1473 #define CMD_ABORT_XRI_CX 0x0F
1474 #define CMD_CLOSE_XRI_CN 0x10
1475 #define CMD_CLOSE_XRI_CX 0x11
1476 #define CMD_CREATE_XRI_CR 0x12
1477 #define CMD_CREATE_XRI_CX 0x13
1478 #define CMD_GET_RPI_CN 0x14
1479 #define CMD_XMIT_ELS_RSP_CX 0x15
1480 #define CMD_GET_RPI_CR 0x16
1481 #define CMD_XRI_ABORTED_CX 0x17
1482 #define CMD_FCP_IWRITE_CR 0x18
1483 #define CMD_FCP_IWRITE_CX 0x19
1484 #define CMD_FCP_IREAD_CR 0x1A
1485 #define CMD_FCP_IREAD_CX 0x1B
1486 #define CMD_FCP_ICMND_CR 0x1C
1487 #define CMD_FCP_ICMND_CX 0x1D
1488 #define CMD_FCP_TSEND_CX 0x1F
1489 #define CMD_FCP_TRECEIVE_CX 0x21
1490 #define CMD_FCP_TRSP_CX 0x23
1491 #define CMD_FCP_AUTO_TRSP_CX 0x29
1492
1493 #define CMD_ADAPTER_MSG 0x20
1494 #define CMD_ADAPTER_DUMP 0x22
1495
1496 /* SLI_2 IOCB Command Set */
1497
1498 #define CMD_ASYNC_STATUS 0x7C
1499 #define CMD_RCV_SEQUENCE64_CX 0x81
1500 #define CMD_XMIT_SEQUENCE64_CR 0x82
1501 #define CMD_XMIT_SEQUENCE64_CX 0x83
1502 #define CMD_XMIT_BCAST64_CN 0x84
1503 #define CMD_XMIT_BCAST64_CX 0x85
1504 #define CMD_QUE_RING_BUF64_CN 0x86
1505 #define CMD_QUE_XRI_BUF64_CX 0x87
1506 #define CMD_IOCB_CONTINUE64_CN 0x88
1507 #define CMD_RET_XRI_BUF64_CX 0x89
1508 #define CMD_ELS_REQUEST64_CR 0x8A
1509 #define CMD_ELS_REQUEST64_CX 0x8B
1510 #define CMD_ABORT_MXRI64_CN 0x8C
1511 #define CMD_RCV_ELS_REQ64_CX 0x8D
1512 #define CMD_XMIT_ELS_RSP64_CX 0x95
1513 #define CMD_XMIT_BLS_RSP64_CX 0x97
1514 #define CMD_FCP_IWRITE64_CR 0x98
1515 #define CMD_FCP_IWRITE64_CX 0x99
1516 #define CMD_FCP_IREAD64_CR 0x9A
1517 #define CMD_FCP_IREAD64_CX 0x9B
1518 #define CMD_FCP_ICMND64_CR 0x9C
1519 #define CMD_FCP_ICMND64_CX 0x9D
1520 #define CMD_FCP_TSEND64_CX 0x9F
1521 #define CMD_FCP_TRECEIVE64_CX 0xA1
1522 #define CMD_FCP_TRSP64_CX 0xA3
1523
1524 #define CMD_QUE_XRI64_CX 0xB3
1525 #define CMD_IOCB_RCV_SEQ64_CX 0xB5
1526 #define CMD_IOCB_RCV_ELS64_CX 0xB7
1527 #define CMD_IOCB_RET_XRI64_CX 0xB9
1528 #define CMD_IOCB_RCV_CONT64_CX 0xBB
1529
1530 #define CMD_GEN_REQUEST64_CR 0xC2
1531 #define CMD_GEN_REQUEST64_CX 0xC3
1532
1533 /* Unhandled SLI-3 Commands */
1534 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
1535 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
1536 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
1537 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
1538 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
1539 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
1540 #define CMD_IOCB_RET_HBQE64_CN 0xCA
1541 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
1542 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
1543 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
1544 #define CMD_IOCB_LOGENTRY_CN 0x94
1545 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
1546
1547 /* Data Security SLI Commands */
1548 #define DSSCMD_IWRITE64_CR 0xF8
1549 #define DSSCMD_IWRITE64_CX 0xF9
1550 #define DSSCMD_IREAD64_CR 0xFA
1551 #define DSSCMD_IREAD64_CX 0xFB
1552
1553 #define CMD_MAX_IOCB_CMD 0xFB
1554 #define CMD_IOCB_MASK 0xff
1555
1556 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1557 iocb */
1558 #define LPFC_MAX_ADPTMSG 32 /* max msg data */
1559 /*
1560 * Define Status
1561 */
1562 #define MBX_SUCCESS 0
1563 #define MBXERR_NUM_RINGS 1
1564 #define MBXERR_NUM_IOCBS 2
1565 #define MBXERR_IOCBS_EXCEEDED 3
1566 #define MBXERR_BAD_RING_NUMBER 4
1567 #define MBXERR_MASK_ENTRIES_RANGE 5
1568 #define MBXERR_MASKS_EXCEEDED 6
1569 #define MBXERR_BAD_PROFILE 7
1570 #define MBXERR_BAD_DEF_CLASS 8
1571 #define MBXERR_BAD_MAX_RESPONDER 9
1572 #define MBXERR_BAD_MAX_ORIGINATOR 10
1573 #define MBXERR_RPI_REGISTERED 11
1574 #define MBXERR_RPI_FULL 12
1575 #define MBXERR_NO_RESOURCES 13
1576 #define MBXERR_BAD_RCV_LENGTH 14
1577 #define MBXERR_DMA_ERROR 15
1578 #define MBXERR_ERROR 16
1579 #define MBXERR_LINK_DOWN 0x33
1580 #define MBXERR_SEC_NO_PERMISSION 0xF02
1581 #define MBX_NOT_FINISHED 255
1582
1583 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1584 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1585
1586 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
1587
1588 /*
1589 * Begin Structure Definitions for Mailbox Commands
1590 */
1591
1592 typedef struct {
1593 #ifdef __BIG_ENDIAN_BITFIELD
1594 uint8_t tval;
1595 uint8_t tmask;
1596 uint8_t rval;
1597 uint8_t rmask;
1598 #else /* __LITTLE_ENDIAN_BITFIELD */
1599 uint8_t rmask;
1600 uint8_t rval;
1601 uint8_t tmask;
1602 uint8_t tval;
1603 #endif
1604 } RR_REG;
1605
1606 struct ulp_bde {
1607 uint32_t bdeAddress;
1608 #ifdef __BIG_ENDIAN_BITFIELD
1609 uint32_t bdeReserved:4;
1610 uint32_t bdeAddrHigh:4;
1611 uint32_t bdeSize:24;
1612 #else /* __LITTLE_ENDIAN_BITFIELD */
1613 uint32_t bdeSize:24;
1614 uint32_t bdeAddrHigh:4;
1615 uint32_t bdeReserved:4;
1616 #endif
1617 };
1618
1619 typedef struct ULP_BDL { /* SLI-2 */
1620 #ifdef __BIG_ENDIAN_BITFIELD
1621 uint32_t bdeFlags:8; /* BDL Flags */
1622 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1623 #else /* __LITTLE_ENDIAN_BITFIELD */
1624 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1625 uint32_t bdeFlags:8; /* BDL Flags */
1626 #endif
1627
1628 uint32_t addrLow; /* Address 0:31 */
1629 uint32_t addrHigh; /* Address 32:63 */
1630 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
1631 } ULP_BDL;
1632
1633 /*
1634 * BlockGuard Definitions
1635 */
1636
1637 enum lpfc_protgrp_type {
1638 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */
1639 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */
1640 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */
1641 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */
1642 };
1643
1644 /* PDE Descriptors */
1645 #define LPFC_PDE5_DESCRIPTOR 0x85
1646 #define LPFC_PDE6_DESCRIPTOR 0x86
1647 #define LPFC_PDE7_DESCRIPTOR 0x87
1648
1649 /* BlockGuard Opcodes */
1650 #define BG_OP_IN_NODIF_OUT_CRC 0x0
1651 #define BG_OP_IN_CRC_OUT_NODIF 0x1
1652 #define BG_OP_IN_NODIF_OUT_CSUM 0x2
1653 #define BG_OP_IN_CSUM_OUT_NODIF 0x3
1654 #define BG_OP_IN_CRC_OUT_CRC 0x4
1655 #define BG_OP_IN_CSUM_OUT_CSUM 0x5
1656 #define BG_OP_IN_CRC_OUT_CSUM 0x6
1657 #define BG_OP_IN_CSUM_OUT_CRC 0x7
1658
1659 struct lpfc_pde5 {
1660 uint32_t word0;
1661 #define pde5_type_SHIFT 24
1662 #define pde5_type_MASK 0x000000ff
1663 #define pde5_type_WORD word0
1664 #define pde5_rsvd0_SHIFT 0
1665 #define pde5_rsvd0_MASK 0x00ffffff
1666 #define pde5_rsvd0_WORD word0
1667 uint32_t reftag; /* Reference Tag Value */
1668 uint32_t reftagtr; /* Reference Tag Translation Value */
1669 };
1670
1671 struct lpfc_pde6 {
1672 uint32_t word0;
1673 #define pde6_type_SHIFT 24
1674 #define pde6_type_MASK 0x000000ff
1675 #define pde6_type_WORD word0
1676 #define pde6_rsvd0_SHIFT 0
1677 #define pde6_rsvd0_MASK 0x00ffffff
1678 #define pde6_rsvd0_WORD word0
1679 uint32_t word1;
1680 #define pde6_rsvd1_SHIFT 26
1681 #define pde6_rsvd1_MASK 0x0000003f
1682 #define pde6_rsvd1_WORD word1
1683 #define pde6_na_SHIFT 25
1684 #define pde6_na_MASK 0x00000001
1685 #define pde6_na_WORD word1
1686 #define pde6_rsvd2_SHIFT 16
1687 #define pde6_rsvd2_MASK 0x000001FF
1688 #define pde6_rsvd2_WORD word1
1689 #define pde6_apptagtr_SHIFT 0
1690 #define pde6_apptagtr_MASK 0x0000ffff
1691 #define pde6_apptagtr_WORD word1
1692 uint32_t word2;
1693 #define pde6_optx_SHIFT 28
1694 #define pde6_optx_MASK 0x0000000f
1695 #define pde6_optx_WORD word2
1696 #define pde6_oprx_SHIFT 24
1697 #define pde6_oprx_MASK 0x0000000f
1698 #define pde6_oprx_WORD word2
1699 #define pde6_nr_SHIFT 23
1700 #define pde6_nr_MASK 0x00000001
1701 #define pde6_nr_WORD word2
1702 #define pde6_ce_SHIFT 22
1703 #define pde6_ce_MASK 0x00000001
1704 #define pde6_ce_WORD word2
1705 #define pde6_re_SHIFT 21
1706 #define pde6_re_MASK 0x00000001
1707 #define pde6_re_WORD word2
1708 #define pde6_ae_SHIFT 20
1709 #define pde6_ae_MASK 0x00000001
1710 #define pde6_ae_WORD word2
1711 #define pde6_ai_SHIFT 19
1712 #define pde6_ai_MASK 0x00000001
1713 #define pde6_ai_WORD word2
1714 #define pde6_bs_SHIFT 16
1715 #define pde6_bs_MASK 0x00000007
1716 #define pde6_bs_WORD word2
1717 #define pde6_apptagval_SHIFT 0
1718 #define pde6_apptagval_MASK 0x0000ffff
1719 #define pde6_apptagval_WORD word2
1720 };
1721
1722 struct lpfc_pde7 {
1723 uint32_t word0;
1724 #define pde7_type_SHIFT 24
1725 #define pde7_type_MASK 0x000000ff
1726 #define pde7_type_WORD word0
1727 #define pde7_rsvd0_SHIFT 0
1728 #define pde7_rsvd0_MASK 0x00ffffff
1729 #define pde7_rsvd0_WORD word0
1730 uint32_t addrHigh;
1731 uint32_t addrLow;
1732 };
1733
1734 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
1735
1736 typedef struct {
1737 #ifdef __BIG_ENDIAN_BITFIELD
1738 uint32_t rsvd2:25;
1739 uint32_t acknowledgment:1;
1740 uint32_t version:1;
1741 uint32_t erase_or_prog:1;
1742 uint32_t update_flash:1;
1743 uint32_t update_ram:1;
1744 uint32_t method:1;
1745 uint32_t load_cmplt:1;
1746 #else /* __LITTLE_ENDIAN_BITFIELD */
1747 uint32_t load_cmplt:1;
1748 uint32_t method:1;
1749 uint32_t update_ram:1;
1750 uint32_t update_flash:1;
1751 uint32_t erase_or_prog:1;
1752 uint32_t version:1;
1753 uint32_t acknowledgment:1;
1754 uint32_t rsvd2:25;
1755 #endif
1756
1757 uint32_t dl_to_adr_low;
1758 uint32_t dl_to_adr_high;
1759 uint32_t dl_len;
1760 union {
1761 uint32_t dl_from_mbx_offset;
1762 struct ulp_bde dl_from_bde;
1763 struct ulp_bde64 dl_from_bde64;
1764 } un;
1765
1766 } LOAD_SM_VAR;
1767
1768 /* Structure for MB Command READ_NVPARM (02) */
1769
1770 typedef struct {
1771 uint32_t rsvd1[3]; /* Read as all one's */
1772 uint32_t rsvd2; /* Read as all zero's */
1773 uint32_t portname[2]; /* N_PORT name */
1774 uint32_t nodename[2]; /* NODE name */
1775
1776 #ifdef __BIG_ENDIAN_BITFIELD
1777 uint32_t pref_DID:24;
1778 uint32_t hardAL_PA:8;
1779 #else /* __LITTLE_ENDIAN_BITFIELD */
1780 uint32_t hardAL_PA:8;
1781 uint32_t pref_DID:24;
1782 #endif
1783
1784 uint32_t rsvd3[21]; /* Read as all one's */
1785 } READ_NV_VAR;
1786
1787 /* Structure for MB Command WRITE_NVPARMS (03) */
1788
1789 typedef struct {
1790 uint32_t rsvd1[3]; /* Must be all one's */
1791 uint32_t rsvd2; /* Must be all zero's */
1792 uint32_t portname[2]; /* N_PORT name */
1793 uint32_t nodename[2]; /* NODE name */
1794
1795 #ifdef __BIG_ENDIAN_BITFIELD
1796 uint32_t pref_DID:24;
1797 uint32_t hardAL_PA:8;
1798 #else /* __LITTLE_ENDIAN_BITFIELD */
1799 uint32_t hardAL_PA:8;
1800 uint32_t pref_DID:24;
1801 #endif
1802
1803 uint32_t rsvd3[21]; /* Must be all one's */
1804 } WRITE_NV_VAR;
1805
1806 /* Structure for MB Command RUN_BIU_DIAG (04) */
1807 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
1808
1809 typedef struct {
1810 uint32_t rsvd1;
1811 union {
1812 struct {
1813 struct ulp_bde xmit_bde;
1814 struct ulp_bde rcv_bde;
1815 } s1;
1816 struct {
1817 struct ulp_bde64 xmit_bde64;
1818 struct ulp_bde64 rcv_bde64;
1819 } s2;
1820 } un;
1821 } BIU_DIAG_VAR;
1822
1823 /* Structure for MB command READ_EVENT_LOG (0x38) */
1824 struct READ_EVENT_LOG_VAR {
1825 uint32_t word1;
1826 #define lpfc_event_log_SHIFT 29
1827 #define lpfc_event_log_MASK 0x00000001
1828 #define lpfc_event_log_WORD word1
1829 #define USE_MAILBOX_RESPONSE 1
1830 uint32_t offset;
1831 struct ulp_bde64 rcv_bde64;
1832 };
1833
1834 /* Structure for MB Command INIT_LINK (05) */
1835
1836 typedef struct {
1837 #ifdef __BIG_ENDIAN_BITFIELD
1838 uint32_t rsvd1:24;
1839 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1840 #else /* __LITTLE_ENDIAN_BITFIELD */
1841 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1842 uint32_t rsvd1:24;
1843 #endif
1844
1845 #ifdef __BIG_ENDIAN_BITFIELD
1846 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1847 uint8_t rsvd2;
1848 uint16_t link_flags;
1849 #else /* __LITTLE_ENDIAN_BITFIELD */
1850 uint16_t link_flags;
1851 uint8_t rsvd2;
1852 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1853 #endif
1854
1855 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
1856 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
1857 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
1858 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
1859 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
1860 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
1861 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
1862
1863 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
1864 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
1865 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
1866
1867 uint32_t link_speed;
1868 #define LINK_SPEED_AUTO 0x0 /* Auto selection */
1869 #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */
1870 #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */
1871 #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */
1872 #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */
1873 #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */
1874 #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */
1875
1876 } INIT_LINK_VAR;
1877
1878 /* Structure for MB Command DOWN_LINK (06) */
1879
1880 typedef struct {
1881 uint32_t rsvd1;
1882 } DOWN_LINK_VAR;
1883
1884 /* Structure for MB Command CONFIG_LINK (07) */
1885
1886 typedef struct {
1887 #ifdef __BIG_ENDIAN_BITFIELD
1888 uint32_t cr:1;
1889 uint32_t ci:1;
1890 uint32_t cr_delay:6;
1891 uint32_t cr_count:8;
1892 uint32_t rsvd1:8;
1893 uint32_t MaxBBC:8;
1894 #else /* __LITTLE_ENDIAN_BITFIELD */
1895 uint32_t MaxBBC:8;
1896 uint32_t rsvd1:8;
1897 uint32_t cr_count:8;
1898 uint32_t cr_delay:6;
1899 uint32_t ci:1;
1900 uint32_t cr:1;
1901 #endif
1902
1903 uint32_t myId;
1904 uint32_t rsvd2;
1905 uint32_t edtov;
1906 uint32_t arbtov;
1907 uint32_t ratov;
1908 uint32_t rttov;
1909 uint32_t altov;
1910 uint32_t crtov;
1911 uint32_t citov;
1912 #ifdef __BIG_ENDIAN_BITFIELD
1913 uint32_t rrq_enable:1;
1914 uint32_t rrq_immed:1;
1915 uint32_t rsvd4:29;
1916 uint32_t ack0_enable:1;
1917 #else /* __LITTLE_ENDIAN_BITFIELD */
1918 uint32_t ack0_enable:1;
1919 uint32_t rsvd4:29;
1920 uint32_t rrq_immed:1;
1921 uint32_t rrq_enable:1;
1922 #endif
1923 } CONFIG_LINK;
1924
1925 /* Structure for MB Command PART_SLIM (08)
1926 * will be removed since SLI1 is no longer supported!
1927 */
1928 typedef struct {
1929 #ifdef __BIG_ENDIAN_BITFIELD
1930 uint16_t offCiocb;
1931 uint16_t numCiocb;
1932 uint16_t offRiocb;
1933 uint16_t numRiocb;
1934 #else /* __LITTLE_ENDIAN_BITFIELD */
1935 uint16_t numCiocb;
1936 uint16_t offCiocb;
1937 uint16_t numRiocb;
1938 uint16_t offRiocb;
1939 #endif
1940 } RING_DEF;
1941
1942 typedef struct {
1943 #ifdef __BIG_ENDIAN_BITFIELD
1944 uint32_t unused1:24;
1945 uint32_t numRing:8;
1946 #else /* __LITTLE_ENDIAN_BITFIELD */
1947 uint32_t numRing:8;
1948 uint32_t unused1:24;
1949 #endif
1950
1951 RING_DEF ringdef[4];
1952 uint32_t hbainit;
1953 } PART_SLIM_VAR;
1954
1955 /* Structure for MB Command CONFIG_RING (09) */
1956
1957 typedef struct {
1958 #ifdef __BIG_ENDIAN_BITFIELD
1959 uint32_t unused2:6;
1960 uint32_t recvSeq:1;
1961 uint32_t recvNotify:1;
1962 uint32_t numMask:8;
1963 uint32_t profile:8;
1964 uint32_t unused1:4;
1965 uint32_t ring:4;
1966 #else /* __LITTLE_ENDIAN_BITFIELD */
1967 uint32_t ring:4;
1968 uint32_t unused1:4;
1969 uint32_t profile:8;
1970 uint32_t numMask:8;
1971 uint32_t recvNotify:1;
1972 uint32_t recvSeq:1;
1973 uint32_t unused2:6;
1974 #endif
1975
1976 #ifdef __BIG_ENDIAN_BITFIELD
1977 uint16_t maxRespXchg;
1978 uint16_t maxOrigXchg;
1979 #else /* __LITTLE_ENDIAN_BITFIELD */
1980 uint16_t maxOrigXchg;
1981 uint16_t maxRespXchg;
1982 #endif
1983
1984 RR_REG rrRegs[6];
1985 } CONFIG_RING_VAR;
1986
1987 /* Structure for MB Command RESET_RING (10) */
1988
1989 typedef struct {
1990 uint32_t ring_no;
1991 } RESET_RING_VAR;
1992
1993 /* Structure for MB Command READ_CONFIG (11) */
1994
1995 typedef struct {
1996 #ifdef __BIG_ENDIAN_BITFIELD
1997 uint32_t cr:1;
1998 uint32_t ci:1;
1999 uint32_t cr_delay:6;
2000 uint32_t cr_count:8;
2001 uint32_t InitBBC:8;
2002 uint32_t MaxBBC:8;
2003 #else /* __LITTLE_ENDIAN_BITFIELD */
2004 uint32_t MaxBBC:8;
2005 uint32_t InitBBC:8;
2006 uint32_t cr_count:8;
2007 uint32_t cr_delay:6;
2008 uint32_t ci:1;
2009 uint32_t cr:1;
2010 #endif
2011
2012 #ifdef __BIG_ENDIAN_BITFIELD
2013 uint32_t topology:8;
2014 uint32_t myDid:24;
2015 #else /* __LITTLE_ENDIAN_BITFIELD */
2016 uint32_t myDid:24;
2017 uint32_t topology:8;
2018 #endif
2019
2020 /* Defines for topology (defined previously) */
2021 #ifdef __BIG_ENDIAN_BITFIELD
2022 uint32_t AR:1;
2023 uint32_t IR:1;
2024 uint32_t rsvd1:29;
2025 uint32_t ack0:1;
2026 #else /* __LITTLE_ENDIAN_BITFIELD */
2027 uint32_t ack0:1;
2028 uint32_t rsvd1:29;
2029 uint32_t IR:1;
2030 uint32_t AR:1;
2031 #endif
2032
2033 uint32_t edtov;
2034 uint32_t arbtov;
2035 uint32_t ratov;
2036 uint32_t rttov;
2037 uint32_t altov;
2038 uint32_t lmt;
2039 #define LMT_RESERVED 0x000 /* Not used */
2040 #define LMT_1Gb 0x004
2041 #define LMT_2Gb 0x008
2042 #define LMT_4Gb 0x040
2043 #define LMT_8Gb 0x080
2044 #define LMT_10Gb 0x100
2045 #define LMT_16Gb 0x200
2046 uint32_t rsvd2;
2047 uint32_t rsvd3;
2048 uint32_t max_xri;
2049 uint32_t max_iocb;
2050 uint32_t max_rpi;
2051 uint32_t avail_xri;
2052 uint32_t avail_iocb;
2053 uint32_t avail_rpi;
2054 uint32_t max_vpi;
2055 uint32_t rsvd4;
2056 uint32_t rsvd5;
2057 uint32_t avail_vpi;
2058 } READ_CONFIG_VAR;
2059
2060 /* Structure for MB Command READ_RCONFIG (12) */
2061
2062 typedef struct {
2063 #ifdef __BIG_ENDIAN_BITFIELD
2064 uint32_t rsvd2:7;
2065 uint32_t recvNotify:1;
2066 uint32_t numMask:8;
2067 uint32_t profile:8;
2068 uint32_t rsvd1:4;
2069 uint32_t ring:4;
2070 #else /* __LITTLE_ENDIAN_BITFIELD */
2071 uint32_t ring:4;
2072 uint32_t rsvd1:4;
2073 uint32_t profile:8;
2074 uint32_t numMask:8;
2075 uint32_t recvNotify:1;
2076 uint32_t rsvd2:7;
2077 #endif
2078
2079 #ifdef __BIG_ENDIAN_BITFIELD
2080 uint16_t maxResp;
2081 uint16_t maxOrig;
2082 #else /* __LITTLE_ENDIAN_BITFIELD */
2083 uint16_t maxOrig;
2084 uint16_t maxResp;
2085 #endif
2086
2087 RR_REG rrRegs[6];
2088
2089 #ifdef __BIG_ENDIAN_BITFIELD
2090 uint16_t cmdRingOffset;
2091 uint16_t cmdEntryCnt;
2092 uint16_t rspRingOffset;
2093 uint16_t rspEntryCnt;
2094 uint16_t nextCmdOffset;
2095 uint16_t rsvd3;
2096 uint16_t nextRspOffset;
2097 uint16_t rsvd4;
2098 #else /* __LITTLE_ENDIAN_BITFIELD */
2099 uint16_t cmdEntryCnt;
2100 uint16_t cmdRingOffset;
2101 uint16_t rspEntryCnt;
2102 uint16_t rspRingOffset;
2103 uint16_t rsvd3;
2104 uint16_t nextCmdOffset;
2105 uint16_t rsvd4;
2106 uint16_t nextRspOffset;
2107 #endif
2108 } READ_RCONF_VAR;
2109
2110 /* Structure for MB Command READ_SPARM (13) */
2111 /* Structure for MB Command READ_SPARM64 (0x8D) */
2112
2113 typedef struct {
2114 uint32_t rsvd1;
2115 uint32_t rsvd2;
2116 union {
2117 struct ulp_bde sp; /* This BDE points to struct serv_parm
2118 structure */
2119 struct ulp_bde64 sp64;
2120 } un;
2121 #ifdef __BIG_ENDIAN_BITFIELD
2122 uint16_t rsvd3;
2123 uint16_t vpi;
2124 #else /* __LITTLE_ENDIAN_BITFIELD */
2125 uint16_t vpi;
2126 uint16_t rsvd3;
2127 #endif
2128 } READ_SPARM_VAR;
2129
2130 /* Structure for MB Command READ_STATUS (14) */
2131
2132 typedef struct {
2133 #ifdef __BIG_ENDIAN_BITFIELD
2134 uint32_t rsvd1:31;
2135 uint32_t clrCounters:1;
2136 uint16_t activeXriCnt;
2137 uint16_t activeRpiCnt;
2138 #else /* __LITTLE_ENDIAN_BITFIELD */
2139 uint32_t clrCounters:1;
2140 uint32_t rsvd1:31;
2141 uint16_t activeRpiCnt;
2142 uint16_t activeXriCnt;
2143 #endif
2144
2145 uint32_t xmitByteCnt;
2146 uint32_t rcvByteCnt;
2147 uint32_t xmitFrameCnt;
2148 uint32_t rcvFrameCnt;
2149 uint32_t xmitSeqCnt;
2150 uint32_t rcvSeqCnt;
2151 uint32_t totalOrigExchanges;
2152 uint32_t totalRespExchanges;
2153 uint32_t rcvPbsyCnt;
2154 uint32_t rcvFbsyCnt;
2155 } READ_STATUS_VAR;
2156
2157 /* Structure for MB Command READ_RPI (15) */
2158 /* Structure for MB Command READ_RPI64 (0x8F) */
2159
2160 typedef struct {
2161 #ifdef __BIG_ENDIAN_BITFIELD
2162 uint16_t nextRpi;
2163 uint16_t reqRpi;
2164 uint32_t rsvd2:8;
2165 uint32_t DID:24;
2166 #else /* __LITTLE_ENDIAN_BITFIELD */
2167 uint16_t reqRpi;
2168 uint16_t nextRpi;
2169 uint32_t DID:24;
2170 uint32_t rsvd2:8;
2171 #endif
2172
2173 union {
2174 struct ulp_bde sp;
2175 struct ulp_bde64 sp64;
2176 } un;
2177
2178 } READ_RPI_VAR;
2179
2180 /* Structure for MB Command READ_XRI (16) */
2181
2182 typedef struct {
2183 #ifdef __BIG_ENDIAN_BITFIELD
2184 uint16_t nextXri;
2185 uint16_t reqXri;
2186 uint16_t rsvd1;
2187 uint16_t rpi;
2188 uint32_t rsvd2:8;
2189 uint32_t DID:24;
2190 uint32_t rsvd3:8;
2191 uint32_t SID:24;
2192 uint32_t rsvd4;
2193 uint8_t seqId;
2194 uint8_t rsvd5;
2195 uint16_t seqCount;
2196 uint16_t oxId;
2197 uint16_t rxId;
2198 uint32_t rsvd6:30;
2199 uint32_t si:1;
2200 uint32_t exchOrig:1;
2201 #else /* __LITTLE_ENDIAN_BITFIELD */
2202 uint16_t reqXri;
2203 uint16_t nextXri;
2204 uint16_t rpi;
2205 uint16_t rsvd1;
2206 uint32_t DID:24;
2207 uint32_t rsvd2:8;
2208 uint32_t SID:24;
2209 uint32_t rsvd3:8;
2210 uint32_t rsvd4;
2211 uint16_t seqCount;
2212 uint8_t rsvd5;
2213 uint8_t seqId;
2214 uint16_t rxId;
2215 uint16_t oxId;
2216 uint32_t exchOrig:1;
2217 uint32_t si:1;
2218 uint32_t rsvd6:30;
2219 #endif
2220 } READ_XRI_VAR;
2221
2222 /* Structure for MB Command READ_REV (17) */
2223
2224 typedef struct {
2225 #ifdef __BIG_ENDIAN_BITFIELD
2226 uint32_t cv:1;
2227 uint32_t rr:1;
2228 uint32_t rsvd2:2;
2229 uint32_t v3req:1;
2230 uint32_t v3rsp:1;
2231 uint32_t rsvd1:25;
2232 uint32_t rv:1;
2233 #else /* __LITTLE_ENDIAN_BITFIELD */
2234 uint32_t rv:1;
2235 uint32_t rsvd1:25;
2236 uint32_t v3rsp:1;
2237 uint32_t v3req:1;
2238 uint32_t rsvd2:2;
2239 uint32_t rr:1;
2240 uint32_t cv:1;
2241 #endif
2242
2243 uint32_t biuRev;
2244 uint32_t smRev;
2245 union {
2246 uint32_t smFwRev;
2247 struct {
2248 #ifdef __BIG_ENDIAN_BITFIELD
2249 uint8_t ProgType;
2250 uint8_t ProgId;
2251 uint16_t ProgVer:4;
2252 uint16_t ProgRev:4;
2253 uint16_t ProgFixLvl:2;
2254 uint16_t ProgDistType:2;
2255 uint16_t DistCnt:4;
2256 #else /* __LITTLE_ENDIAN_BITFIELD */
2257 uint16_t DistCnt:4;
2258 uint16_t ProgDistType:2;
2259 uint16_t ProgFixLvl:2;
2260 uint16_t ProgRev:4;
2261 uint16_t ProgVer:4;
2262 uint8_t ProgId;
2263 uint8_t ProgType;
2264 #endif
2265
2266 } b;
2267 } un;
2268 uint32_t endecRev;
2269 #ifdef __BIG_ENDIAN_BITFIELD
2270 uint8_t feaLevelHigh;
2271 uint8_t feaLevelLow;
2272 uint8_t fcphHigh;
2273 uint8_t fcphLow;
2274 #else /* __LITTLE_ENDIAN_BITFIELD */
2275 uint8_t fcphLow;
2276 uint8_t fcphHigh;
2277 uint8_t feaLevelLow;
2278 uint8_t feaLevelHigh;
2279 #endif
2280
2281 uint32_t postKernRev;
2282 uint32_t opFwRev;
2283 uint8_t opFwName[16];
2284 uint32_t sli1FwRev;
2285 uint8_t sli1FwName[16];
2286 uint32_t sli2FwRev;
2287 uint8_t sli2FwName[16];
2288 uint32_t sli3Feat;
2289 uint32_t RandomData[6];
2290 } READ_REV_VAR;
2291
2292 /* Structure for MB Command READ_LINK_STAT (18) */
2293
2294 typedef struct {
2295 uint32_t rsvd1;
2296 uint32_t linkFailureCnt;
2297 uint32_t lossSyncCnt;
2298
2299 uint32_t lossSignalCnt;
2300 uint32_t primSeqErrCnt;
2301 uint32_t invalidXmitWord;
2302 uint32_t crcCnt;
2303 uint32_t primSeqTimeout;
2304 uint32_t elasticOverrun;
2305 uint32_t arbTimeout;
2306 } READ_LNK_VAR;
2307
2308 /* Structure for MB Command REG_LOGIN (19) */
2309 /* Structure for MB Command REG_LOGIN64 (0x93) */
2310
2311 typedef struct {
2312 #ifdef __BIG_ENDIAN_BITFIELD
2313 uint16_t rsvd1;
2314 uint16_t rpi;
2315 uint32_t rsvd2:8;
2316 uint32_t did:24;
2317 #else /* __LITTLE_ENDIAN_BITFIELD */
2318 uint16_t rpi;
2319 uint16_t rsvd1;
2320 uint32_t did:24;
2321 uint32_t rsvd2:8;
2322 #endif
2323
2324 union {
2325 struct ulp_bde sp;
2326 struct ulp_bde64 sp64;
2327 } un;
2328
2329 #ifdef __BIG_ENDIAN_BITFIELD
2330 uint16_t rsvd6;
2331 uint16_t vpi;
2332 #else /* __LITTLE_ENDIAN_BITFIELD */
2333 uint16_t vpi;
2334 uint16_t rsvd6;
2335 #endif
2336
2337 } REG_LOGIN_VAR;
2338
2339 /* Word 30 contents for REG_LOGIN */
2340 typedef union {
2341 struct {
2342 #ifdef __BIG_ENDIAN_BITFIELD
2343 uint16_t rsvd1:12;
2344 uint16_t wd30_class:4;
2345 uint16_t xri;
2346 #else /* __LITTLE_ENDIAN_BITFIELD */
2347 uint16_t xri;
2348 uint16_t wd30_class:4;
2349 uint16_t rsvd1:12;
2350 #endif
2351 } f;
2352 uint32_t word;
2353 } REG_WD30;
2354
2355 /* Structure for MB Command UNREG_LOGIN (20) */
2356
2357 typedef struct {
2358 #ifdef __BIG_ENDIAN_BITFIELD
2359 uint16_t rsvd1;
2360 uint16_t rpi;
2361 uint32_t rsvd2;
2362 uint32_t rsvd3;
2363 uint32_t rsvd4;
2364 uint32_t rsvd5;
2365 uint16_t rsvd6;
2366 uint16_t vpi;
2367 #else /* __LITTLE_ENDIAN_BITFIELD */
2368 uint16_t rpi;
2369 uint16_t rsvd1;
2370 uint32_t rsvd2;
2371 uint32_t rsvd3;
2372 uint32_t rsvd4;
2373 uint32_t rsvd5;
2374 uint16_t vpi;
2375 uint16_t rsvd6;
2376 #endif
2377 } UNREG_LOGIN_VAR;
2378
2379 /* Structure for MB Command REG_VPI (0x96) */
2380 typedef struct {
2381 #ifdef __BIG_ENDIAN_BITFIELD
2382 uint32_t rsvd1;
2383 uint32_t rsvd2:7;
2384 uint32_t upd:1;
2385 uint32_t sid:24;
2386 uint32_t wwn[2];
2387 uint32_t rsvd5;
2388 uint16_t vfi;
2389 uint16_t vpi;
2390 #else /* __LITTLE_ENDIAN */
2391 uint32_t rsvd1;
2392 uint32_t sid:24;
2393 uint32_t upd:1;
2394 uint32_t rsvd2:7;
2395 uint32_t wwn[2];
2396 uint32_t rsvd5;
2397 uint16_t vpi;
2398 uint16_t vfi;
2399 #endif
2400 } REG_VPI_VAR;
2401
2402 /* Structure for MB Command UNREG_VPI (0x97) */
2403 typedef struct {
2404 uint32_t rsvd1;
2405 #ifdef __BIG_ENDIAN_BITFIELD
2406 uint16_t rsvd2;
2407 uint16_t sli4_vpi;
2408 #else /* __LITTLE_ENDIAN */
2409 uint16_t sli4_vpi;
2410 uint16_t rsvd2;
2411 #endif
2412 uint32_t rsvd3;
2413 uint32_t rsvd4;
2414 uint32_t rsvd5;
2415 #ifdef __BIG_ENDIAN_BITFIELD
2416 uint16_t rsvd6;
2417 uint16_t vpi;
2418 #else /* __LITTLE_ENDIAN */
2419 uint16_t vpi;
2420 uint16_t rsvd6;
2421 #endif
2422 } UNREG_VPI_VAR;
2423
2424 /* Structure for MB Command UNREG_D_ID (0x23) */
2425
2426 typedef struct {
2427 uint32_t did;
2428 uint32_t rsvd2;
2429 uint32_t rsvd3;
2430 uint32_t rsvd4;
2431 uint32_t rsvd5;
2432 #ifdef __BIG_ENDIAN_BITFIELD
2433 uint16_t rsvd6;
2434 uint16_t vpi;
2435 #else
2436 uint16_t vpi;
2437 uint16_t rsvd6;
2438 #endif
2439 } UNREG_D_ID_VAR;
2440
2441 /* Structure for MB Command READ_TOPOLOGY (0x95) */
2442 struct lpfc_mbx_read_top {
2443 uint32_t eventTag; /* Event tag */
2444 uint32_t word2;
2445 #define lpfc_mbx_read_top_fa_SHIFT 12
2446 #define lpfc_mbx_read_top_fa_MASK 0x00000001
2447 #define lpfc_mbx_read_top_fa_WORD word2
2448 #define lpfc_mbx_read_top_mm_SHIFT 11
2449 #define lpfc_mbx_read_top_mm_MASK 0x00000001
2450 #define lpfc_mbx_read_top_mm_WORD word2
2451 #define lpfc_mbx_read_top_pb_SHIFT 9
2452 #define lpfc_mbx_read_top_pb_MASK 0X00000001
2453 #define lpfc_mbx_read_top_pb_WORD word2
2454 #define lpfc_mbx_read_top_il_SHIFT 8
2455 #define lpfc_mbx_read_top_il_MASK 0x00000001
2456 #define lpfc_mbx_read_top_il_WORD word2
2457 #define lpfc_mbx_read_top_att_type_SHIFT 0
2458 #define lpfc_mbx_read_top_att_type_MASK 0x000000FF
2459 #define lpfc_mbx_read_top_att_type_WORD word2
2460 #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */
2461 #define LPFC_ATT_LINK_UP 0x01 /* Link is up */
2462 #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */
2463 uint32_t word3;
2464 #define lpfc_mbx_read_top_alpa_granted_SHIFT 24
2465 #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF
2466 #define lpfc_mbx_read_top_alpa_granted_WORD word3
2467 #define lpfc_mbx_read_top_lip_alps_SHIFT 16
2468 #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF
2469 #define lpfc_mbx_read_top_lip_alps_WORD word3
2470 #define lpfc_mbx_read_top_lip_type_SHIFT 8
2471 #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF
2472 #define lpfc_mbx_read_top_lip_type_WORD word3
2473 #define lpfc_mbx_read_top_topology_SHIFT 0
2474 #define lpfc_mbx_read_top_topology_MASK 0x000000FF
2475 #define lpfc_mbx_read_top_topology_WORD word3
2476 #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2477 #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
2478 #define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */
2479 /* store the LILP AL_PA position map into */
2480 struct ulp_bde64 lilpBde64;
2481 #define LPFC_ALPA_MAP_SIZE 128
2482 uint32_t word7;
2483 #define lpfc_mbx_read_top_ld_lu_SHIFT 31
2484 #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001
2485 #define lpfc_mbx_read_top_ld_lu_WORD word7
2486 #define lpfc_mbx_read_top_ld_tf_SHIFT 30
2487 #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001
2488 #define lpfc_mbx_read_top_ld_tf_WORD word7
2489 #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8
2490 #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF
2491 #define lpfc_mbx_read_top_ld_link_spd_WORD word7
2492 #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4
2493 #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F
2494 #define lpfc_mbx_read_top_ld_nl_port_WORD word7
2495 #define lpfc_mbx_read_top_ld_tx_SHIFT 2
2496 #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003
2497 #define lpfc_mbx_read_top_ld_tx_WORD word7
2498 #define lpfc_mbx_read_top_ld_rx_SHIFT 0
2499 #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003
2500 #define lpfc_mbx_read_top_ld_rx_WORD word7
2501 uint32_t word8;
2502 #define lpfc_mbx_read_top_lu_SHIFT 31
2503 #define lpfc_mbx_read_top_lu_MASK 0x00000001
2504 #define lpfc_mbx_read_top_lu_WORD word8
2505 #define lpfc_mbx_read_top_tf_SHIFT 30
2506 #define lpfc_mbx_read_top_tf_MASK 0x00000001
2507 #define lpfc_mbx_read_top_tf_WORD word8
2508 #define lpfc_mbx_read_top_link_spd_SHIFT 8
2509 #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF
2510 #define lpfc_mbx_read_top_link_spd_WORD word8
2511 #define lpfc_mbx_read_top_nl_port_SHIFT 4
2512 #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F
2513 #define lpfc_mbx_read_top_nl_port_WORD word8
2514 #define lpfc_mbx_read_top_tx_SHIFT 2
2515 #define lpfc_mbx_read_top_tx_MASK 0x00000003
2516 #define lpfc_mbx_read_top_tx_WORD word8
2517 #define lpfc_mbx_read_top_rx_SHIFT 0
2518 #define lpfc_mbx_read_top_rx_MASK 0x00000003
2519 #define lpfc_mbx_read_top_rx_WORD word8
2520 #define LPFC_LINK_SPEED_UNKNOWN 0x0
2521 #define LPFC_LINK_SPEED_1GHZ 0x04
2522 #define LPFC_LINK_SPEED_2GHZ 0x08
2523 #define LPFC_LINK_SPEED_4GHZ 0x10
2524 #define LPFC_LINK_SPEED_8GHZ 0x20
2525 #define LPFC_LINK_SPEED_10GHZ 0x40
2526 #define LPFC_LINK_SPEED_16GHZ 0x80
2527 };
2528
2529 /* Structure for MB Command CLEAR_LA (22) */
2530
2531 typedef struct {
2532 uint32_t eventTag; /* Event tag */
2533 uint32_t rsvd1;
2534 } CLEAR_LA_VAR;
2535
2536 /* Structure for MB Command DUMP */
2537
2538 typedef struct {
2539 #ifdef __BIG_ENDIAN_BITFIELD
2540 uint32_t rsvd:25;
2541 uint32_t ra:1;
2542 uint32_t co:1;
2543 uint32_t cv:1;
2544 uint32_t type:4;
2545 uint32_t entry_index:16;
2546 uint32_t region_id:16;
2547 #else /* __LITTLE_ENDIAN_BITFIELD */
2548 uint32_t type:4;
2549 uint32_t cv:1;
2550 uint32_t co:1;
2551 uint32_t ra:1;
2552 uint32_t rsvd:25;
2553 uint32_t region_id:16;
2554 uint32_t entry_index:16;
2555 #endif
2556
2557 uint32_t sli4_length;
2558 uint32_t word_cnt;
2559 uint32_t resp_offset;
2560 } DUMP_VAR;
2561
2562 #define DMP_MEM_REG 0x1
2563 #define DMP_NV_PARAMS 0x2
2564
2565 #define DMP_REGION_VPD 0xe
2566 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
2567 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
2568 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
2569
2570 #define DMP_REGION_VPORT 0x16 /* VPort info region */
2571 #define DMP_VPORT_REGION_SIZE 0x200
2572 #define DMP_MBOX_OFFSET_WORD 0x5
2573
2574 #define DMP_REGION_23 0x17 /* fcoe param and port state region */
2575 #define DMP_RGN23_SIZE 0x400
2576
2577 #define WAKE_UP_PARMS_REGION_ID 4
2578 #define WAKE_UP_PARMS_WORD_SIZE 15
2579
2580 struct vport_rec {
2581 uint8_t wwpn[8];
2582 uint8_t wwnn[8];
2583 };
2584
2585 #define VPORT_INFO_SIG 0x32324752
2586 #define VPORT_INFO_REV_MASK 0xff
2587 #define VPORT_INFO_REV 0x1
2588 #define MAX_STATIC_VPORT_COUNT 16
2589 struct static_vport_info {
2590 uint32_t signature;
2591 uint32_t rev;
2592 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT];
2593 uint32_t resvd[66];
2594 };
2595
2596 /* Option rom version structure */
2597 struct prog_id {
2598 #ifdef __BIG_ENDIAN_BITFIELD
2599 uint8_t type;
2600 uint8_t id;
2601 uint32_t ver:4; /* Major Version */
2602 uint32_t rev:4; /* Revision */
2603 uint32_t lev:2; /* Level */
2604 uint32_t dist:2; /* Dist Type */
2605 uint32_t num:4; /* number after dist type */
2606 #else /* __LITTLE_ENDIAN_BITFIELD */
2607 uint32_t num:4; /* number after dist type */
2608 uint32_t dist:2; /* Dist Type */
2609 uint32_t lev:2; /* Level */
2610 uint32_t rev:4; /* Revision */
2611 uint32_t ver:4; /* Major Version */
2612 uint8_t id;
2613 uint8_t type;
2614 #endif
2615 };
2616
2617 /* Structure for MB Command UPDATE_CFG (0x1B) */
2618
2619 struct update_cfg_var {
2620 #ifdef __BIG_ENDIAN_BITFIELD
2621 uint32_t rsvd2:16;
2622 uint32_t type:8;
2623 uint32_t rsvd:1;
2624 uint32_t ra:1;
2625 uint32_t co:1;
2626 uint32_t cv:1;
2627 uint32_t req:4;
2628 uint32_t entry_length:16;
2629 uint32_t region_id:16;
2630 #else /* __LITTLE_ENDIAN_BITFIELD */
2631 uint32_t req:4;
2632 uint32_t cv:1;
2633 uint32_t co:1;
2634 uint32_t ra:1;
2635 uint32_t rsvd:1;
2636 uint32_t type:8;
2637 uint32_t rsvd2:16;
2638 uint32_t region_id:16;
2639 uint32_t entry_length:16;
2640 #endif
2641
2642 uint32_t resp_info;
2643 uint32_t byte_cnt;
2644 uint32_t data_offset;
2645 };
2646
2647 struct hbq_mask {
2648 #ifdef __BIG_ENDIAN_BITFIELD
2649 uint8_t tmatch;
2650 uint8_t tmask;
2651 uint8_t rctlmatch;
2652 uint8_t rctlmask;
2653 #else /* __LITTLE_ENDIAN */
2654 uint8_t rctlmask;
2655 uint8_t rctlmatch;
2656 uint8_t tmask;
2657 uint8_t tmatch;
2658 #endif
2659 };
2660
2661
2662 /* Structure for MB Command CONFIG_HBQ (7c) */
2663
2664 struct config_hbq_var {
2665 #ifdef __BIG_ENDIAN_BITFIELD
2666 uint32_t rsvd1 :7;
2667 uint32_t recvNotify :1; /* Receive Notification */
2668 uint32_t numMask :8; /* # Mask Entries */
2669 uint32_t profile :8; /* Selection Profile */
2670 uint32_t rsvd2 :8;
2671 #else /* __LITTLE_ENDIAN */
2672 uint32_t rsvd2 :8;
2673 uint32_t profile :8; /* Selection Profile */
2674 uint32_t numMask :8; /* # Mask Entries */
2675 uint32_t recvNotify :1; /* Receive Notification */
2676 uint32_t rsvd1 :7;
2677 #endif
2678
2679 #ifdef __BIG_ENDIAN_BITFIELD
2680 uint32_t hbqId :16;
2681 uint32_t rsvd3 :12;
2682 uint32_t ringMask :4;
2683 #else /* __LITTLE_ENDIAN */
2684 uint32_t ringMask :4;
2685 uint32_t rsvd3 :12;
2686 uint32_t hbqId :16;
2687 #endif
2688
2689 #ifdef __BIG_ENDIAN_BITFIELD
2690 uint32_t entry_count :16;
2691 uint32_t rsvd4 :8;
2692 uint32_t headerLen :8;
2693 #else /* __LITTLE_ENDIAN */
2694 uint32_t headerLen :8;
2695 uint32_t rsvd4 :8;
2696 uint32_t entry_count :16;
2697 #endif
2698
2699 uint32_t hbqaddrLow;
2700 uint32_t hbqaddrHigh;
2701
2702 #ifdef __BIG_ENDIAN_BITFIELD
2703 uint32_t rsvd5 :31;
2704 uint32_t logEntry :1;
2705 #else /* __LITTLE_ENDIAN */
2706 uint32_t logEntry :1;
2707 uint32_t rsvd5 :31;
2708 #endif
2709
2710 uint32_t rsvd6; /* w7 */
2711 uint32_t rsvd7; /* w8 */
2712 uint32_t rsvd8; /* w9 */
2713
2714 struct hbq_mask hbqMasks[6];
2715
2716
2717 union {
2718 uint32_t allprofiles[12];
2719
2720 struct {
2721 #ifdef __BIG_ENDIAN_BITFIELD
2722 uint32_t seqlenoff :16;
2723 uint32_t maxlen :16;
2724 #else /* __LITTLE_ENDIAN */
2725 uint32_t maxlen :16;
2726 uint32_t seqlenoff :16;
2727 #endif
2728 #ifdef __BIG_ENDIAN_BITFIELD
2729 uint32_t rsvd1 :28;
2730 uint32_t seqlenbcnt :4;
2731 #else /* __LITTLE_ENDIAN */
2732 uint32_t seqlenbcnt :4;
2733 uint32_t rsvd1 :28;
2734 #endif
2735 uint32_t rsvd[10];
2736 } profile2;
2737
2738 struct {
2739 #ifdef __BIG_ENDIAN_BITFIELD
2740 uint32_t seqlenoff :16;
2741 uint32_t maxlen :16;
2742 #else /* __LITTLE_ENDIAN */
2743 uint32_t maxlen :16;
2744 uint32_t seqlenoff :16;
2745 #endif
2746 #ifdef __BIG_ENDIAN_BITFIELD
2747 uint32_t cmdcodeoff :28;
2748 uint32_t rsvd1 :12;
2749 uint32_t seqlenbcnt :4;
2750 #else /* __LITTLE_ENDIAN */
2751 uint32_t seqlenbcnt :4;
2752 uint32_t rsvd1 :12;
2753 uint32_t cmdcodeoff :28;
2754 #endif
2755 uint32_t cmdmatch[8];
2756
2757 uint32_t rsvd[2];
2758 } profile3;
2759
2760 struct {
2761 #ifdef __BIG_ENDIAN_BITFIELD
2762 uint32_t seqlenoff :16;
2763 uint32_t maxlen :16;
2764 #else /* __LITTLE_ENDIAN */
2765 uint32_t maxlen :16;
2766 uint32_t seqlenoff :16;
2767 #endif
2768 #ifdef __BIG_ENDIAN_BITFIELD
2769 uint32_t cmdcodeoff :28;
2770 uint32_t rsvd1 :12;
2771 uint32_t seqlenbcnt :4;
2772 #else /* __LITTLE_ENDIAN */
2773 uint32_t seqlenbcnt :4;
2774 uint32_t rsvd1 :12;
2775 uint32_t cmdcodeoff :28;
2776 #endif
2777 uint32_t cmdmatch[8];
2778
2779 uint32_t rsvd[2];
2780 } profile5;
2781
2782 } profiles;
2783
2784 };
2785
2786
2787
2788 /* Structure for MB Command CONFIG_PORT (0x88) */
2789 typedef struct {
2790 #ifdef __BIG_ENDIAN_BITFIELD
2791 uint32_t cBE : 1;
2792 uint32_t cET : 1;
2793 uint32_t cHpcb : 1;
2794 uint32_t cMA : 1;
2795 uint32_t sli_mode : 4;
2796 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2797 * config block */
2798 #else /* __LITTLE_ENDIAN */
2799 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2800 * config block */
2801 uint32_t sli_mode : 4;
2802 uint32_t cMA : 1;
2803 uint32_t cHpcb : 1;
2804 uint32_t cET : 1;
2805 uint32_t cBE : 1;
2806 #endif
2807
2808 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
2809 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
2810 uint32_t hbainit[5];
2811 #ifdef __BIG_ENDIAN_BITFIELD
2812 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
2813 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
2814 #else /* __LITTLE_ENDIAN */
2815 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
2816 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
2817 #endif
2818
2819 #ifdef __BIG_ENDIAN_BITFIELD
2820 uint32_t rsvd1 : 19; /* Reserved */
2821 uint32_t cdss : 1; /* Configure Data Security SLI */
2822 uint32_t rsvd2 : 3; /* Reserved */
2823 uint32_t cbg : 1; /* Configure BlockGuard */
2824 uint32_t cmv : 1; /* Configure Max VPIs */
2825 uint32_t ccrp : 1; /* Config Command Ring Polling */
2826 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2827 uint32_t chbs : 1; /* Cofigure Host Backing store */
2828 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2829 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2830 uint32_t cmx : 1; /* Configure Max XRIs */
2831 uint32_t cmr : 1; /* Configure Max RPIs */
2832 #else /* __LITTLE_ENDIAN */
2833 uint32_t cmr : 1; /* Configure Max RPIs */
2834 uint32_t cmx : 1; /* Configure Max XRIs */
2835 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2836 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2837 uint32_t chbs : 1; /* Cofigure Host Backing store */
2838 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2839 uint32_t ccrp : 1; /* Config Command Ring Polling */
2840 uint32_t cmv : 1; /* Configure Max VPIs */
2841 uint32_t cbg : 1; /* Configure BlockGuard */
2842 uint32_t rsvd2 : 3; /* Reserved */
2843 uint32_t cdss : 1; /* Configure Data Security SLI */
2844 uint32_t rsvd1 : 19; /* Reserved */
2845 #endif
2846 #ifdef __BIG_ENDIAN_BITFIELD
2847 uint32_t rsvd3 : 19; /* Reserved */
2848 uint32_t gdss : 1; /* Configure Data Security SLI */
2849 uint32_t rsvd4 : 3; /* Reserved */
2850 uint32_t gbg : 1; /* Grant BlockGuard */
2851 uint32_t gmv : 1; /* Grant Max VPIs */
2852 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2853 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2854 uint32_t ghbs : 1; /* Grant Host Backing Store */
2855 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2856 uint32_t gerbm : 1; /* Grant ERBM Request */
2857 uint32_t gmx : 1; /* Grant Max XRIs */
2858 uint32_t gmr : 1; /* Grant Max RPIs */
2859 #else /* __LITTLE_ENDIAN */
2860 uint32_t gmr : 1; /* Grant Max RPIs */
2861 uint32_t gmx : 1; /* Grant Max XRIs */
2862 uint32_t gerbm : 1; /* Grant ERBM Request */
2863 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2864 uint32_t ghbs : 1; /* Grant Host Backing Store */
2865 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2866 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2867 uint32_t gmv : 1; /* Grant Max VPIs */
2868 uint32_t gbg : 1; /* Grant BlockGuard */
2869 uint32_t rsvd4 : 3; /* Reserved */
2870 uint32_t gdss : 1; /* Configure Data Security SLI */
2871 uint32_t rsvd3 : 19; /* Reserved */
2872 #endif
2873
2874 #ifdef __BIG_ENDIAN_BITFIELD
2875 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2876 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2877 #else /* __LITTLE_ENDIAN */
2878 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2879 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2880 #endif
2881
2882 #ifdef __BIG_ENDIAN_BITFIELD
2883 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2884 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
2885 #else /* __LITTLE_ENDIAN */
2886 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
2887 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2888 #endif
2889
2890 uint32_t rsvd6; /* Reserved */
2891
2892 #ifdef __BIG_ENDIAN_BITFIELD
2893 uint32_t fips_rev : 3; /* FIPS Spec Revision */
2894 uint32_t fips_level : 4; /* FIPS Level */
2895 uint32_t sec_err : 9; /* security crypto error */
2896 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2897 #else /* __LITTLE_ENDIAN */
2898 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2899 uint32_t sec_err : 9; /* security crypto error */
2900 uint32_t fips_level : 4; /* FIPS Level */
2901 uint32_t fips_rev : 3; /* FIPS Spec Revision */
2902 #endif
2903
2904 } CONFIG_PORT_VAR;
2905
2906 /* Structure for MB Command CONFIG_MSI (0x30) */
2907 struct config_msi_var {
2908 #ifdef __BIG_ENDIAN_BITFIELD
2909 uint32_t dfltMsgNum:8; /* Default message number */
2910 uint32_t rsvd1:11; /* Reserved */
2911 uint32_t NID:5; /* Number of secondary attention IDs */
2912 uint32_t rsvd2:5; /* Reserved */
2913 uint32_t dfltPresent:1; /* Default message number present */
2914 uint32_t addFlag:1; /* Add association flag */
2915 uint32_t reportFlag:1; /* Report association flag */
2916 #else /* __LITTLE_ENDIAN_BITFIELD */
2917 uint32_t reportFlag:1; /* Report association flag */
2918 uint32_t addFlag:1; /* Add association flag */
2919 uint32_t dfltPresent:1; /* Default message number present */
2920 uint32_t rsvd2:5; /* Reserved */
2921 uint32_t NID:5; /* Number of secondary attention IDs */
2922 uint32_t rsvd1:11; /* Reserved */
2923 uint32_t dfltMsgNum:8; /* Default message number */
2924 #endif
2925 uint32_t attentionConditions[2];
2926 uint8_t attentionId[16];
2927 uint8_t messageNumberByHA[64];
2928 uint8_t messageNumberByID[16];
2929 uint32_t autoClearHA[2];
2930 #ifdef __BIG_ENDIAN_BITFIELD
2931 uint32_t rsvd3:16;
2932 uint32_t autoClearID:16;
2933 #else /* __LITTLE_ENDIAN_BITFIELD */
2934 uint32_t autoClearID:16;
2935 uint32_t rsvd3:16;
2936 #endif
2937 uint32_t rsvd4;
2938 };
2939
2940 /* SLI-2 Port Control Block */
2941
2942 /* SLIM POINTER */
2943 #define SLIMOFF 0x30 /* WORD */
2944
2945 typedef struct _SLI2_RDSC {
2946 uint32_t cmdEntries;
2947 uint32_t cmdAddrLow;
2948 uint32_t cmdAddrHigh;
2949
2950 uint32_t rspEntries;
2951 uint32_t rspAddrLow;
2952 uint32_t rspAddrHigh;
2953 } SLI2_RDSC;
2954
2955 typedef struct _PCB {
2956 #ifdef __BIG_ENDIAN_BITFIELD
2957 uint32_t type:8;
2958 #define TYPE_NATIVE_SLI2 0x01
2959 uint32_t feature:8;
2960 #define FEATURE_INITIAL_SLI2 0x01
2961 uint32_t rsvd:12;
2962 uint32_t maxRing:4;
2963 #else /* __LITTLE_ENDIAN_BITFIELD */
2964 uint32_t maxRing:4;
2965 uint32_t rsvd:12;
2966 uint32_t feature:8;
2967 #define FEATURE_INITIAL_SLI2 0x01
2968 uint32_t type:8;
2969 #define TYPE_NATIVE_SLI2 0x01
2970 #endif
2971
2972 uint32_t mailBoxSize;
2973 uint32_t mbAddrLow;
2974 uint32_t mbAddrHigh;
2975
2976 uint32_t hgpAddrLow;
2977 uint32_t hgpAddrHigh;
2978
2979 uint32_t pgpAddrLow;
2980 uint32_t pgpAddrHigh;
2981 SLI2_RDSC rdsc[MAX_RINGS];
2982 } PCB_t;
2983
2984 /* NEW_FEATURE */
2985 typedef struct {
2986 #ifdef __BIG_ENDIAN_BITFIELD
2987 uint32_t rsvd0:27;
2988 uint32_t discardFarp:1;
2989 uint32_t IPEnable:1;
2990 uint32_t nodeName:1;
2991 uint32_t portName:1;
2992 uint32_t filterEnable:1;
2993 #else /* __LITTLE_ENDIAN_BITFIELD */
2994 uint32_t filterEnable:1;
2995 uint32_t portName:1;
2996 uint32_t nodeName:1;
2997 uint32_t IPEnable:1;
2998 uint32_t discardFarp:1;
2999 uint32_t rsvd:27;
3000 #endif
3001
3002 uint8_t portname[8]; /* Used to be struct lpfc_name */
3003 uint8_t nodename[8];
3004 uint32_t rsvd1;
3005 uint32_t rsvd2;
3006 uint32_t rsvd3;
3007 uint32_t IPAddress;
3008 } CONFIG_FARP_VAR;
3009
3010 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3011
3012 typedef struct {
3013 #ifdef __BIG_ENDIAN_BITFIELD
3014 uint32_t rsvd:30;
3015 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3016 #else /* __LITTLE_ENDIAN */
3017 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3018 uint32_t rsvd:30;
3019 #endif
3020 } ASYNCEVT_ENABLE_VAR;
3021
3022 /* Union of all Mailbox Command types */
3023 #define MAILBOX_CMD_WSIZE 32
3024 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3025 /* ext_wsize times 4 bytes should not be greater than max xmit size */
3026 #define MAILBOX_EXT_WSIZE 512
3027 #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3028 #define MAILBOX_HBA_EXT_OFFSET 0x100
3029 /* max mbox xmit size is a page size for sysfs IO operations */
3030 #define MAILBOX_SYSFS_MAX 4096
3031
3032 typedef union {
3033 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3034 * feature/max ring number
3035 */
3036 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
3037 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
3038 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
3039 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
3040 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
3041 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
3042 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
3043 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
3044 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
3045 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
3046 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
3047 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
3048 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
3049 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
3050 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
3051 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
3052 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
3053 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
3054 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
3055 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
3056 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
3057 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
3058 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
3059 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
3060 * NEW_FEATURE
3061 */
3062 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
3063 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3064 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
3065 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3066 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
3067 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
3068 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
3069 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38
3070 * (READ_EVENT_LOG)
3071 */
3072 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */
3073 } MAILVARIANTS;
3074
3075 /*
3076 * SLI-2 specific structures
3077 */
3078
3079 struct lpfc_hgp {
3080 __le32 cmdPutInx;
3081 __le32 rspGetInx;
3082 };
3083
3084 struct lpfc_pgp {
3085 __le32 cmdGetInx;
3086 __le32 rspPutInx;
3087 };
3088
3089 struct sli2_desc {
3090 uint32_t unused1[16];
3091 struct lpfc_hgp host[MAX_RINGS];
3092 struct lpfc_pgp port[MAX_RINGS];
3093 };
3094
3095 struct sli3_desc {
3096 struct lpfc_hgp host[MAX_RINGS];
3097 uint32_t reserved[8];
3098 uint32_t hbq_put[16];
3099 };
3100
3101 struct sli3_pgp {
3102 struct lpfc_pgp port[MAX_RINGS];
3103 uint32_t hbq_get[16];
3104 };
3105
3106 union sli_var {
3107 struct sli2_desc s2;
3108 struct sli3_desc s3;
3109 struct sli3_pgp s3_pgp;
3110 };
3111
3112 typedef struct {
3113 #ifdef __BIG_ENDIAN_BITFIELD
3114 uint16_t mbxStatus;
3115 uint8_t mbxCommand;
3116 uint8_t mbxReserved:6;
3117 uint8_t mbxHc:1;
3118 uint8_t mbxOwner:1; /* Low order bit first word */
3119 #else /* __LITTLE_ENDIAN_BITFIELD */
3120 uint8_t mbxOwner:1; /* Low order bit first word */
3121 uint8_t mbxHc:1;
3122 uint8_t mbxReserved:6;
3123 uint8_t mbxCommand;
3124 uint16_t mbxStatus;
3125 #endif
3126
3127 MAILVARIANTS un;
3128 union sli_var us;
3129 } MAILBOX_t;
3130
3131 /*
3132 * Begin Structure Definitions for IOCB Commands
3133 */
3134
3135 typedef struct {
3136 #ifdef __BIG_ENDIAN_BITFIELD
3137 uint8_t statAction;
3138 uint8_t statRsn;
3139 uint8_t statBaExp;
3140 uint8_t statLocalError;
3141 #else /* __LITTLE_ENDIAN_BITFIELD */
3142 uint8_t statLocalError;
3143 uint8_t statBaExp;
3144 uint8_t statRsn;
3145 uint8_t statAction;
3146 #endif
3147 /* statRsn P/F_RJT reason codes */
3148 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
3149 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
3150 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
3151 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
3152 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */
3153 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
3154 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */
3155 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
3156 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
3157 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
3158 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */
3159 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */
3160 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
3161 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
3162 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
3163 #define RJT_BAD_PARM 0x10 /* Param. field invalid */
3164 #define RJT_XCHG_ERR 0x11 /* Exchange error */
3165 #define RJT_PROT_ERR 0x12 /* Protocol error */
3166 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */
3167 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3168 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3169 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
3170 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
3171 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
3172 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
3173 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
3174
3175 #define IOERR_SUCCESS 0x00 /* statLocalError */
3176 #define IOERR_MISSING_CONTINUE 0x01
3177 #define IOERR_SEQUENCE_TIMEOUT 0x02
3178 #define IOERR_INTERNAL_ERROR 0x03
3179 #define IOERR_INVALID_RPI 0x04
3180 #define IOERR_NO_XRI 0x05
3181 #define IOERR_ILLEGAL_COMMAND 0x06
3182 #define IOERR_XCHG_DROPPED 0x07
3183 #define IOERR_ILLEGAL_FIELD 0x08
3184 #define IOERR_BAD_CONTINUE 0x09
3185 #define IOERR_TOO_MANY_BUFFERS 0x0A
3186 #define IOERR_RCV_BUFFER_WAITING 0x0B
3187 #define IOERR_NO_CONNECTION 0x0C
3188 #define IOERR_TX_DMA_FAILED 0x0D
3189 #define IOERR_RX_DMA_FAILED 0x0E
3190 #define IOERR_ILLEGAL_FRAME 0x0F
3191 #define IOERR_EXTRA_DATA 0x10
3192 #define IOERR_NO_RESOURCES 0x11
3193 #define IOERR_RESERVED 0x12
3194 #define IOERR_ILLEGAL_LENGTH 0x13
3195 #define IOERR_UNSUPPORTED_FEATURE 0x14
3196 #define IOERR_ABORT_IN_PROGRESS 0x15
3197 #define IOERR_ABORT_REQUESTED 0x16
3198 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
3199 #define IOERR_LOOP_OPEN_FAILURE 0x18
3200 #define IOERR_RING_RESET 0x19
3201 #define IOERR_LINK_DOWN 0x1A
3202 #define IOERR_CORRUPTED_DATA 0x1B
3203 #define IOERR_CORRUPTED_RPI 0x1C
3204 #define IOERR_OUT_OF_ORDER_DATA 0x1D
3205 #define IOERR_OUT_OF_ORDER_ACK 0x1E
3206 #define IOERR_DUP_FRAME 0x1F
3207 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
3208 #define IOERR_BAD_HOST_ADDRESS 0x21
3209 #define IOERR_RCV_HDRBUF_WAITING 0x22
3210 #define IOERR_MISSING_HDR_BUFFER 0x23
3211 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
3212 #define IOERR_ABORTMULT_REQUESTED 0x25
3213 #define IOERR_BUFFER_SHORTAGE 0x28
3214 #define IOERR_DEFAULT 0x29
3215 #define IOERR_CNT 0x2A
3216 #define IOERR_SLER_FAILURE 0x46
3217 #define IOERR_SLER_CMD_RCV_FAILURE 0x47
3218 #define IOERR_SLER_REC_RJT_ERR 0x48
3219 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
3220 #define IOERR_SLER_SRR_RJT_ERR 0x4A
3221 #define IOERR_SLER_RRQ_RJT_ERR 0x4C
3222 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D
3223 #define IOERR_SLER_ABTS_ERR 0x4E
3224 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0
3225 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1
3226 #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2
3227 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3
3228 #define IOERR_DRVR_MASK 0x100
3229 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
3230 #define IOERR_SLI_BRESET 0x102
3231 #define IOERR_SLI_ABORTED 0x103
3232 } PARM_ERR;
3233
3234 typedef union {
3235 struct {
3236 #ifdef __BIG_ENDIAN_BITFIELD
3237 uint8_t Rctl; /* R_CTL field */
3238 uint8_t Type; /* TYPE field */
3239 uint8_t Dfctl; /* DF_CTL field */
3240 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3241 #else /* __LITTLE_ENDIAN_BITFIELD */
3242 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3243 uint8_t Dfctl; /* DF_CTL field */
3244 uint8_t Type; /* TYPE field */
3245 uint8_t Rctl; /* R_CTL field */
3246 #endif
3247
3248 #define BC 0x02 /* Broadcast Received - Fctl */
3249 #define SI 0x04 /* Sequence Initiative */
3250 #define LA 0x08 /* Ignore Link Attention state */
3251 #define LS 0x80 /* Last Sequence */
3252 } hcsw;
3253 uint32_t reserved;
3254 } WORD5;
3255
3256 /* IOCB Command template for a generic response */
3257 typedef struct {
3258 uint32_t reserved[4];
3259 PARM_ERR perr;
3260 } GENERIC_RSP;
3261
3262 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3263 typedef struct {
3264 struct ulp_bde xrsqbde[2];
3265 uint32_t xrsqRo; /* Starting Relative Offset */
3266 WORD5 w5; /* Header control/status word */
3267 } XR_SEQ_FIELDS;
3268
3269 /* IOCB Command template for ELS_REQUEST */
3270 typedef struct {
3271 struct ulp_bde elsReq;
3272 struct ulp_bde elsRsp;
3273
3274 #ifdef __BIG_ENDIAN_BITFIELD
3275 uint32_t word4Rsvd:7;
3276 uint32_t fl:1;
3277 uint32_t myID:24;
3278 uint32_t word5Rsvd:8;
3279 uint32_t remoteID:24;
3280 #else /* __LITTLE_ENDIAN_BITFIELD */
3281 uint32_t myID:24;
3282 uint32_t fl:1;
3283 uint32_t word4Rsvd:7;
3284 uint32_t remoteID:24;
3285 uint32_t word5Rsvd:8;
3286 #endif
3287 } ELS_REQUEST;
3288
3289 /* IOCB Command template for RCV_ELS_REQ */
3290 typedef struct {
3291 struct ulp_bde elsReq[2];
3292 uint32_t parmRo;
3293
3294 #ifdef __BIG_ENDIAN_BITFIELD
3295 uint32_t word5Rsvd:8;
3296 uint32_t remoteID:24;
3297 #else /* __LITTLE_ENDIAN_BITFIELD */
3298 uint32_t remoteID:24;
3299 uint32_t word5Rsvd:8;
3300 #endif
3301 } RCV_ELS_REQ;
3302
3303 /* IOCB Command template for ABORT / CLOSE_XRI */
3304 typedef struct {
3305 uint32_t rsvd[3];
3306 uint32_t abortType;
3307 #define ABORT_TYPE_ABTX 0x00000000
3308 #define ABORT_TYPE_ABTS 0x00000001
3309 uint32_t parm;
3310 #ifdef __BIG_ENDIAN_BITFIELD
3311 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3312 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3313 #else /* __LITTLE_ENDIAN_BITFIELD */
3314 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3315 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3316 #endif
3317 } AC_XRI;
3318
3319 /* IOCB Command template for ABORT_MXRI64 */
3320 typedef struct {
3321 uint32_t rsvd[3];
3322 uint32_t abortType;
3323 uint32_t parm;
3324 uint32_t iotag32;
3325 } A_MXRI64;
3326
3327 /* IOCB Command template for GET_RPI */
3328 typedef struct {
3329 uint32_t rsvd[4];
3330 uint32_t parmRo;
3331 #ifdef __BIG_ENDIAN_BITFIELD
3332 uint32_t word5Rsvd:8;
3333 uint32_t remoteID:24;
3334 #else /* __LITTLE_ENDIAN_BITFIELD */
3335 uint32_t remoteID:24;
3336 uint32_t word5Rsvd:8;
3337 #endif
3338 } GET_RPI;
3339
3340 /* IOCB Command template for all FCP Initiator commands */
3341 typedef struct {
3342 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
3343 struct ulp_bde fcpi_rsp; /* Rcv buffer */
3344 uint32_t fcpi_parm;
3345 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3346 } FCPI_FIELDS;
3347
3348 /* IOCB Command template for all FCP Target commands */
3349 typedef struct {
3350 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
3351 uint32_t fcpt_Offset;
3352 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3353 } FCPT_FIELDS;
3354
3355 /* SLI-2 IOCB structure definitions */
3356
3357 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3358 typedef struct {
3359 ULP_BDL bdl;
3360 uint32_t xrsqRo; /* Starting Relative Offset */
3361 WORD5 w5; /* Header control/status word */
3362 } XMT_SEQ_FIELDS64;
3363
3364 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3365 typedef struct {
3366 struct ulp_bde64 rcvBde;
3367 uint32_t rsvd1;
3368 uint32_t xrsqRo; /* Starting Relative Offset */
3369 WORD5 w5; /* Header control/status word */
3370 } RCV_SEQ_FIELDS64;
3371
3372 /* IOCB Command template for ELS_REQUEST64 */
3373 typedef struct {
3374 ULP_BDL bdl;
3375 #ifdef __BIG_ENDIAN_BITFIELD
3376 uint32_t word4Rsvd:7;
3377 uint32_t fl:1;
3378 uint32_t myID:24;
3379 uint32_t word5Rsvd:8;
3380 uint32_t remoteID:24;
3381 #else /* __LITTLE_ENDIAN_BITFIELD */
3382 uint32_t myID:24;
3383 uint32_t fl:1;
3384 uint32_t word4Rsvd:7;
3385 uint32_t remoteID:24;
3386 uint32_t word5Rsvd:8;
3387 #endif
3388 } ELS_REQUEST64;
3389
3390 /* IOCB Command template for GEN_REQUEST64 */
3391 typedef struct {
3392 ULP_BDL bdl;
3393 uint32_t xrsqRo; /* Starting Relative Offset */
3394 WORD5 w5; /* Header control/status word */
3395 } GEN_REQUEST64;
3396
3397 /* IOCB Command template for RCV_ELS_REQ64 */
3398 typedef struct {
3399 struct ulp_bde64 elsReq;
3400 uint32_t rcvd1;
3401 uint32_t parmRo;
3402
3403 #ifdef __BIG_ENDIAN_BITFIELD
3404 uint32_t word5Rsvd:8;
3405 uint32_t remoteID:24;
3406 #else /* __LITTLE_ENDIAN_BITFIELD */
3407 uint32_t remoteID:24;
3408 uint32_t word5Rsvd:8;
3409 #endif
3410 } RCV_ELS_REQ64;
3411
3412 /* IOCB Command template for RCV_SEQ64 */
3413 struct rcv_seq64 {
3414 struct ulp_bde64 elsReq;
3415 uint32_t hbq_1;
3416 uint32_t parmRo;
3417 #ifdef __BIG_ENDIAN_BITFIELD
3418 uint32_t rctl:8;
3419 uint32_t type:8;
3420 uint32_t dfctl:8;
3421 uint32_t ls:1;
3422 uint32_t fs:1;
3423 uint32_t rsvd2:3;
3424 uint32_t si:1;
3425 uint32_t bc:1;
3426 uint32_t rsvd3:1;
3427 #else /* __LITTLE_ENDIAN_BITFIELD */
3428 uint32_t rsvd3:1;
3429 uint32_t bc:1;
3430 uint32_t si:1;
3431 uint32_t rsvd2:3;
3432 uint32_t fs:1;
3433 uint32_t ls:1;
3434 uint32_t dfctl:8;
3435 uint32_t type:8;
3436 uint32_t rctl:8;
3437 #endif
3438 };
3439
3440 /* IOCB Command template for all 64 bit FCP Initiator commands */
3441 typedef struct {
3442 ULP_BDL bdl;
3443 uint32_t fcpi_parm;
3444 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3445 } FCPI_FIELDS64;
3446
3447 /* IOCB Command template for all 64 bit FCP Target commands */
3448 typedef struct {
3449 ULP_BDL bdl;
3450 uint32_t fcpt_Offset;
3451 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3452 } FCPT_FIELDS64;
3453
3454 /* IOCB Command template for Async Status iocb commands */
3455 typedef struct {
3456 uint32_t rsvd[4];
3457 uint32_t param;
3458 #ifdef __BIG_ENDIAN_BITFIELD
3459 uint16_t evt_code; /* High order bits word 5 */
3460 uint16_t sub_ctxt_tag; /* Low order bits word 5 */
3461 #else /* __LITTLE_ENDIAN_BITFIELD */
3462 uint16_t sub_ctxt_tag; /* High order bits word 5 */
3463 uint16_t evt_code; /* Low order bits word 5 */
3464 #endif
3465 } ASYNCSTAT_FIELDS;
3466 #define ASYNC_TEMP_WARN 0x100
3467 #define ASYNC_TEMP_SAFE 0x101
3468
3469 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
3470 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
3471
3472 struct rcv_sli3 {
3473 #ifdef __BIG_ENDIAN_BITFIELD
3474 uint16_t ox_id;
3475 uint16_t seq_cnt;
3476
3477 uint16_t vpi;
3478 uint16_t word9Rsvd;
3479 #else /* __LITTLE_ENDIAN */
3480 uint16_t seq_cnt;
3481 uint16_t ox_id;
3482
3483 uint16_t word9Rsvd;
3484 uint16_t vpi;
3485 #endif
3486 uint32_t word10Rsvd;
3487 uint32_t acc_len; /* accumulated length */
3488 struct ulp_bde64 bde2;
3489 };
3490
3491 /* Structure used for a single HBQ entry */
3492 struct lpfc_hbq_entry {
3493 struct ulp_bde64 bde;
3494 uint32_t buffer_tag;
3495 };
3496
3497 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
3498 typedef struct {
3499 struct lpfc_hbq_entry buff;
3500 uint32_t rsvd;
3501 uint32_t rsvd1;
3502 } QUE_XRI64_CX_FIELDS;
3503
3504 struct que_xri64cx_ext_fields {
3505 uint32_t iotag64_low;
3506 uint32_t iotag64_high;
3507 uint32_t ebde_count;
3508 uint32_t rsvd;
3509 struct lpfc_hbq_entry buff[5];
3510 };
3511
3512 struct sli3_bg_fields {
3513 uint32_t filler[6]; /* word 8-13 in IOCB */
3514 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */
3515 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
3516 #define BGS_BIDIR_BG_PROF_MASK 0xff000000
3517 #define BGS_BIDIR_BG_PROF_SHIFT 24
3518 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
3519 #define BGS_BIDIR_ERR_COND_SHIFT 16
3520 #define BGS_BG_PROFILE_MASK 0x0000ff00
3521 #define BGS_BG_PROFILE_SHIFT 8
3522 #define BGS_INVALID_PROF_MASK 0x00000020
3523 #define BGS_INVALID_PROF_SHIFT 5
3524 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
3525 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4
3526 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
3527 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
3528 #define BGS_REFTAG_ERR_MASK 0x00000004
3529 #define BGS_REFTAG_ERR_SHIFT 2
3530 #define BGS_APPTAG_ERR_MASK 0x00000002
3531 #define BGS_APPTAG_ERR_SHIFT 1
3532 #define BGS_GUARD_ERR_MASK 0x00000001
3533 #define BGS_GUARD_ERR_SHIFT 0
3534 uint32_t bgstat; /* word 15 - BlockGuard Status */
3535 };
3536
3537 static inline uint32_t
3538 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
3539 {
3540 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
3541 BGS_BIDIR_BG_PROF_SHIFT;
3542 }
3543
3544 static inline uint32_t
3545 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
3546 {
3547 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
3548 BGS_BIDIR_ERR_COND_SHIFT;
3549 }
3550
3551 static inline uint32_t
3552 lpfc_bgs_get_bg_prof(uint32_t bgstat)
3553 {
3554 return (bgstat & BGS_BG_PROFILE_MASK) >>
3555 BGS_BG_PROFILE_SHIFT;
3556 }
3557
3558 static inline uint32_t
3559 lpfc_bgs_get_invalid_prof(uint32_t bgstat)
3560 {
3561 return (bgstat & BGS_INVALID_PROF_MASK) >>
3562 BGS_INVALID_PROF_SHIFT;
3563 }
3564
3565 static inline uint32_t
3566 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
3567 {
3568 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
3569 BGS_UNINIT_DIF_BLOCK_SHIFT;
3570 }
3571
3572 static inline uint32_t
3573 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
3574 {
3575 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
3576 BGS_HI_WATER_MARK_PRESENT_SHIFT;
3577 }
3578
3579 static inline uint32_t
3580 lpfc_bgs_get_reftag_err(uint32_t bgstat)
3581 {
3582 return (bgstat & BGS_REFTAG_ERR_MASK) >>
3583 BGS_REFTAG_ERR_SHIFT;
3584 }
3585
3586 static inline uint32_t
3587 lpfc_bgs_get_apptag_err(uint32_t bgstat)
3588 {
3589 return (bgstat & BGS_APPTAG_ERR_MASK) >>
3590 BGS_APPTAG_ERR_SHIFT;
3591 }
3592
3593 static inline uint32_t
3594 lpfc_bgs_get_guard_err(uint32_t bgstat)
3595 {
3596 return (bgstat & BGS_GUARD_ERR_MASK) >>
3597 BGS_GUARD_ERR_SHIFT;
3598 }
3599
3600 #define LPFC_EXT_DATA_BDE_COUNT 3
3601 struct fcp_irw_ext {
3602 uint32_t io_tag64_low;
3603 uint32_t io_tag64_high;
3604 #ifdef __BIG_ENDIAN_BITFIELD
3605 uint8_t reserved1;
3606 uint8_t reserved2;
3607 uint8_t reserved3;
3608 uint8_t ebde_count;
3609 #else /* __LITTLE_ENDIAN */
3610 uint8_t ebde_count;
3611 uint8_t reserved3;
3612 uint8_t reserved2;
3613 uint8_t reserved1;
3614 #endif
3615 uint32_t reserved4;
3616 struct ulp_bde64 rbde; /* response bde */
3617 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
3618 uint8_t icd[32]; /* immediate command data (32 bytes) */
3619 };
3620
3621 typedef struct _IOCB { /* IOCB structure */
3622 union {
3623 GENERIC_RSP grsp; /* Generic response */
3624 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
3625 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
3626 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
3627 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
3628 A_MXRI64 amxri; /* abort multiple xri command overlay */
3629 GET_RPI getrpi; /* GET_RPI template */
3630 FCPI_FIELDS fcpi; /* FCP Initiator template */
3631 FCPT_FIELDS fcpt; /* FCP target template */
3632
3633 /* SLI-2 structures */
3634
3635 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
3636 * bde_64s */
3637 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
3638 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
3639 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
3640 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
3641 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
3642 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
3643 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
3644 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
3645 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */
3646 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
3647 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
3648 } un;
3649 union {
3650 struct {
3651 #ifdef __BIG_ENDIAN_BITFIELD
3652 uint16_t ulpContext; /* High order bits word 6 */
3653 uint16_t ulpIoTag; /* Low order bits word 6 */
3654 #else /* __LITTLE_ENDIAN_BITFIELD */
3655 uint16_t ulpIoTag; /* Low order bits word 6 */
3656 uint16_t ulpContext; /* High order bits word 6 */
3657 #endif
3658 } t1;
3659 struct {
3660 #ifdef __BIG_ENDIAN_BITFIELD
3661 uint16_t ulpContext; /* High order bits word 6 */
3662 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3663 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3664 #else /* __LITTLE_ENDIAN_BITFIELD */
3665 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3666 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3667 uint16_t ulpContext; /* High order bits word 6 */
3668 #endif
3669 } t2;
3670 } un1;
3671 #define ulpContext un1.t1.ulpContext
3672 #define ulpIoTag un1.t1.ulpIoTag
3673 #define ulpIoTag0 un1.t2.ulpIoTag0
3674
3675 #ifdef __BIG_ENDIAN_BITFIELD
3676 uint32_t ulpTimeout:8;
3677 uint32_t ulpXS:1;
3678 uint32_t ulpFCP2Rcvy:1;
3679 uint32_t ulpPU:2;
3680 uint32_t ulpIr:1;
3681 uint32_t ulpClass:3;
3682 uint32_t ulpCommand:8;
3683 uint32_t ulpStatus:4;
3684 uint32_t ulpBdeCount:2;
3685 uint32_t ulpLe:1;
3686 uint32_t ulpOwner:1; /* Low order bit word 7 */
3687 #else /* __LITTLE_ENDIAN_BITFIELD */
3688 uint32_t ulpOwner:1; /* Low order bit word 7 */
3689 uint32_t ulpLe:1;
3690 uint32_t ulpBdeCount:2;
3691 uint32_t ulpStatus:4;
3692 uint32_t ulpCommand:8;
3693 uint32_t ulpClass:3;
3694 uint32_t ulpIr:1;
3695 uint32_t ulpPU:2;
3696 uint32_t ulpFCP2Rcvy:1;
3697 uint32_t ulpXS:1;
3698 uint32_t ulpTimeout:8;
3699 #endif
3700
3701 union {
3702 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
3703
3704 /* words 8-31 used for que_xri_cx iocb */
3705 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
3706 struct fcp_irw_ext fcp_ext;
3707 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
3708
3709 /* words 8-15 for BlockGuard */
3710 struct sli3_bg_fields sli3_bg;
3711 } unsli3;
3712
3713 #define ulpCt_h ulpXS
3714 #define ulpCt_l ulpFCP2Rcvy
3715
3716 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
3717 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
3718 #define PARM_UNUSED 0 /* PU field (Word 4) not used */
3719 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
3720 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
3721 #define PARM_NPIV_DID 3
3722 #define CLASS1 0 /* Class 1 */
3723 #define CLASS2 1 /* Class 2 */
3724 #define CLASS3 2 /* Class 3 */
3725 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
3726
3727 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
3728 #define IOSTAT_FCP_RSP_ERROR 0x1
3729 #define IOSTAT_REMOTE_STOP 0x2
3730 #define IOSTAT_LOCAL_REJECT 0x3
3731 #define IOSTAT_NPORT_RJT 0x4
3732 #define IOSTAT_FABRIC_RJT 0x5
3733 #define IOSTAT_NPORT_BSY 0x6
3734 #define IOSTAT_FABRIC_BSY 0x7
3735 #define IOSTAT_INTERMED_RSP 0x8
3736 #define IOSTAT_LS_RJT 0x9
3737 #define IOSTAT_BA_RJT 0xA
3738 #define IOSTAT_RSVD1 0xB
3739 #define IOSTAT_RSVD2 0xC
3740 #define IOSTAT_RSVD3 0xD
3741 #define IOSTAT_RSVD4 0xE
3742 #define IOSTAT_NEED_BUFFER 0xF
3743 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
3744 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
3745 #define IOSTAT_CNT 0x11
3746
3747 } IOCB_t;
3748
3749
3750 #define SLI1_SLIM_SIZE (4 * 1024)
3751
3752 /* Up to 498 IOCBs will fit into 16k
3753 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
3754 */
3755 #define SLI2_SLIM_SIZE (64 * 1024)
3756
3757 /* Maximum IOCBs that will fit in SLI2 slim */
3758 #define MAX_SLI2_IOCB 498
3759 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
3760 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
3761 sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
3762
3763 /* HBQ entries are 4 words each = 4k */
3764 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
3765 lpfc_sli_hbq_count())
3766
3767 struct lpfc_sli2_slim {
3768 MAILBOX_t mbx;
3769 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE];
3770 PCB_t pcb;
3771 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
3772 };
3773
3774 /*
3775 * This function checks PCI device to allow special handling for LC HBAs.
3776 *
3777 * Parameters:
3778 * device : struct pci_dev 's device field
3779 *
3780 * return 1 => TRUE
3781 * 0 => FALSE
3782 */
3783 static inline int
3784 lpfc_is_LC_HBA(unsigned short device)
3785 {
3786 if ((device == PCI_DEVICE_ID_TFLY) ||
3787 (device == PCI_DEVICE_ID_PFLY) ||
3788 (device == PCI_DEVICE_ID_LP101) ||
3789 (device == PCI_DEVICE_ID_BMID) ||
3790 (device == PCI_DEVICE_ID_BSMB) ||
3791 (device == PCI_DEVICE_ID_ZMID) ||
3792 (device == PCI_DEVICE_ID_ZSMB) ||
3793 (device == PCI_DEVICE_ID_SAT_MID) ||
3794 (device == PCI_DEVICE_ID_SAT_SMB) ||
3795 (device == PCI_DEVICE_ID_RFLY))
3796 return 1;
3797 else
3798 return 0;
3799 }
3800
3801 /*
3802 * Determine if an IOCB failed because of a link event or firmware reset.
3803 */
3804
3805 static inline int
3806 lpfc_error_lost_link(IOCB_t *iocbp)
3807 {
3808 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
3809 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
3810 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
3811 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
3812 }
3813
3814 #define MENLO_TRANSPORT_TYPE 0xfe
3815 #define MENLO_CONTEXT 0
3816 #define MENLO_PU 3
3817 #define MENLO_TIMEOUT 30
3818 #define SETVAR_MLOMNT 0x103107
3819 #define SETVAR_MLORST 0x103007
3820
3821 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */
linux-next