MERGE-master-patchset-edits
[linux-2.6/openmoko-kernel.git] / arch / arm / mach-realview / platsmp.c
blobea3c75595fa9a575d021a82c7d6c4e92e8510b6e
1 /*
2 * linux/arch/arm/mach-realview/platsmp.c
4 * Copyright (C) 2002 ARM Ltd.
5 * All Rights Reserved
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/init.h>
12 #include <linux/errno.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/jiffies.h>
16 #include <linux/smp.h>
17 #include <linux/io.h>
19 #include <asm/cacheflush.h>
20 #include <mach/hardware.h>
21 #include <asm/mach-types.h>
23 #include <mach/board-eb.h>
24 #include <mach/board-pb11mp.h>
25 #include <mach/scu.h>
27 #include "core.h"
29 extern void realview_secondary_startup(void);
32 * control for which core is the next to come out of the secondary
33 * boot "holding pen"
35 volatile int __cpuinitdata pen_release = -1;
37 static void __iomem *scu_base_addr(void)
39 if (machine_is_realview_eb_mp())
40 return __io_address(REALVIEW_EB11MP_SCU_BASE);
41 else if (machine_is_realview_pb11mp())
42 return __io_address(REALVIEW_TC11MP_SCU_BASE);
43 else
44 return (void __iomem *)0;
47 static unsigned int __init get_core_count(void)
49 unsigned int ncores;
50 void __iomem *scu_base = scu_base_addr();
52 if (scu_base) {
53 ncores = __raw_readl(scu_base + SCU_CONFIG);
54 ncores = (ncores & 0x03) + 1;
55 } else
56 ncores = 1;
58 return ncores;
62 * Setup the SCU
64 static void scu_enable(void)
66 u32 scu_ctrl;
67 void __iomem *scu_base = scu_base_addr();
69 scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
70 scu_ctrl |= 1;
71 __raw_writel(scu_ctrl, scu_base + SCU_CTRL);
74 static DEFINE_SPINLOCK(boot_lock);
76 void __cpuinit platform_secondary_init(unsigned int cpu)
78 trace_hardirqs_off();
81 * the primary core may have used a "cross call" soft interrupt
82 * to get this processor out of WFI in the BootMonitor - make
83 * sure that we are no longer being sent this soft interrupt
85 smp_cross_call_done(cpumask_of_cpu(cpu));
88 * if any interrupts are already enabled for the primary
89 * core (e.g. timer irq), then they will not have been enabled
90 * for us: do so
92 gic_cpu_init(0, gic_cpu_base_addr);
95 * let the primary processor know we're out of the
96 * pen, then head off into the C entry point
98 pen_release = -1;
99 smp_wmb();
102 * Synchronise with the boot thread.
104 spin_lock(&boot_lock);
105 spin_unlock(&boot_lock);
108 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
110 unsigned long timeout;
113 * set synchronisation state between this boot processor
114 * and the secondary one
116 spin_lock(&boot_lock);
119 * The secondary processor is waiting to be released from
120 * the holding pen - release it, then wait for it to flag
121 * that it has been released by resetting pen_release.
123 * Note that "pen_release" is the hardware CPU ID, whereas
124 * "cpu" is Linux's internal ID.
126 pen_release = cpu;
127 flush_cache_all();
130 * XXX
132 * This is a later addition to the booting protocol: the
133 * bootMonitor now puts secondary cores into WFI, so
134 * poke_milo() no longer gets the cores moving; we need
135 * to send a soft interrupt to wake the secondary core.
136 * Use smp_cross_call() for this, since there's little
137 * point duplicating the code here
139 smp_cross_call(cpumask_of_cpu(cpu));
141 timeout = jiffies + (1 * HZ);
142 while (time_before(jiffies, timeout)) {
143 smp_rmb();
144 if (pen_release == -1)
145 break;
147 udelay(10);
151 * now the secondary core is starting up let it run its
152 * calibrations, then wait for it to finish
154 spin_unlock(&boot_lock);
156 return pen_release != -1 ? -ENOSYS : 0;
159 static void __init poke_milo(void)
161 extern void secondary_startup(void);
163 /* nobody is to be released from the pen yet */
164 pen_release = -1;
167 * write the address of secondary startup into the system-wide
168 * flags register, then clear the bottom two bits, which is what
169 * BootMonitor is waiting for
171 #if 1
172 #define REALVIEW_SYS_FLAGSS_OFFSET 0x30
173 __raw_writel(virt_to_phys(realview_secondary_startup),
174 __io_address(REALVIEW_SYS_BASE) +
175 REALVIEW_SYS_FLAGSS_OFFSET);
176 #define REALVIEW_SYS_FLAGSC_OFFSET 0x34
177 __raw_writel(3,
178 __io_address(REALVIEW_SYS_BASE) +
179 REALVIEW_SYS_FLAGSC_OFFSET);
180 #endif
182 mb();
186 * Initialise the CPU possible map early - this describes the CPUs
187 * which may be present or become present in the system.
189 void __init smp_init_cpus(void)
191 unsigned int i, ncores = get_core_count();
193 for (i = 0; i < ncores; i++)
194 cpu_set(i, cpu_possible_map);
197 void __init smp_prepare_cpus(unsigned int max_cpus)
199 unsigned int ncores = get_core_count();
200 unsigned int cpu = smp_processor_id();
201 int i;
203 /* sanity check */
204 if (ncores == 0) {
205 printk(KERN_ERR
206 "Realview: strange CM count of 0? Default to 1\n");
208 ncores = 1;
211 if (ncores > NR_CPUS) {
212 printk(KERN_WARNING
213 "Realview: no. of cores (%d) greater than configured "
214 "maximum of %d - clipping\n",
215 ncores, NR_CPUS);
216 ncores = NR_CPUS;
219 smp_store_cpu_info(cpu);
222 * are we trying to boot more cores than exist?
224 if (max_cpus > ncores)
225 max_cpus = ncores;
227 #ifdef CONFIG_LOCAL_TIMERS
229 * Enable the local timer for primary CPU. If the device is
230 * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in
231 * realview_timer_init
233 local_timer_setup();
234 #endif
237 * Initialise the present map, which describes the set of CPUs
238 * actually populated at the present time.
240 for (i = 0; i < max_cpus; i++)
241 cpu_set(i, cpu_present_map);
244 * Initialise the SCU if there are more than one CPU and let
245 * them know where to start. Note that, on modern versions of
246 * MILO, the "poke" doesn't actually do anything until each
247 * individual core is sent a soft interrupt to get it out of
248 * WFI
250 if (max_cpus > 1) {
251 scu_enable();
252 poke_milo();