MERGE-master-patchset-edits
[linux-2.6/openmoko-kernel.git] / arch / avr32 / kernel / time.c
blob0ff46bf873b034192ec557511febfe6586930ece
1 /*
2 * Copyright (C) 2004-2007 Atmel Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 #include <linux/clk.h>
9 #include <linux/clockchips.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/kernel.h>
14 #include <linux/time.h>
16 #include <asm/sysreg.h>
18 #include <mach/pm.h>
21 static cycle_t read_cycle_count(void)
23 return (cycle_t)sysreg_read(COUNT);
27 * The architectural cycle count registers are a fine clocksource unless
28 * the system idle loop use sleep states like "idle": the CPU cycles
29 * measured by COUNT (and COMPARE) don't happen during sleep states.
30 * Their duration also changes if cpufreq changes the CPU clock rate.
31 * So we rate the clocksource using COUNT as very low quality.
33 static struct clocksource counter = {
34 .name = "avr32_counter",
35 .rating = 50,
36 .read = read_cycle_count,
37 .mask = CLOCKSOURCE_MASK(32),
38 .shift = 16,
39 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
42 static irqreturn_t timer_interrupt(int irq, void *dev_id)
44 struct clock_event_device *evdev = dev_id;
46 if (unlikely(!(intc_get_pending(0) & 1)))
47 return IRQ_NONE;
50 * Disable the interrupt until the clockevent subsystem
51 * reprograms it.
53 sysreg_write(COMPARE, 0);
55 evdev->event_handler(evdev);
56 return IRQ_HANDLED;
59 static struct irqaction timer_irqaction = {
60 .handler = timer_interrupt,
61 /* Oprofile uses the same irq as the timer, so allow it to be shared */
62 .flags = IRQF_TIMER | IRQF_DISABLED | IRQF_SHARED,
63 .name = "avr32_comparator",
66 static int comparator_next_event(unsigned long delta,
67 struct clock_event_device *evdev)
69 unsigned long flags;
71 raw_local_irq_save(flags);
73 /* The time to read COUNT then update COMPARE must be less
74 * than the min_delta_ns value for this clockevent source.
76 sysreg_write(COMPARE, (sysreg_read(COUNT) + delta) ? : 1);
78 raw_local_irq_restore(flags);
80 return 0;
83 static void comparator_mode(enum clock_event_mode mode,
84 struct clock_event_device *evdev)
86 switch (mode) {
87 case CLOCK_EVT_MODE_ONESHOT:
88 pr_debug("%s: start\n", evdev->name);
89 /* FALLTHROUGH */
90 case CLOCK_EVT_MODE_RESUME:
91 cpu_disable_idle_sleep();
92 break;
93 case CLOCK_EVT_MODE_UNUSED:
94 case CLOCK_EVT_MODE_SHUTDOWN:
95 sysreg_write(COMPARE, 0);
96 pr_debug("%s: stop\n", evdev->name);
97 cpu_enable_idle_sleep();
98 break;
99 default:
100 BUG();
104 static struct clock_event_device comparator = {
105 .name = "avr32_comparator",
106 .features = CLOCK_EVT_FEAT_ONESHOT,
107 .shift = 16,
108 .rating = 50,
109 .set_next_event = comparator_next_event,
110 .set_mode = comparator_mode,
113 void __init time_init(void)
115 unsigned long counter_hz;
116 int ret;
118 xtime.tv_sec = mktime(2007, 1, 1, 0, 0, 0);
119 xtime.tv_nsec = 0;
121 set_normalized_timespec(&wall_to_monotonic,
122 -xtime.tv_sec, -xtime.tv_nsec);
124 /* figure rate for counter */
125 counter_hz = clk_get_rate(boot_cpu_data.clk);
126 counter.mult = clocksource_hz2mult(counter_hz, counter.shift);
128 ret = clocksource_register(&counter);
129 if (ret)
130 pr_debug("timer: could not register clocksource: %d\n", ret);
132 /* setup COMPARE clockevent */
133 comparator.mult = div_sc(counter_hz, NSEC_PER_SEC, comparator.shift);
134 comparator.max_delta_ns = clockevent_delta2ns((u32)~0, &comparator);
135 comparator.min_delta_ns = clockevent_delta2ns(50, &comparator) + 1;
136 comparator.cpumask = cpumask_of(0);
138 sysreg_write(COMPARE, 0);
139 timer_irqaction.dev_id = &comparator;
141 ret = setup_irq(0, &timer_irqaction);
142 if (ret)
143 pr_debug("timer: could not request IRQ 0: %d\n", ret);
144 else {
145 clockevents_register_device(&comparator);
147 pr_info("%s: irq 0, %lu.%03lu MHz\n", comparator.name,
148 ((counter_hz + 500) / 1000) / 1000,
149 ((counter_hz + 500) / 1000) % 1000);