include/asm-cris/arch-v32/tlb.h

   1 #ifndef _CRIS_ARCH_TLB_H
   2 #define _CRIS_ARCH_TLB_H
   3
   4 /*
   5  * The TLB is a 64-entry cache. Each entry has a 8-bit page_id that is used
   6  * to store the "process" it belongs to (=> fast mm context switch). The
   7  * last page_id is never used so we can make TLB entries that never matches.
   8  */
   9 #define NUM_TLB_ENTRIES 64
  10 #define NUM_PAGEID 256
  11 #define INVALID_PAGEID 255
  12 #define NO_CONTEXT -1
  13
  14 #endif /* _CRIS_ARCH_TLB_H */