include/asm-sparc64/system.h

   1 /* $Id: system.h,v 1.69 2002/02/09 19:49:31 davem Exp $ */
   2 #ifndef __SPARC64_SYSTEM_H
   3 #define __SPARC64_SYSTEM_H
   4
   5 #include <asm/ptrace.h>
   6 #include <asm/processor.h>
   7 #include <asm/visasm.h>
   8
   9 #ifndef __ASSEMBLY__
  10 /*
  11  * Sparc (general) CPU types
  12  */
  13 enum sparc_cpu {
  14   sun4        = 0x00,
  15   sun4c       = 0x01,
  16   sun4m       = 0x02,
  17   sun4d       = 0x03,
  18   sun4e       = 0x04,
  19   sun4u       = 0x05, /* V8 ploos ploos */
  20   sun_unknown = 0x06,
  21   ap1000      = 0x07, /* almost a sun4m */
  22 };
  23
  24 #define sparc_cpu_model sun4u
  25
  26 /* This cannot ever be a sun4c nor sun4 :) That's just history. */
  27 #define ARCH_SUN4C_SUN4 0
  28 #define ARCH_SUN4 0
  29
  30 /* These are here in an effort to more fully work around Spitfire Errata
  31  * #51.  Essentially, if a memory barrier occurs soon after a mispredicted
  32  * branch, the chip can stop executing instructions until a trap occurs.
  33  * Therefore, if interrupts are disabled, the chip can hang forever.
  34  *
  35  * It used to be believed that the memory barrier had to be right in the
  36  * delay slot, but a case has been traced recently wherein the memory barrier
  37  * was one instruction after the branch delay slot and the chip still hung.
  38  * The offending sequence was the following in sym_wakeup_done() of the
  39  * sym53c8xx_2 driver:
  40  *
  41  *      call    sym_ccb_from_dsa, 0
  42  *       movge  %icc, 0, %l0
  43  *      brz,pn  %o0, .LL1303
  44  *       mov    %o0, %l2
  45  *      membar  #LoadLoad
  46  *
  47  * The branch has to be mispredicted for the bug to occur.  Therefore, we put
  48  * the memory barrier explicitly into a "branch always, predicted taken"
  49  * delay slot to avoid the problem case.
  50  */
  51 #define membar_safe(type) \
  52 do {    __asm__ __volatile__("ba,pt     %%xcc, 1f\n\t" \
  53                              " membar   " type "\n" \
  54                              "1:\n" \
  55                              : : : "memory"); \
  56 } while (0)
  57
  58 #define mb()    \
  59         membar_safe("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")
  60 #define rmb()   \
  61         membar_safe("#LoadLoad")
  62 #define wmb()   \
  63         membar_safe("#StoreStore")
  64 #define membar_storeload() \
  65         membar_safe("#StoreLoad")
  66 #define membar_storeload_storestore() \
  67         membar_safe("#StoreLoad | #StoreStore")
  68 #define membar_storeload_loadload() \
  69         membar_safe("#StoreLoad | #LoadLoad")
  70 #define membar_storestore_loadstore() \
  71         membar_safe("#StoreStore | #LoadStore")
  72
  73 #endif
  74
  75 #define setipl(__new_ipl) \
  76         __asm__ __volatile__("wrpr      %0, %%pil"  : : "r" (__new_ipl) : "memory")
  77
  78 #define local_irq_disable() \
  79         __asm__ __volatile__("wrpr      15, %%pil" : : : "memory")
  80
  81 #define local_irq_enable() \
  82         __asm__ __volatile__("wrpr      0, %%pil" : : : "memory")
  83
  84 #define getipl() \
  85 ({ unsigned long retval; __asm__ __volatile__("rdpr     %%pil, %0" : "=r" (retval)); retval; })
  86
  87 #define swap_pil(__new_pil) \
  88 ({      unsigned long retval; \
  89         __asm__ __volatile__("rdpr      %%pil, %0\n\t" \
  90                              "wrpr      %1, %%pil" \
  91                              : "=&r" (retval) \
  92                              : "r" (__new_pil) \
  93                              : "memory"); \
  94         retval; \
  95 })
  96
  97 #define read_pil_and_cli() \
  98 ({      unsigned long retval; \
  99         __asm__ __volatile__("rdpr      %%pil, %0\n\t" \
 100                              "wrpr      15, %%pil" \
 101                              : "=r" (retval) \
 102                              : : "memory"); \
 103         retval; \
 104 })
 105
 106 #define local_save_flags(flags)         ((flags) = getipl())
 107 #define local_irq_save(flags)           ((flags) = read_pil_and_cli())
 108 #define local_irq_restore(flags)                setipl((flags))
 109
 110 /* On sparc64 IRQ flags are the PIL register.  A value of zero
 111  * means all interrupt levels are enabled, any other value means
 112  * only IRQ levels greater than that value will be received.
 113  * Consequently this means that the lowest IRQ level is one.
 114  */
 115 #define irqs_disabled()         \
 116 ({      unsigned long flags;    \
 117         local_save_flags(flags);\
 118         (flags > 0);            \
 119 })
 120
 121 #define nop()           __asm__ __volatile__ ("nop")
 122
 123 #define read_barrier_depends()          do { } while(0)
 124 #define set_mb(__var, __value) \
 125         do { __var = __value; membar_storeload_storestore(); } while(0)
 126 #define set_wmb(__var, __value) \
 127         do { __var = __value; wmb(); } while(0)
 128
 129 #ifdef CONFIG_SMP
 130 #define smp_mb()        mb()
 131 #define smp_rmb()       rmb()
 132 #define smp_wmb()       wmb()
 133 #define smp_read_barrier_depends()      read_barrier_depends()
 134 #else
 135 #define smp_mb()        __asm__ __volatile__("":::"memory")
 136 #define smp_rmb()       __asm__ __volatile__("":::"memory")
 137 #define smp_wmb()       __asm__ __volatile__("":::"memory")
 138 #define smp_read_barrier_depends()      do { } while(0)
 139 #endif
 140
 141 #define flushi(addr)    __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
 142
 143 #define flushw_all()    __asm__ __volatile__("flushw")
 144
 145 /* Performance counter register access. */
 146 #define read_pcr(__p)  __asm__ __volatile__("rd %%pcr, %0" : "=r" (__p))
 147 #define write_pcr(__p) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (__p))
 148 #define read_pic(__p)  __asm__ __volatile__("rd %%pic, %0" : "=r" (__p))
 149
 150 /* Blackbird errata workaround.  See commentary in
 151  * arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
 152  * for more information.
 153  */
 154 #define reset_pic()                                             \
 155         __asm__ __volatile__("ba,pt     %xcc, 99f\n\t"          \
 156                              ".align    64\n"                   \
 157                           "99:wr        %g0, 0x0, %pic\n\t"     \
 158                              "rd        %pic, %g0")
 159
 160 #ifndef __ASSEMBLY__
 161
 162 extern void sun_do_break(void);
 163 extern int serial_console;
 164 extern int stop_a_enabled;
 165
 166 static __inline__ int con_is_present(void)
 167 {
 168         return serial_console ? 0 : 1;
 169 }
 170
 171 extern void synchronize_user_stack(void);
 172
 173 extern void __flushw_user(void);
 174 #define flushw_user() __flushw_user()
 175
 176 #define flush_user_windows flushw_user
 177 #define flush_register_windows flushw_all
 178
 179 /* Don't hold the runqueue lock over context switch */
 180 #define __ARCH_WANT_UNLOCKED_CTXSW
 181 #define prepare_arch_switch(next)               \
 182 do {                                            \
 183         flushw_all();                           \
 184 } while (0)
 185
 186         /* See what happens when you design the chip correctly?
 187          *
 188          * We tell gcc we clobber all non-fixed-usage registers except
 189          * for l0/l1.  It will use one for 'next' and the other to hold
 190          * the output value of 'last'.  'next' is not referenced again
 191          * past the invocation of switch_to in the scheduler, so we need
 192          * not preserve it's value.  Hairy, but it lets us remove 2 loads
 193          * and 2 stores in this critical code path.  -DaveM
 194          */
 195 #define EXTRA_CLOBBER ,"%l1"
 196 #define switch_to(prev, next, last)                                     \
 197 do {    if (test_thread_flag(TIF_PERFCTR)) {                            \
 198                 unsigned long __tmp;                                    \
 199                 read_pcr(__tmp);                                        \
 200                 current_thread_info()->pcr_reg = __tmp;                 \
 201                 read_pic(__tmp);                                        \
 202                 current_thread_info()->kernel_cntd0 += (unsigned int)(__tmp);\
 203                 current_thread_info()->kernel_cntd1 += ((__tmp) >> 32); \
 204         }                                                               \
 205         flush_tlb_pending();                                            \
 206         save_and_clear_fpu();                                           \
 207         /* If you are tempted to conditionalize the following */        \
 208         /* so that ASI is only written if it changes, think again. */   \
 209         __asm__ __volatile__("wr %%g0, %0, %%asi"                       \
 210         : : "r" (__thread_flag_byte_ptr(task_thread_info(next))[TI_FLAG_BYTE_CURRENT_DS]));\
 211         trap_block[current_thread_info()->cpu].thread =                 \
 212                 task_thread_info(next);                                 \
 213         __asm__ __volatile__(                                           \
 214         "mov    %%g4, %%g7\n\t"                                         \
 215         "stx    %%i6, [%%sp + 2047 + 0x70]\n\t"                         \
 216         "stx    %%i7, [%%sp + 2047 + 0x78]\n\t"                         \
 217         "rdpr   %%wstate, %%o5\n\t"                                     \
 218         "stx    %%o6, [%%g6 + %3]\n\t"                                  \
 219         "stb    %%o5, [%%g6 + %2]\n\t"                                  \
 220         "rdpr   %%cwp, %%o5\n\t"                                        \
 221         "stb    %%o5, [%%g6 + %5]\n\t"                                  \
 222         "mov    %1, %%g6\n\t"                                           \
 223         "ldub   [%1 + %5], %%g1\n\t"                                    \
 224         "wrpr   %%g1, %%cwp\n\t"                                        \
 225         "ldx    [%%g6 + %3], %%o6\n\t"                                  \
 226         "ldub   [%%g6 + %2], %%o5\n\t"                                  \
 227         "ldub   [%%g6 + %4], %%o7\n\t"                                  \
 228         "wrpr   %%o5, 0x0, %%wstate\n\t"                                \
 229         "ldx    [%%sp + 2047 + 0x70], %%i6\n\t"                         \
 230         "ldx    [%%sp + 2047 + 0x78], %%i7\n\t"                         \
 231         "ldx    [%%g6 + %6], %%g4\n\t"                                  \
 232         "brz,pt %%o7, 1f\n\t"                                           \
 233         " mov   %%g7, %0\n\t"                                           \
 234         "b,a ret_from_syscall\n\t"                                      \
 235         "1:\n\t"                                                        \
 236         : "=&r" (last)                                                  \
 237         : "0" (task_thread_info(next)),                                 \
 238           "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD),            \
 239           "i" (TI_CWP), "i" (TI_TASK)                                   \
 240         : "cc",                                                         \
 241                 "g1", "g2", "g3",                   "g7",               \
 242                       "l2", "l3", "l4", "l5", "l6", "l7",               \
 243           "i0", "i1", "i2", "i3", "i4", "i5",                           \
 244           "o0", "o1", "o2", "o3", "o4", "o5",       "o7" EXTRA_CLOBBER);\
 245         /* If you fuck with this, update ret_from_syscall code too. */  \
 246         if (test_thread_flag(TIF_PERFCTR)) {                            \
 247                 write_pcr(current_thread_info()->pcr_reg);              \
 248                 reset_pic();                                            \
 249         }                                                               \
 250 } while(0)
 251
 252 /*
 253  * On SMP systems, when the scheduler does migration-cost autodetection,
 254  * it needs a way to flush as much of the CPU's caches as possible.
 255  *
 256  * TODO: fill this in!
 257  */
 258 static inline void sched_cacheflush(void)
 259 {
 260 }
 261
 262 static inline unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val)
 263 {
 264         unsigned long tmp1, tmp2;
 265
 266         __asm__ __volatile__(
 267 "       membar          #StoreLoad | #LoadLoad\n"
 268 "       mov             %0, %1\n"
 269 "1:     lduw            [%4], %2\n"
 270 "       cas             [%4], %2, %0\n"
 271 "       cmp             %2, %0\n"
 272 "       bne,a,pn        %%icc, 1b\n"
 273 "        mov            %1, %0\n"
 274 "       membar          #StoreLoad | #StoreStore\n"
 275         : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
 276         : "0" (val), "r" (m)
 277         : "cc", "memory");
 278         return val;
 279 }
 280
 281 static inline unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val)
 282 {
 283         unsigned long tmp1, tmp2;
 284
 285         __asm__ __volatile__(
 286 "       membar          #StoreLoad | #LoadLoad\n"
 287 "       mov             %0, %1\n"
 288 "1:     ldx             [%4], %2\n"
 289 "       casx            [%4], %2, %0\n"
 290 "       cmp             %2, %0\n"
 291 "       bne,a,pn        %%xcc, 1b\n"
 292 "        mov            %1, %0\n"
 293 "       membar          #StoreLoad | #StoreStore\n"
 294         : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
 295         : "0" (val), "r" (m)
 296         : "cc", "memory");
 297         return val;
 298 }
 299
 300 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 301 #define tas(ptr) (xchg((ptr),1))
 302
 303 extern void __xchg_called_with_bad_pointer(void);
 304
 305 static __inline__ unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
 306                                        int size)
 307 {
 308         switch (size) {
 309         case 4:
 310                 return xchg32(ptr, x);
 311         case 8:
 312                 return xchg64(ptr, x);
 313         };
 314         __xchg_called_with_bad_pointer();
 315         return x;
 316 }
 317
 318 extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
 319
 320 /*
 321  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 322  * store NEW in MEM.  Return the initial value in MEM.  Success is
 323  * indicated by comparing RETURN with OLD.
 324  */
 325
 326 #define __HAVE_ARCH_CMPXCHG 1
 327
 328 static __inline__ unsigned long
 329 __cmpxchg_u32(volatile int *m, int old, int new)
 330 {
 331         __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
 332                              "cas [%2], %3, %0\n\t"
 333                              "membar #StoreLoad | #StoreStore"
 334                              : "=&r" (new)
 335                              : "0" (new), "r" (m), "r" (old)
 336                              : "memory");
 337
 338         return new;
 339 }
 340
 341 static __inline__ unsigned long
 342 __cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
 343 {
 344         __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
 345                              "casx [%2], %3, %0\n\t"
 346                              "membar #StoreLoad | #StoreStore"
 347                              : "=&r" (new)
 348                              : "0" (new), "r" (m), "r" (old)
 349                              : "memory");
 350
 351         return new;
 352 }
 353
 354 /* This function doesn't exist, so you'll get a linker error
 355    if something tries to do an invalid cmpxchg().  */
 356 extern void __cmpxchg_called_with_bad_pointer(void);
 357
 358 static __inline__ unsigned long
 359 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 360 {
 361         switch (size) {
 362                 case 4:
 363                         return __cmpxchg_u32(ptr, old, new);
 364                 case 8:
 365                         return __cmpxchg_u64(ptr, old, new);
 366         }
 367         __cmpxchg_called_with_bad_pointer();
 368         return old;
 369 }
 370
 371 #define cmpxchg(ptr,o,n)                                                 \
 372   ({                                                                     \
 373      __typeof__(*(ptr)) _o_ = (o);                                       \
 374      __typeof__(*(ptr)) _n_ = (n);                                       \
 375      (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
 376                                     (unsigned long)_n_, sizeof(*(ptr))); \
 377   })
 378
 379 #endif /* !(__ASSEMBLY__) */
 380
 381 #define arch_align_stack(x) (x)
 382
 383 #endif /* !(__SPARC64_SYSTEM_H) */