1 #ifndef _I386_PGTABLE_H
2 #define _I386_PGTABLE_H
6 * The Linux memory management assumes a three-level page table setup. On
7 * the i386, we use that, but "fold" the mid level into the top-level page
8 * table, so that we physically have the same two-level page table as the
11 * This file contains the functions and defines necessary to modify and use
12 * the i386 page table tree.
15 #include <asm/processor.h>
16 #include <asm/fixmap.h>
17 #include <linux/threads.h>
18 #include <asm/paravirt.h>
20 #include <linux/bitops.h>
21 #include <linux/slab.h>
22 #include <linux/list.h>
23 #include <linux/spinlock.h>
26 struct vm_area_struct
;
28 extern pgd_t swapper_pg_dir
[1024];
30 static inline void pgtable_cache_init(void) { }
31 static inline void check_pgt_cache(void) { }
32 void paging_init(void);
36 * The Linux x86 paging architecture is 'compile-time dual-mode', it
37 * implements both the traditional 2-level x86 page tables and the
38 * newer 3-level PAE-mode page tables.
41 # include <asm/pgtable-3level-defs.h>
42 # define PMD_SIZE (1UL << PMD_SHIFT)
43 # define PMD_MASK (~(PMD_SIZE - 1))
45 # include <asm/pgtable-2level-defs.h>
48 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
49 #define PGDIR_MASK (~(PGDIR_SIZE - 1))
51 /* Just any arbitrary offset to the start of the vmalloc VM area: the
52 * current 8MB value just means that there will be a 8MB "hole" after the
53 * physical memory until the kernel virtual memory starts. That means that
54 * any out-of-bounds memory accesses will hopefully be caught.
55 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
56 * area for the same reason. ;)
58 #define VMALLOC_OFFSET (8 * 1024 * 1024)
59 #define VMALLOC_START (((unsigned long)high_memory + 2 * VMALLOC_OFFSET - 1) \
60 & ~(VMALLOC_OFFSET - 1))
62 #define LAST_PKMAP 512
64 #define LAST_PKMAP 1024
67 #define PKMAP_BASE ((FIXADDR_BOOT_START - PAGE_SIZE * (LAST_PKMAP + 1)) \
71 # define VMALLOC_END (PKMAP_BASE - 2 * PAGE_SIZE)
73 # define VMALLOC_END (FIXADDR_START - 2 * PAGE_SIZE)
77 * Define this if things work differently on an i386 and an i486:
78 * it will (on an i486) warn about kernel memory accesses that are
79 * done without a 'access_ok(VERIFY_WRITE,..)'
83 /* The boot page tables (all created as a single array) */
84 extern unsigned long pg0
[];
86 #define pte_present(x) ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
88 /* To avoid harmful races, pmd_none(x) should check only the lower when PAE */
89 #define pmd_none(x) (!(unsigned long)pmd_val((x)))
90 #define pmd_present(x) (pmd_val((x)) & _PAGE_PRESENT)
91 #define pmd_bad(x) ((pmd_val(x) & (~PTE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
93 #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
96 # include <asm/pgtable-3level.h>
98 # include <asm/pgtable-2level.h>
102 * Macro to mark a page protection value as "uncacheable".
103 * On processors which do not support it, this is a no-op.
105 #define pgprot_noncached(prot) \
106 ((boot_cpu_data.x86 > 3) \
107 ? (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT)) \
111 * Conversion functions: convert a page and protection to a page entry,
112 * and a page entry and page directory to the page they refer to.
114 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
117 * the pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD]
119 * this macro returns the index of the entry in the pgd page which would
120 * control the given virtual address
122 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
123 #define pgd_index_k(addr) pgd_index((addr))
126 * pgd_offset() returns a (pgd_t *)
127 * pgd_index() is used get the offset into the pgd page's array of pgd_t's;
129 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index((address)))
132 * a shortcut which implies the use of the kernel's pgd, instead
135 #define pgd_offset_k(address) pgd_offset(&init_mm, (address))
137 static inline int pud_large(pud_t pud
) { return 0; }
140 * the pmd page can be thought of an array like this: pmd_t[PTRS_PER_PMD]
142 * this macro returns the index of the entry in the pmd page which would
143 * control the given virtual address
145 #define pmd_index(address) \
146 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
149 * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
151 * this macro returns the index of the entry in the pte page which would
152 * control the given virtual address
154 #define pte_index(address) \
155 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
156 #define pte_offset_kernel(dir, address) \
157 ((pte_t *)pmd_page_vaddr(*(dir)) + pte_index((address)))
159 #define pmd_page(pmd) (pfn_to_page(pmd_val((pmd)) >> PAGE_SHIFT))
161 #define pmd_page_vaddr(pmd) \
162 ((unsigned long)__va(pmd_val((pmd)) & PTE_MASK))
164 #if defined(CONFIG_HIGHPTE)
165 #define pte_offset_map(dir, address) \
166 ((pte_t *)kmap_atomic_pte(pmd_page(*(dir)), KM_PTE0) + \
167 pte_index((address)))
168 #define pte_offset_map_nested(dir, address) \
169 ((pte_t *)kmap_atomic_pte(pmd_page(*(dir)), KM_PTE1) + \
170 pte_index((address)))
171 #define pte_unmap(pte) kunmap_atomic((pte), KM_PTE0)
172 #define pte_unmap_nested(pte) kunmap_atomic((pte), KM_PTE1)
174 #define pte_offset_map(dir, address) \
175 ((pte_t *)page_address(pmd_page(*(dir))) + pte_index((address)))
176 #define pte_offset_map_nested(dir, address) pte_offset_map((dir), (address))
177 #define pte_unmap(pte) do { } while (0)
178 #define pte_unmap_nested(pte) do { } while (0)
181 /* Clear a kernel PTE and flush it from the TLB */
182 #define kpte_clear_flush(ptep, vaddr) \
184 pte_clear(&init_mm, (vaddr), (ptep)); \
185 __flush_tlb_one((vaddr)); \
189 * The i386 doesn't have any external MMU info: the kernel page
190 * tables contain all the necessary information.
192 #define update_mmu_cache(vma, address, pte) do { } while (0)
194 extern void native_pagetable_setup_start(pgd_t
*base
);
195 extern void native_pagetable_setup_done(pgd_t
*base
);
197 #ifndef CONFIG_PARAVIRT
198 static inline void __init
paravirt_pagetable_setup_start(pgd_t
*base
)
200 native_pagetable_setup_start(base
);
203 static inline void __init
paravirt_pagetable_setup_done(pgd_t
*base
)
205 native_pagetable_setup_done(base
);
207 #endif /* !CONFIG_PARAVIRT */
209 #endif /* !__ASSEMBLY__ */
212 * kern_addr_valid() is (1) for FLATMEM and (0) for
213 * SPARSEMEM and DISCONTIGMEM
215 #ifdef CONFIG_FLATMEM
216 #define kern_addr_valid(addr) (1)
218 #define kern_addr_valid(kaddr) (0)
221 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
222 remap_pfn_range(vma, vaddr, pfn, size, prot)
224 #endif /* _I386_PGTABLE_H */